1 ; RUN: llc -march=mipsel -mcpu=mips2 < %s | FileCheck %s
4 declare i32 @llvm.atomic.load.add.i32.p0i32(i32* nocapture, i32) nounwind
5 declare i32 @llvm.atomic.load.nand.i32.p0i32(i32* nocapture, i32) nounwind
6 declare i32 @llvm.atomic.swap.i32.p0i32(i32* nocapture, i32) nounwind
7 declare i32 @llvm.atomic.cmp.swap.i32.p0i32(i32* nocapture, i32, i32) nounwind
9 declare i8 @llvm.atomic.load.add.i8.p0i8(i8* nocapture, i8) nounwind
10 declare i8 @llvm.atomic.load.sub.i8.p0i8(i8* nocapture, i8) nounwind
11 declare i8 @llvm.atomic.load.nand.i8.p0i8(i8* nocapture, i8) nounwind
12 declare i8 @llvm.atomic.swap.i8.p0i8(i8* nocapture, i8) nounwind
13 declare i8 @llvm.atomic.cmp.swap.i8.p0i8(i8* nocapture, i8, i8) nounwind
16 @x = common global i32 0, align 4
18 define i32 @AtomicLoadAdd32(i32 %incr) nounwind {
20 %0 = call i32 @llvm.atomic.load.add.i32.p0i32(i32* @x, i32 %incr)
23 ; CHECK: AtomicLoadAdd32:
24 ; CHECK: lw $[[R0:[0-9]+]], %got(x)($gp)
25 ; CHECK: $[[BB0:[A-Z_0-9]+]]:
26 ; CHECK: ll $[[R1:[0-9]+]], 0($[[R0]])
27 ; CHECK: addu $[[R2:[0-9]+]], $[[R1]], $4
28 ; CHECK: sc $[[R2]], 0($[[R0]])
29 ; CHECK: beq $[[R2]], $zero, $[[BB0]]
32 define i32 @AtomicLoadNand32(i32 %incr) nounwind {
34 %0 = call i32 @llvm.atomic.load.nand.i32.p0i32(i32* @x, i32 %incr)
37 ; CHECK: AtomicLoadNand32:
38 ; CHECK: lw $[[R0:[0-9]+]], %got(x)($gp)
39 ; CHECK: $[[BB0:[A-Z_0-9]+]]:
40 ; CHECK: ll $[[R1:[0-9]+]], 0($[[R0]])
41 ; CHECK: and $[[R3:[0-9]+]], $[[R1]], $4
42 ; CHECK: nor $[[R2:[0-9]+]], $zero, $[[R3]]
43 ; CHECK: sc $[[R2]], 0($[[R0]])
44 ; CHECK: beq $[[R2]], $zero, $[[BB0]]
47 define i32 @AtomicSwap32(i32 %newval) nounwind {
49 %newval.addr = alloca i32, align 4
50 store i32 %newval, i32* %newval.addr, align 4
51 %tmp = load i32* %newval.addr, align 4
52 %0 = call i32 @llvm.atomic.swap.i32.p0i32(i32* @x, i32 %tmp)
55 ; CHECK: AtomicSwap32:
56 ; CHECK: lw $[[R0:[0-9]+]], %got(x)($gp)
57 ; CHECK: $[[BB0:[A-Z_0-9]+]]:
58 ; CHECK: ll ${{[0-9]+}}, 0($[[R0]])
59 ; CHECK: sc $[[R2:[0-9]+]], 0($[[R0]])
60 ; CHECK: beq $[[R2]], $zero, $[[BB0]]
63 define i32 @AtomicCmpSwap32(i32 %oldval, i32 %newval) nounwind {
65 %newval.addr = alloca i32, align 4
66 store i32 %newval, i32* %newval.addr, align 4
67 %tmp = load i32* %newval.addr, align 4
68 %0 = call i32 @llvm.atomic.cmp.swap.i32.p0i32(i32* @x, i32 %oldval, i32 %tmp)
71 ; CHECK: AtomicCmpSwap32:
72 ; CHECK: lw $[[R0:[0-9]+]], %got(x)($gp)
73 ; CHECK: $[[BB0:[A-Z_0-9]+]]:
74 ; CHECK: ll $2, 0($[[R0]])
75 ; CHECK: bne $2, $4, $[[BB1:[A-Z_0-9]+]]
76 ; CHECK: or $[[R2:[0-9]+]], $zero, $5
77 ; CHECK: sc $[[R2]], 0($[[R0]])
78 ; CHECK: beq $[[R2]], $zero, $[[BB0]]
84 @y = common global i8 0, align 1
86 define signext i8 @AtomicLoadAdd8(i8 signext %incr) nounwind {
88 %0 = call i8 @llvm.atomic.load.add.i8.p0i8(i8* @y, i8 %incr)
91 ; CHECK: AtomicLoadAdd8:
92 ; CHECK: lw $[[R0:[0-9]+]], %got(y)($gp)
93 ; CHECK: addiu $[[R1:[0-9]+]], $zero, -4
94 ; CHECK: and $[[R2:[0-9]+]], $[[R0]], $[[R1]]
95 ; CHECK: andi $[[R3:[0-9]+]], $[[R0]], 3
96 ; CHECK: sll $[[R4:[0-9]+]], $[[R3]], 3
97 ; CHECK: ori $[[R5:[0-9]+]], $zero, 255
98 ; CHECK: sll $[[R6:[0-9]+]], $[[R5]], $[[R4]]
99 ; CHECK: nor $[[R7:[0-9]+]], $zero, $[[R6]]
100 ; CHECK: andi $[[R8:[0-9]+]], $4, 255
101 ; CHECK: sll $[[R9:[0-9]+]], $[[R8]], $[[R4]]
103 ; CHECK: $[[BB0:[A-Z_0-9]+]]:
104 ; CHECK: ll $[[R10:[0-9]+]], 0($[[R2]])
105 ; CHECK: addu $[[R11:[0-9]+]], $[[R10]], $[[R9]]
106 ; CHECK: and $[[R12:[0-9]+]], $[[R11]], $[[R6]]
107 ; CHECK: and $[[R13:[0-9]+]], $[[R10]], $[[R7]]
108 ; CHECK: or $[[R14:[0-9]+]], $[[R13]], $[[R12]]
109 ; CHECK: sc $[[R14]], 0($[[R2]])
110 ; CHECK: beq $[[R14]], $zero, $[[BB0]]
112 ; CHECK: and $[[R15:[0-9]+]], $[[R10]], $[[R6]]
113 ; CHECK: srl $[[R16:[0-9]+]], $[[R15]], $[[R4]]
114 ; CHECK: sll $[[R17:[0-9]+]], $[[R16]], 24
115 ; CHECK: sra $2, $[[R17]], 24
118 define signext i8 @AtomicLoadSub8(i8 signext %incr) nounwind {
120 %0 = call i8 @llvm.atomic.load.sub.i8.p0i8(i8* @y, i8 %incr)
123 ; CHECK: AtomicLoadSub8:
124 ; CHECK: lw $[[R0:[0-9]+]], %got(y)($gp)
125 ; CHECK: addiu $[[R1:[0-9]+]], $zero, -4
126 ; CHECK: and $[[R2:[0-9]+]], $[[R0]], $[[R1]]
127 ; CHECK: andi $[[R3:[0-9]+]], $[[R0]], 3
128 ; CHECK: sll $[[R4:[0-9]+]], $[[R3]], 3
129 ; CHECK: ori $[[R5:[0-9]+]], $zero, 255
130 ; CHECK: sll $[[R6:[0-9]+]], $[[R5]], $[[R4]]
131 ; CHECK: nor $[[R7:[0-9]+]], $zero, $[[R6]]
132 ; CHECK: subu $[[R18:[0-9]+]], $zero, $4
133 ; CHECK: andi $[[R8:[0-9]+]], $[[R18]], 255
134 ; CHECK: sll $[[R9:[0-9]+]], $[[R8]], $[[R4]]
136 ; CHECK: $[[BB0:[A-Z_0-9]+]]:
137 ; CHECK: ll $[[R10:[0-9]+]], 0($[[R2]])
138 ; CHECK: addu $[[R11:[0-9]+]], $[[R10]], $[[R9]]
139 ; CHECK: and $[[R12:[0-9]+]], $[[R11]], $[[R6]]
140 ; CHECK: and $[[R13:[0-9]+]], $[[R10]], $[[R7]]
141 ; CHECK: or $[[R14:[0-9]+]], $[[R13]], $[[R12]]
142 ; CHECK: sc $[[R14]], 0($[[R2]])
143 ; CHECK: beq $[[R14]], $zero, $[[BB0]]
145 ; CHECK: and $[[R15:[0-9]+]], $[[R10]], $[[R6]]
146 ; CHECK: srl $[[R16:[0-9]+]], $[[R15]], $[[R4]]
147 ; CHECK: sll $[[R17:[0-9]+]], $[[R16]], 24
148 ; CHECK: sra $2, $[[R17]], 24
151 define signext i8 @AtomicLoadNand8(i8 signext %incr) nounwind {
153 %0 = call i8 @llvm.atomic.load.nand.i8.p0i8(i8* @y, i8 %incr)
156 ; CHECK: AtomicLoadNand8:
157 ; CHECK: lw $[[R0:[0-9]+]], %got(y)($gp)
158 ; CHECK: addiu $[[R1:[0-9]+]], $zero, -4
159 ; CHECK: and $[[R2:[0-9]+]], $[[R0]], $[[R1]]
160 ; CHECK: andi $[[R3:[0-9]+]], $[[R0]], 3
161 ; CHECK: sll $[[R4:[0-9]+]], $[[R3]], 3
162 ; CHECK: ori $[[R5:[0-9]+]], $zero, 255
163 ; CHECK: sll $[[R6:[0-9]+]], $[[R5]], $[[R4]]
164 ; CHECK: nor $[[R7:[0-9]+]], $zero, $[[R6]]
165 ; CHECK: andi $[[R8:[0-9]+]], $4, 255
166 ; CHECK: sll $[[R9:[0-9]+]], $[[R8]], $[[R4]]
168 ; CHECK: $[[BB0:[A-Z_0-9]+]]:
169 ; CHECK: ll $[[R10:[0-9]+]], 0($[[R2]])
170 ; CHECK: and $[[R18:[0-9]+]], $[[R10]], $[[R9]]
171 ; CHECK: nor $[[R11:[0-9]+]], $zero, $[[R18]]
172 ; CHECK: and $[[R12:[0-9]+]], $[[R11]], $[[R6]]
173 ; CHECK: and $[[R13:[0-9]+]], $[[R10]], $[[R7]]
174 ; CHECK: or $[[R14:[0-9]+]], $[[R13]], $[[R12]]
175 ; CHECK: sc $[[R14]], 0($[[R2]])
176 ; CHECK: beq $[[R14]], $zero, $[[BB0]]
178 ; CHECK: and $[[R15:[0-9]+]], $[[R10]], $[[R6]]
179 ; CHECK: srl $[[R16:[0-9]+]], $[[R15]], $[[R4]]
180 ; CHECK: sll $[[R17:[0-9]+]], $[[R16]], 24
181 ; CHECK: sra $2, $[[R17]], 24
184 define signext i8 @AtomicSwap8(i8 signext %newval) nounwind {
186 %0 = call i8 @llvm.atomic.swap.i8.p0i8(i8* @y, i8 %newval)
189 ; CHECK: AtomicSwap8:
190 ; CHECK: lw $[[R0:[0-9]+]], %got(y)($gp)
191 ; CHECK: addiu $[[R1:[0-9]+]], $zero, -4
192 ; CHECK: and $[[R2:[0-9]+]], $[[R0]], $[[R1]]
193 ; CHECK: andi $[[R3:[0-9]+]], $[[R0]], 3
194 ; CHECK: sll $[[R4:[0-9]+]], $[[R3]], 3
195 ; CHECK: ori $[[R5:[0-9]+]], $zero, 255
196 ; CHECK: sll $[[R6:[0-9]+]], $[[R5]], $[[R4]]
197 ; CHECK: nor $[[R7:[0-9]+]], $zero, $[[R6]]
198 ; CHECK: andi $[[R8:[0-9]+]], $4, 255
199 ; CHECK: sll $[[R9:[0-9]+]], $[[R8]], $[[R4]]
201 ; CHECK: $[[BB0:[A-Z_0-9]+]]:
202 ; CHECK: ll $[[R10:[0-9]+]], 0($[[R2]])
203 ; CHECK: and $[[R13:[0-9]+]], $[[R10]], $[[R7]]
204 ; CHECK: or $[[R14:[0-9]+]], $[[R13]], $[[R9]]
205 ; CHECK: sc $[[R14]], 0($[[R2]])
206 ; CHECK: beq $[[R14]], $zero, $[[BB0]]
208 ; CHECK: and $[[R15:[0-9]+]], $[[R10]], $[[R6]]
209 ; CHECK: srl $[[R16:[0-9]+]], $[[R15]], $[[R4]]
210 ; CHECK: sll $[[R17:[0-9]+]], $[[R16]], 24
211 ; CHECK: sra $2, $[[R17]], 24
214 define signext i8 @AtomicCmpSwap8(i8 signext %oldval, i8 signext %newval) nounwind {
216 %0 = call i8 @llvm.atomic.cmp.swap.i8.p0i8(i8* @y, i8 %oldval, i8 %newval)
219 ; CHECK: AtomicCmpSwap8:
220 ; CHECK: lw $[[R0:[0-9]+]], %got(y)($gp)
221 ; CHECK: addiu $[[R1:[0-9]+]], $zero, -4
222 ; CHECK: and $[[R2:[0-9]+]], $[[R0]], $[[R1]]
223 ; CHECK: andi $[[R3:[0-9]+]], $[[R0]], 3
224 ; CHECK: sll $[[R4:[0-9]+]], $[[R3]], 3
225 ; CHECK: ori $[[R5:[0-9]+]], $zero, 255
226 ; CHECK: sll $[[R6:[0-9]+]], $[[R5]], $[[R4]]
227 ; CHECK: nor $[[R7:[0-9]+]], $zero, $[[R6]]
228 ; CHECK: andi $[[R8:[0-9]+]], $4, 255
229 ; CHECK: sll $[[R9:[0-9]+]], $[[R8]], $[[R4]]
230 ; CHECK: andi $[[R10:[0-9]+]], $5, 255
231 ; CHECK: sll $[[R11:[0-9]+]], $[[R10]], $[[R4]]
233 ; CHECK: $[[BB0:[A-Z_0-9]+]]:
234 ; CHECK: ll $[[R12:[0-9]+]], 0($[[R2]])
235 ; CHECK: and $[[R13:[0-9]+]], $[[R12]], $[[R6]]
236 ; CHECK: bne $[[R13]], $[[R9]], $[[BB1:[A-Z_0-9]+]]
238 ; CHECK: and $[[R14:[0-9]+]], $[[R12]], $[[R7]]
239 ; CHECK: or $[[R15:[0-9]+]], $[[R14]], $[[R11]]
240 ; CHECK: sc $[[R15]], 0($[[R2]])
241 ; CHECK: beq $[[R15]], $zero, $[[BB0]]
244 ; CHECK: srl $[[R16:[0-9]+]], $[[R13]], $[[R4]]
245 ; CHECK: sll $[[R17:[0-9]+]], $[[R16]], 24
246 ; CHECK: sra $2, $[[R17]], 24