1 ; RUN: llc -march=mips -mattr=dsp < %s | FileCheck %s -check-prefix=R1
2 ; RUN: llc -march=mips -mattr=dspr2 < %s | FileCheck %s -check-prefix=R2
7 define zeroext i8 @test_lbux(i8* nocapture %b, i32 %i) {
9 %add.ptr = getelementptr inbounds i8* %b, i32 %i
10 %0 = load i8* %add.ptr, align 1
17 define signext i16 @test_lhx(i16* nocapture %b, i32 %i) {
19 %add.ptr = getelementptr inbounds i16* %b, i32 %i
20 %0 = load i16* %add.ptr, align 2
27 define i32 @test_lwx(i32* nocapture %b, i32 %i) {
29 %add.ptr = getelementptr inbounds i32* %b, i32 %i
30 %0 = load i32* %add.ptr, align 4
34 ; R1: test_add_v2q15_:
35 ; R1: addq.ph ${{[0-9]+}}
37 define { i32 } @test_add_v2q15_(i32 %a.coerce, i32 %b.coerce) {
39 %0 = bitcast i32 %a.coerce to <2 x i16>
40 %1 = bitcast i32 %b.coerce to <2 x i16>
41 %add = add <2 x i16> %0, %1
42 %2 = bitcast <2 x i16> %add to i32
43 %.fca.0.insert = insertvalue { i32 } undef, i32 %2, 0
44 ret { i32 } %.fca.0.insert
47 ; R1: test_sub_v2q15_:
48 ; R1: subq.ph ${{[0-9]+}}
50 define { i32 } @test_sub_v2q15_(i32 %a.coerce, i32 %b.coerce) {
52 %0 = bitcast i32 %a.coerce to <2 x i16>
53 %1 = bitcast i32 %b.coerce to <2 x i16>
54 %sub = sub <2 x i16> %0, %1
55 %2 = bitcast <2 x i16> %sub to i32
56 %.fca.0.insert = insertvalue { i32 } undef, i32 %2, 0
57 ret { i32 } %.fca.0.insert
60 ; R2: test_mul_v2q15_:
61 ; R2: mul.ph ${{[0-9]+}}
63 ; mul.ph is an R2 instruction. Check that multiply node gets expanded.
64 ; R1: test_mul_v2q15_:
68 define { i32 } @test_mul_v2q15_(i32 %a.coerce, i32 %b.coerce) {
70 %0 = bitcast i32 %a.coerce to <2 x i16>
71 %1 = bitcast i32 %b.coerce to <2 x i16>
72 %mul = mul <2 x i16> %0, %1
73 %2 = bitcast <2 x i16> %mul to i32
74 %.fca.0.insert = insertvalue { i32 } undef, i32 %2, 0
75 ret { i32 } %.fca.0.insert
79 ; R1: addu.qb ${{[0-9]+}}
81 define { i32 } @test_add_v4i8_(i32 %a.coerce, i32 %b.coerce) {
83 %0 = bitcast i32 %a.coerce to <4 x i8>
84 %1 = bitcast i32 %b.coerce to <4 x i8>
85 %add = add <4 x i8> %0, %1
86 %2 = bitcast <4 x i8> %add to i32
87 %.fca.0.insert = insertvalue { i32 } undef, i32 %2, 0
88 ret { i32 } %.fca.0.insert
92 ; R1: subu.qb ${{[0-9]+}}
94 define { i32 } @test_sub_v4i8_(i32 %a.coerce, i32 %b.coerce) {
96 %0 = bitcast i32 %a.coerce to <4 x i8>
97 %1 = bitcast i32 %b.coerce to <4 x i8>
98 %sub = sub <4 x i8> %0, %1
99 %2 = bitcast <4 x i8> %sub to i32
100 %.fca.0.insert = insertvalue { i32 } undef, i32 %2, 0
101 ret { i32 } %.fca.0.insert
104 ; DSP-ASE doesn't have a v4i8 multiply instruction. Check that multiply node gets expanded.
105 ; R2: test_mul_v4i8_:
106 ; R2: mul ${{[0-9]+}}
107 ; R2: mul ${{[0-9]+}}
108 ; R2: mul ${{[0-9]+}}
109 ; R2: mul ${{[0-9]+}}
111 define { i32 } @test_mul_v4i8_(i32 %a.coerce, i32 %b.coerce) {
113 %0 = bitcast i32 %a.coerce to <4 x i8>
114 %1 = bitcast i32 %b.coerce to <4 x i8>
115 %mul = mul <4 x i8> %0, %1
116 %2 = bitcast <4 x i8> %mul to i32
117 %.fca.0.insert = insertvalue { i32 } undef, i32 %2, 0
118 ret { i32 } %.fca.0.insert