1 ; RUN: llc -march=mipsel -mattr=+dsp < %s | FileCheck %s
3 define i32 @test__builtin_mips_extr_w1(i32 %i0, i32, i64 %a0) nounwind {
7 %1 = tail call i32 @llvm.mips.extr.w(i64 %a0, i32 15)
11 declare i32 @llvm.mips.extr.w(i64, i32) nounwind
13 define i32 @test__builtin_mips_extr_w2(i32 %i0, i32, i64 %a0, i32 %a1) nounwind {
17 %1 = tail call i32 @llvm.mips.extr.w(i64 %a0, i32 %a1)
21 define i32 @test__builtin_mips_extr_r_w1(i32 %i0, i32, i64 %a0) nounwind {
25 %1 = tail call i32 @llvm.mips.extr.r.w(i64 %a0, i32 15)
29 declare i32 @llvm.mips.extr.r.w(i64, i32) nounwind
31 define i32 @test__builtin_mips_extr_s_h1(i32 %i0, i32, i64 %a0, i32 %a1) nounwind {
35 %1 = tail call i32 @llvm.mips.extr.s.h(i64 %a0, i32 %a1)
39 declare i32 @llvm.mips.extr.s.h(i64, i32) nounwind
41 define i32 @test__builtin_mips_extr_rs_w1(i32 %i0, i32, i64 %a0) nounwind {
45 %1 = tail call i32 @llvm.mips.extr.rs.w(i64 %a0, i32 15)
49 declare i32 @llvm.mips.extr.rs.w(i64, i32) nounwind
51 define i32 @test__builtin_mips_extr_rs_w2(i32 %i0, i32, i64 %a0, i32 %a1) nounwind {
55 %1 = tail call i32 @llvm.mips.extr.rs.w(i64 %a0, i32 %a1)
59 define i32 @test__builtin_mips_extr_s_h2(i32 %i0, i32, i64 %a0) nounwind {
63 %1 = tail call i32 @llvm.mips.extr.s.h(i64 %a0, i32 15)
67 define i32 @test__builtin_mips_extr_r_w2(i32 %i0, i32, i64 %a0, i32 %a1) nounwind {
71 %1 = tail call i32 @llvm.mips.extr.r.w(i64 %a0, i32 %a1)
75 define i32 @test__builtin_mips_extp1(i32 %i0, i32, i64 %a0) nounwind {
79 %1 = tail call i32 @llvm.mips.extp(i64 %a0, i32 15)
83 declare i32 @llvm.mips.extp(i64, i32) nounwind
85 define i32 @test__builtin_mips_extp2(i32 %i0, i32, i64 %a0, i32 %a1) nounwind {
89 %1 = tail call i32 @llvm.mips.extp(i64 %a0, i32 %a1)
93 define i32 @test__builtin_mips_extpdp1(i32 %i0, i32, i64 %a0) nounwind {
97 %1 = tail call i32 @llvm.mips.extpdp(i64 %a0, i32 15)
101 declare i32 @llvm.mips.extpdp(i64, i32) nounwind
103 define i32 @test__builtin_mips_extpdp2(i32 %i0, i32, i64 %a0, i32 %a1) nounwind {
107 %1 = tail call i32 @llvm.mips.extpdp(i64 %a0, i32 %a1)
111 define i64 @test__builtin_mips_dpau_h_qbl1(i32 %i0, i32, i64 %a0, i32 %a1.coerce, i32 %a2.coerce) nounwind readnone {
115 %1 = bitcast i32 %a1.coerce to <4 x i8>
116 %2 = bitcast i32 %a2.coerce to <4 x i8>
117 %3 = tail call i64 @llvm.mips.dpau.h.qbl(i64 %a0, <4 x i8> %1, <4 x i8> %2)
121 declare i64 @llvm.mips.dpau.h.qbl(i64, <4 x i8>, <4 x i8>) nounwind readnone
123 define i64 @test__builtin_mips_dpau_h_qbr1(i32 %i0, i32, i64 %a0, i32 %a1.coerce, i32 %a2.coerce) nounwind readnone {
127 %1 = bitcast i32 %a1.coerce to <4 x i8>
128 %2 = bitcast i32 %a2.coerce to <4 x i8>
129 %3 = tail call i64 @llvm.mips.dpau.h.qbr(i64 %a0, <4 x i8> %1, <4 x i8> %2)
133 declare i64 @llvm.mips.dpau.h.qbr(i64, <4 x i8>, <4 x i8>) nounwind readnone
135 define i64 @test__builtin_mips_dpsu_h_qbl1(i32 %i0, i32, i64 %a0, i32 %a1.coerce, i32 %a2.coerce) nounwind readnone {
139 %1 = bitcast i32 %a1.coerce to <4 x i8>
140 %2 = bitcast i32 %a2.coerce to <4 x i8>
141 %3 = tail call i64 @llvm.mips.dpsu.h.qbl(i64 %a0, <4 x i8> %1, <4 x i8> %2)
145 declare i64 @llvm.mips.dpsu.h.qbl(i64, <4 x i8>, <4 x i8>) nounwind readnone
147 define i64 @test__builtin_mips_dpsu_h_qbr1(i32 %i0, i32, i64 %a0, i32 %a1.coerce, i32 %a2.coerce) nounwind readnone {
151 %1 = bitcast i32 %a1.coerce to <4 x i8>
152 %2 = bitcast i32 %a2.coerce to <4 x i8>
153 %3 = tail call i64 @llvm.mips.dpsu.h.qbr(i64 %a0, <4 x i8> %1, <4 x i8> %2)
157 declare i64 @llvm.mips.dpsu.h.qbr(i64, <4 x i8>, <4 x i8>) nounwind readnone
159 define i64 @test__builtin_mips_dpaq_s_w_ph1(i32 %i0, i32, i64 %a0, i32 %a1.coerce, i32 %a2.coerce) nounwind {
163 %1 = bitcast i32 %a1.coerce to <2 x i16>
164 %2 = bitcast i32 %a2.coerce to <2 x i16>
165 %3 = tail call i64 @llvm.mips.dpaq.s.w.ph(i64 %a0, <2 x i16> %1, <2 x i16> %2)
169 declare i64 @llvm.mips.dpaq.s.w.ph(i64, <2 x i16>, <2 x i16>) nounwind
171 define i64 @test__builtin_mips_dpaq_sa_l_w1(i32 %i0, i32, i64 %a0, i32 %a1, i32 %a2) nounwind {
175 %1 = tail call i64 @llvm.mips.dpaq.sa.l.w(i64 %a0, i32 %a1, i32 %a2)
179 declare i64 @llvm.mips.dpaq.sa.l.w(i64, i32, i32) nounwind
181 define i64 @test__builtin_mips_dpsq_s_w_ph1(i32 %i0, i32, i64 %a0, i32 %a1.coerce, i32 %a2.coerce) nounwind {
185 %1 = bitcast i32 %a1.coerce to <2 x i16>
186 %2 = bitcast i32 %a2.coerce to <2 x i16>
187 %3 = tail call i64 @llvm.mips.dpsq.s.w.ph(i64 %a0, <2 x i16> %1, <2 x i16> %2)
191 declare i64 @llvm.mips.dpsq.s.w.ph(i64, <2 x i16>, <2 x i16>) nounwind
193 define i64 @test__builtin_mips_dpsq_sa_l_w1(i32 %i0, i32, i64 %a0, i32 %a1, i32 %a2) nounwind {
197 %1 = tail call i64 @llvm.mips.dpsq.sa.l.w(i64 %a0, i32 %a1, i32 %a2)
201 declare i64 @llvm.mips.dpsq.sa.l.w(i64, i32, i32) nounwind
203 define i64 @test__builtin_mips_mulsaq_s_w_ph1(i32 %i0, i32, i64 %a0, i32 %a1.coerce, i32 %a2.coerce) nounwind {
205 ; CHECK: mulsaq_s.w.ph
207 %1 = bitcast i32 %a1.coerce to <2 x i16>
208 %2 = bitcast i32 %a2.coerce to <2 x i16>
209 %3 = tail call i64 @llvm.mips.mulsaq.s.w.ph(i64 %a0, <2 x i16> %1, <2 x i16> %2)
213 declare i64 @llvm.mips.mulsaq.s.w.ph(i64, <2 x i16>, <2 x i16>) nounwind
215 define i64 @test__builtin_mips_maq_s_w_phl1(i32 %i0, i32, i64 %a0, i32 %a1.coerce, i32 %a2.coerce) nounwind {
219 %1 = bitcast i32 %a1.coerce to <2 x i16>
220 %2 = bitcast i32 %a2.coerce to <2 x i16>
221 %3 = tail call i64 @llvm.mips.maq.s.w.phl(i64 %a0, <2 x i16> %1, <2 x i16> %2)
225 declare i64 @llvm.mips.maq.s.w.phl(i64, <2 x i16>, <2 x i16>) nounwind
227 define i64 @test__builtin_mips_maq_s_w_phr1(i32 %i0, i32, i64 %a0, i32 %a1.coerce, i32 %a2.coerce) nounwind {
231 %1 = bitcast i32 %a1.coerce to <2 x i16>
232 %2 = bitcast i32 %a2.coerce to <2 x i16>
233 %3 = tail call i64 @llvm.mips.maq.s.w.phr(i64 %a0, <2 x i16> %1, <2 x i16> %2)
237 declare i64 @llvm.mips.maq.s.w.phr(i64, <2 x i16>, <2 x i16>) nounwind
239 define i64 @test__builtin_mips_maq_sa_w_phl1(i32 %i0, i32, i64 %a0, i32 %a1.coerce, i32 %a2.coerce) nounwind {
241 ; CHECK: maq_sa.w.phl
243 %1 = bitcast i32 %a1.coerce to <2 x i16>
244 %2 = bitcast i32 %a2.coerce to <2 x i16>
245 %3 = tail call i64 @llvm.mips.maq.sa.w.phl(i64 %a0, <2 x i16> %1, <2 x i16> %2)
249 declare i64 @llvm.mips.maq.sa.w.phl(i64, <2 x i16>, <2 x i16>) nounwind
251 define i64 @test__builtin_mips_maq_sa_w_phr1(i32 %i0, i32, i64 %a0, i32 %a1.coerce, i32 %a2.coerce) nounwind {
253 ; CHECK: maq_sa.w.phr
255 %1 = bitcast i32 %a1.coerce to <2 x i16>
256 %2 = bitcast i32 %a2.coerce to <2 x i16>
257 %3 = tail call i64 @llvm.mips.maq.sa.w.phr(i64 %a0, <2 x i16> %1, <2 x i16> %2)
261 declare i64 @llvm.mips.maq.sa.w.phr(i64, <2 x i16>, <2 x i16>) nounwind
263 define i64 @test__builtin_mips_shilo1(i32 %i0, i32, i64 %a0) nounwind readnone {
267 %1 = tail call i64 @llvm.mips.shilo(i64 %a0, i32 0)
271 declare i64 @llvm.mips.shilo(i64, i32) nounwind readnone
273 define i64 @test__builtin_mips_shilo2(i32 %i0, i32, i64 %a0, i32 %a1) nounwind readnone {
277 %1 = tail call i64 @llvm.mips.shilo(i64 %a0, i32 %a1)
281 define i64 @test__builtin_mips_mthlip1(i32 %i0, i32, i64 %a0, i32 %a1) nounwind {
285 %1 = tail call i64 @llvm.mips.mthlip(i64 %a0, i32 %a1)
289 declare i64 @llvm.mips.mthlip(i64, i32) nounwind
291 define i32 @test__builtin_mips_bposge321(i32 %i0) nounwind readonly {
295 %0 = tail call i32 @llvm.mips.bposge32()
299 declare i32 @llvm.mips.bposge32() nounwind readonly
301 define i64 @test__builtin_mips_madd1(i32 %i0, i32, i64 %a0, i32 %a1, i32 %a2) nounwind readnone {
305 %1 = tail call i64 @llvm.mips.madd(i64 %a0, i32 %a1, i32 %a2)
309 declare i64 @llvm.mips.madd(i64, i32, i32) nounwind readnone
311 define i64 @test__builtin_mips_maddu1(i32 %i0, i32, i64 %a0, i32 %a1, i32 %a2) nounwind readnone {
315 %1 = tail call i64 @llvm.mips.maddu(i64 %a0, i32 %a1, i32 %a2)
319 declare i64 @llvm.mips.maddu(i64, i32, i32) nounwind readnone
321 define i64 @test__builtin_mips_msub1(i32 %i0, i32, i64 %a0, i32 %a1, i32 %a2) nounwind readnone {
325 %1 = tail call i64 @llvm.mips.msub(i64 %a0, i32 %a1, i32 %a2)
329 declare i64 @llvm.mips.msub(i64, i32, i32) nounwind readnone
331 define i64 @test__builtin_mips_msubu1(i32 %i0, i32, i64 %a0, i32 %a1, i32 %a2) nounwind readnone {
335 %1 = tail call i64 @llvm.mips.msubu(i64 %a0, i32 %a1, i32 %a2)
339 declare i64 @llvm.mips.msubu(i64, i32, i32) nounwind readnone
341 define i64 @test__builtin_mips_mult1(i32 %i0, i32 %a0, i32 %a1) nounwind readnone {
345 %0 = tail call i64 @llvm.mips.mult(i32 %a0, i32 %a1)
349 declare i64 @llvm.mips.mult(i32, i32) nounwind readnone
351 define i64 @test__builtin_mips_multu1(i32 %i0, i32 %a0, i32 %a1) nounwind readnone {
355 %0 = tail call i64 @llvm.mips.multu(i32 %a0, i32 %a1)
359 declare i64 @llvm.mips.multu(i32, i32) nounwind readnone
361 define { i32 } @test__builtin_mips_addq_ph1(i32 %i0, i32 %a0.coerce, i32 %a1.coerce) nounwind {
365 %0 = bitcast i32 %a0.coerce to <2 x i16>
366 %1 = bitcast i32 %a1.coerce to <2 x i16>
367 %2 = tail call <2 x i16> @llvm.mips.addq.ph(<2 x i16> %0, <2 x i16> %1)
368 %3 = bitcast <2 x i16> %2 to i32
369 %.fca.0.insert = insertvalue { i32 } undef, i32 %3, 0
370 ret { i32 } %.fca.0.insert
373 declare <2 x i16> @llvm.mips.addq.ph(<2 x i16>, <2 x i16>) nounwind
375 define { i32 } @test__builtin_mips_addq_s_ph1(i32 %i0, i32 %a0.coerce, i32 %a1.coerce) nounwind {
379 %0 = bitcast i32 %a0.coerce to <2 x i16>
380 %1 = bitcast i32 %a1.coerce to <2 x i16>
381 %2 = tail call <2 x i16> @llvm.mips.addq.s.ph(<2 x i16> %0, <2 x i16> %1)
382 %3 = bitcast <2 x i16> %2 to i32
383 %.fca.0.insert = insertvalue { i32 } undef, i32 %3, 0
384 ret { i32 } %.fca.0.insert
387 declare <2 x i16> @llvm.mips.addq.s.ph(<2 x i16>, <2 x i16>) nounwind
389 define i32 @test__builtin_mips_addq_s_w1(i32 %i0, i32 %a0, i32 %a1) nounwind {
393 %0 = tail call i32 @llvm.mips.addq.s.w(i32 %a0, i32 %a1)
397 declare i32 @llvm.mips.addq.s.w(i32, i32) nounwind
399 define { i32 } @test__builtin_mips_addu_qb1(i32 %i0, i32 %a0.coerce, i32 %a1.coerce) nounwind {
403 %0 = bitcast i32 %a0.coerce to <4 x i8>
404 %1 = bitcast i32 %a1.coerce to <4 x i8>
405 %2 = tail call <4 x i8> @llvm.mips.addu.qb(<4 x i8> %0, <4 x i8> %1)
406 %3 = bitcast <4 x i8> %2 to i32
407 %.fca.0.insert = insertvalue { i32 } undef, i32 %3, 0
408 ret { i32 } %.fca.0.insert
411 declare <4 x i8> @llvm.mips.addu.qb(<4 x i8>, <4 x i8>) nounwind
413 define { i32 } @test__builtin_mips_addu_s_qb1(i32 %i0, i32 %a0.coerce, i32 %a1.coerce) nounwind {
417 %0 = bitcast i32 %a0.coerce to <4 x i8>
418 %1 = bitcast i32 %a1.coerce to <4 x i8>
419 %2 = tail call <4 x i8> @llvm.mips.addu.s.qb(<4 x i8> %0, <4 x i8> %1)
420 %3 = bitcast <4 x i8> %2 to i32
421 %.fca.0.insert = insertvalue { i32 } undef, i32 %3, 0
422 ret { i32 } %.fca.0.insert
425 declare <4 x i8> @llvm.mips.addu.s.qb(<4 x i8>, <4 x i8>) nounwind
427 define { i32 } @test__builtin_mips_subq_ph1(i32 %i0, i32 %a0.coerce, i32 %a1.coerce) nounwind {
431 %0 = bitcast i32 %a0.coerce to <2 x i16>
432 %1 = bitcast i32 %a1.coerce to <2 x i16>
433 %2 = tail call <2 x i16> @llvm.mips.subq.ph(<2 x i16> %0, <2 x i16> %1)
434 %3 = bitcast <2 x i16> %2 to i32
435 %.fca.0.insert = insertvalue { i32 } undef, i32 %3, 0
436 ret { i32 } %.fca.0.insert
439 declare <2 x i16> @llvm.mips.subq.ph(<2 x i16>, <2 x i16>) nounwind
441 define { i32 } @test__builtin_mips_subq_s_ph1(i32 %i0, i32 %a0.coerce, i32 %a1.coerce) nounwind {
445 %0 = bitcast i32 %a0.coerce to <2 x i16>
446 %1 = bitcast i32 %a1.coerce to <2 x i16>
447 %2 = tail call <2 x i16> @llvm.mips.subq.s.ph(<2 x i16> %0, <2 x i16> %1)
448 %3 = bitcast <2 x i16> %2 to i32
449 %.fca.0.insert = insertvalue { i32 } undef, i32 %3, 0
450 ret { i32 } %.fca.0.insert
453 declare <2 x i16> @llvm.mips.subq.s.ph(<2 x i16>, <2 x i16>) nounwind
455 define i32 @test__builtin_mips_subq_s_w1(i32 %i0, i32 %a0, i32 %a1) nounwind {
459 %0 = tail call i32 @llvm.mips.subq.s.w(i32 %a0, i32 %a1)
463 declare i32 @llvm.mips.subq.s.w(i32, i32) nounwind
465 define { i32 } @test__builtin_mips_subu_qb1(i32 %i0, i32 %a0.coerce, i32 %a1.coerce) nounwind {
469 %0 = bitcast i32 %a0.coerce to <4 x i8>
470 %1 = bitcast i32 %a1.coerce to <4 x i8>
471 %2 = tail call <4 x i8> @llvm.mips.subu.qb(<4 x i8> %0, <4 x i8> %1)
472 %3 = bitcast <4 x i8> %2 to i32
473 %.fca.0.insert = insertvalue { i32 } undef, i32 %3, 0
474 ret { i32 } %.fca.0.insert
477 declare <4 x i8> @llvm.mips.subu.qb(<4 x i8>, <4 x i8>) nounwind
479 define { i32 } @test__builtin_mips_subu_s_qb1(i32 %i0, i32 %a0.coerce, i32 %a1.coerce) nounwind {
483 %0 = bitcast i32 %a0.coerce to <4 x i8>
484 %1 = bitcast i32 %a1.coerce to <4 x i8>
485 %2 = tail call <4 x i8> @llvm.mips.subu.s.qb(<4 x i8> %0, <4 x i8> %1)
486 %3 = bitcast <4 x i8> %2 to i32
487 %.fca.0.insert = insertvalue { i32 } undef, i32 %3, 0
488 ret { i32 } %.fca.0.insert
491 declare <4 x i8> @llvm.mips.subu.s.qb(<4 x i8>, <4 x i8>) nounwind
493 define i32 @test__builtin_mips_addsc1(i32 %i0, i32 %a0, i32 %a1) nounwind {
497 %0 = tail call i32 @llvm.mips.addsc(i32 %a0, i32 %a1)
501 declare i32 @llvm.mips.addsc(i32, i32) nounwind
503 define i32 @test__builtin_mips_addwc1(i32 %i0, i32 %a0, i32 %a1) nounwind {
507 %0 = tail call i32 @llvm.mips.addwc(i32 %a0, i32 %a1)
511 declare i32 @llvm.mips.addwc(i32, i32) nounwind
513 define i32 @test__builtin_mips_modsub1(i32 %i0, i32 %a0, i32 %a1) nounwind readnone {
517 %0 = tail call i32 @llvm.mips.modsub(i32 %a0, i32 %a1)
521 declare i32 @llvm.mips.modsub(i32, i32) nounwind readnone
523 define i32 @test__builtin_mips_raddu_w_qb1(i32 %i0, i32 %a0.coerce) nounwind readnone {
527 %0 = bitcast i32 %a0.coerce to <4 x i8>
528 %1 = tail call i32 @llvm.mips.raddu.w.qb(<4 x i8> %0)
532 declare i32 @llvm.mips.raddu.w.qb(<4 x i8>) nounwind readnone
534 define { i32 } @test__builtin_mips_muleu_s_ph_qbl1(i32 %i0, i32 %a0.coerce, i32 %a1.coerce) nounwind {
536 ; CHECK: muleu_s.ph.qbl
538 %0 = bitcast i32 %a0.coerce to <4 x i8>
539 %1 = bitcast i32 %a1.coerce to <2 x i16>
540 %2 = tail call <2 x i16> @llvm.mips.muleu.s.ph.qbl(<4 x i8> %0, <2 x i16> %1)
541 %3 = bitcast <2 x i16> %2 to i32
542 %.fca.0.insert = insertvalue { i32 } undef, i32 %3, 0
543 ret { i32 } %.fca.0.insert
546 declare <2 x i16> @llvm.mips.muleu.s.ph.qbl(<4 x i8>, <2 x i16>) nounwind
548 define { i32 } @test__builtin_mips_muleu_s_ph_qbr1(i32 %i0, i32 %a0.coerce, i32 %a1.coerce) nounwind {
550 ; CHECK: muleu_s.ph.qbr
552 %0 = bitcast i32 %a0.coerce to <4 x i8>
553 %1 = bitcast i32 %a1.coerce to <2 x i16>
554 %2 = tail call <2 x i16> @llvm.mips.muleu.s.ph.qbr(<4 x i8> %0, <2 x i16> %1)
555 %3 = bitcast <2 x i16> %2 to i32
556 %.fca.0.insert = insertvalue { i32 } undef, i32 %3, 0
557 ret { i32 } %.fca.0.insert
560 declare <2 x i16> @llvm.mips.muleu.s.ph.qbr(<4 x i8>, <2 x i16>) nounwind
562 define { i32 } @test__builtin_mips_mulq_rs_ph1(i32 %i0, i32 %a0.coerce, i32 %a1.coerce) nounwind {
566 %0 = bitcast i32 %a0.coerce to <2 x i16>
567 %1 = bitcast i32 %a1.coerce to <2 x i16>
568 %2 = tail call <2 x i16> @llvm.mips.mulq.rs.ph(<2 x i16> %0, <2 x i16> %1)
569 %3 = bitcast <2 x i16> %2 to i32
570 %.fca.0.insert = insertvalue { i32 } undef, i32 %3, 0
571 ret { i32 } %.fca.0.insert
574 declare <2 x i16> @llvm.mips.mulq.rs.ph(<2 x i16>, <2 x i16>) nounwind
576 define i32 @test__builtin_mips_muleq_s_w_phl1(i32 %i0, i32 %a0.coerce, i32 %a1.coerce) nounwind {
578 ; CHECK: muleq_s.w.phl
580 %0 = bitcast i32 %a0.coerce to <2 x i16>
581 %1 = bitcast i32 %a1.coerce to <2 x i16>
582 %2 = tail call i32 @llvm.mips.muleq.s.w.phl(<2 x i16> %0, <2 x i16> %1)
586 declare i32 @llvm.mips.muleq.s.w.phl(<2 x i16>, <2 x i16>) nounwind
588 define i32 @test__builtin_mips_muleq_s_w_phr1(i32 %i0, i32 %a0.coerce, i32 %a1.coerce) nounwind {
590 ; CHECK: muleq_s.w.phr
592 %0 = bitcast i32 %a0.coerce to <2 x i16>
593 %1 = bitcast i32 %a1.coerce to <2 x i16>
594 %2 = tail call i32 @llvm.mips.muleq.s.w.phr(<2 x i16> %0, <2 x i16> %1)
598 declare i32 @llvm.mips.muleq.s.w.phr(<2 x i16>, <2 x i16>) nounwind