1 ; RUN: llc -march=mipsel -mattr=+dsp < %s | FileCheck %s
3 define i32 @test__builtin_mips_extr_w1(i32 %i0, i32, i64 %a0) nounwind {
7 %1 = tail call i32 @llvm.mips.extr.w(i64 %a0, i32 15)
11 declare i32 @llvm.mips.extr.w(i64, i32) nounwind
13 define i32 @test__builtin_mips_extr_w2(i32 %i0, i32, i64 %a0, i32 %a1) nounwind {
17 %1 = tail call i32 @llvm.mips.extr.w(i64 %a0, i32 %a1)
21 define i32 @test__builtin_mips_extr_r_w1(i32 %i0, i32, i64 %a0) nounwind {
25 %1 = tail call i32 @llvm.mips.extr.r.w(i64 %a0, i32 15)
29 declare i32 @llvm.mips.extr.r.w(i64, i32) nounwind
31 define i32 @test__builtin_mips_extr_s_h1(i32 %i0, i32, i64 %a0, i32 %a1) nounwind {
35 %1 = tail call i32 @llvm.mips.extr.s.h(i64 %a0, i32 %a1)
39 declare i32 @llvm.mips.extr.s.h(i64, i32) nounwind
41 define i32 @test__builtin_mips_extr_rs_w1(i32 %i0, i32, i64 %a0) nounwind {
45 %1 = tail call i32 @llvm.mips.extr.rs.w(i64 %a0, i32 15)
49 declare i32 @llvm.mips.extr.rs.w(i64, i32) nounwind
51 define i32 @test__builtin_mips_extr_rs_w2(i32 %i0, i32, i64 %a0, i32 %a1) nounwind {
55 %1 = tail call i32 @llvm.mips.extr.rs.w(i64 %a0, i32 %a1)
59 define i32 @test__builtin_mips_extr_s_h2(i32 %i0, i32, i64 %a0) nounwind {
63 %1 = tail call i32 @llvm.mips.extr.s.h(i64 %a0, i32 15)
67 define i32 @test__builtin_mips_extr_r_w2(i32 %i0, i32, i64 %a0, i32 %a1) nounwind {
71 %1 = tail call i32 @llvm.mips.extr.r.w(i64 %a0, i32 %a1)
75 define i32 @test__builtin_mips_extp1(i32 %i0, i32, i64 %a0) nounwind {
79 %1 = tail call i32 @llvm.mips.extp(i64 %a0, i32 15)
83 declare i32 @llvm.mips.extp(i64, i32) nounwind
85 define i32 @test__builtin_mips_extp2(i32 %i0, i32, i64 %a0, i32 %a1) nounwind {
89 %1 = tail call i32 @llvm.mips.extp(i64 %a0, i32 %a1)
93 define i32 @test__builtin_mips_extpdp1(i32 %i0, i32, i64 %a0) nounwind {
97 %1 = tail call i32 @llvm.mips.extpdp(i64 %a0, i32 15)
101 declare i32 @llvm.mips.extpdp(i64, i32) nounwind
103 define i32 @test__builtin_mips_extpdp2(i32 %i0, i32, i64 %a0, i32 %a1) nounwind {
107 %1 = tail call i32 @llvm.mips.extpdp(i64 %a0, i32 %a1)
111 define i64 @test__builtin_mips_dpau_h_qbl1(i32 %i0, i32, i64 %a0, i32 %a1.coerce, i32 %a2.coerce) nounwind readnone {
115 %1 = bitcast i32 %a1.coerce to <4 x i8>
116 %2 = bitcast i32 %a2.coerce to <4 x i8>
117 %3 = tail call i64 @llvm.mips.dpau.h.qbl(i64 %a0, <4 x i8> %1, <4 x i8> %2)
121 declare i64 @llvm.mips.dpau.h.qbl(i64, <4 x i8>, <4 x i8>) nounwind readnone
123 define i64 @test__builtin_mips_dpau_h_qbr1(i32 %i0, i32, i64 %a0, i32 %a1.coerce, i32 %a2.coerce) nounwind readnone {
127 %1 = bitcast i32 %a1.coerce to <4 x i8>
128 %2 = bitcast i32 %a2.coerce to <4 x i8>
129 %3 = tail call i64 @llvm.mips.dpau.h.qbr(i64 %a0, <4 x i8> %1, <4 x i8> %2)
133 declare i64 @llvm.mips.dpau.h.qbr(i64, <4 x i8>, <4 x i8>) nounwind readnone
135 define i64 @test__builtin_mips_dpsu_h_qbl1(i32 %i0, i32, i64 %a0, i32 %a1.coerce, i32 %a2.coerce) nounwind readnone {
139 %1 = bitcast i32 %a1.coerce to <4 x i8>
140 %2 = bitcast i32 %a2.coerce to <4 x i8>
141 %3 = tail call i64 @llvm.mips.dpsu.h.qbl(i64 %a0, <4 x i8> %1, <4 x i8> %2)
145 declare i64 @llvm.mips.dpsu.h.qbl(i64, <4 x i8>, <4 x i8>) nounwind readnone
147 define i64 @test__builtin_mips_dpsu_h_qbr1(i32 %i0, i32, i64 %a0, i32 %a1.coerce, i32 %a2.coerce) nounwind readnone {
151 %1 = bitcast i32 %a1.coerce to <4 x i8>
152 %2 = bitcast i32 %a2.coerce to <4 x i8>
153 %3 = tail call i64 @llvm.mips.dpsu.h.qbr(i64 %a0, <4 x i8> %1, <4 x i8> %2)
157 declare i64 @llvm.mips.dpsu.h.qbr(i64, <4 x i8>, <4 x i8>) nounwind readnone
159 define i64 @test__builtin_mips_dpaq_s_w_ph1(i32 %i0, i32, i64 %a0, i32 %a1.coerce, i32 %a2.coerce) nounwind {
163 %1 = bitcast i32 %a1.coerce to <2 x i16>
164 %2 = bitcast i32 %a2.coerce to <2 x i16>
165 %3 = tail call i64 @llvm.mips.dpaq.s.w.ph(i64 %a0, <2 x i16> %1, <2 x i16> %2)
169 declare i64 @llvm.mips.dpaq.s.w.ph(i64, <2 x i16>, <2 x i16>) nounwind
171 define i64 @test__builtin_mips_dpaq_sa_l_w1(i32 %i0, i32, i64 %a0, i32 %a1, i32 %a2) nounwind {
175 %1 = tail call i64 @llvm.mips.dpaq.sa.l.w(i64 %a0, i32 %a1, i32 %a2)
179 declare i64 @llvm.mips.dpaq.sa.l.w(i64, i32, i32) nounwind
181 define i64 @test__builtin_mips_dpsq_s_w_ph1(i32 %i0, i32, i64 %a0, i32 %a1.coerce, i32 %a2.coerce) nounwind {
185 %1 = bitcast i32 %a1.coerce to <2 x i16>
186 %2 = bitcast i32 %a2.coerce to <2 x i16>
187 %3 = tail call i64 @llvm.mips.dpsq.s.w.ph(i64 %a0, <2 x i16> %1, <2 x i16> %2)
191 declare i64 @llvm.mips.dpsq.s.w.ph(i64, <2 x i16>, <2 x i16>) nounwind
193 define i64 @test__builtin_mips_dpsq_sa_l_w1(i32 %i0, i32, i64 %a0, i32 %a1, i32 %a2) nounwind {
197 %1 = tail call i64 @llvm.mips.dpsq.sa.l.w(i64 %a0, i32 %a1, i32 %a2)
201 declare i64 @llvm.mips.dpsq.sa.l.w(i64, i32, i32) nounwind
203 define i64 @test__builtin_mips_mulsaq_s_w_ph1(i32 %i0, i32, i64 %a0, i32 %a1.coerce, i32 %a2.coerce) nounwind {
205 ; CHECK: mulsaq_s.w.ph
207 %1 = bitcast i32 %a1.coerce to <2 x i16>
208 %2 = bitcast i32 %a2.coerce to <2 x i16>
209 %3 = tail call i64 @llvm.mips.mulsaq.s.w.ph(i64 %a0, <2 x i16> %1, <2 x i16> %2)
213 declare i64 @llvm.mips.mulsaq.s.w.ph(i64, <2 x i16>, <2 x i16>) nounwind
215 define i64 @test__builtin_mips_maq_s_w_phl1(i32 %i0, i32, i64 %a0, i32 %a1.coerce, i32 %a2.coerce) nounwind {
219 %1 = bitcast i32 %a1.coerce to <2 x i16>
220 %2 = bitcast i32 %a2.coerce to <2 x i16>
221 %3 = tail call i64 @llvm.mips.maq.s.w.phl(i64 %a0, <2 x i16> %1, <2 x i16> %2)
225 declare i64 @llvm.mips.maq.s.w.phl(i64, <2 x i16>, <2 x i16>) nounwind
227 define i64 @test__builtin_mips_maq_s_w_phr1(i32 %i0, i32, i64 %a0, i32 %a1.coerce, i32 %a2.coerce) nounwind {
231 %1 = bitcast i32 %a1.coerce to <2 x i16>
232 %2 = bitcast i32 %a2.coerce to <2 x i16>
233 %3 = tail call i64 @llvm.mips.maq.s.w.phr(i64 %a0, <2 x i16> %1, <2 x i16> %2)
237 declare i64 @llvm.mips.maq.s.w.phr(i64, <2 x i16>, <2 x i16>) nounwind
239 define i64 @test__builtin_mips_maq_sa_w_phl1(i32 %i0, i32, i64 %a0, i32 %a1.coerce, i32 %a2.coerce) nounwind {
241 ; CHECK: maq_sa.w.phl
243 %1 = bitcast i32 %a1.coerce to <2 x i16>
244 %2 = bitcast i32 %a2.coerce to <2 x i16>
245 %3 = tail call i64 @llvm.mips.maq.sa.w.phl(i64 %a0, <2 x i16> %1, <2 x i16> %2)
249 declare i64 @llvm.mips.maq.sa.w.phl(i64, <2 x i16>, <2 x i16>) nounwind
251 define i64 @test__builtin_mips_maq_sa_w_phr1(i32 %i0, i32, i64 %a0, i32 %a1.coerce, i32 %a2.coerce) nounwind {
253 ; CHECK: maq_sa.w.phr
255 %1 = bitcast i32 %a1.coerce to <2 x i16>
256 %2 = bitcast i32 %a2.coerce to <2 x i16>
257 %3 = tail call i64 @llvm.mips.maq.sa.w.phr(i64 %a0, <2 x i16> %1, <2 x i16> %2)
261 declare i64 @llvm.mips.maq.sa.w.phr(i64, <2 x i16>, <2 x i16>) nounwind
263 define i64 @test__builtin_mips_shilo1(i32 %i0, i32, i64 %a0) nounwind readnone {
267 %1 = tail call i64 @llvm.mips.shilo(i64 %a0, i32 0)
271 declare i64 @llvm.mips.shilo(i64, i32) nounwind readnone
273 define i64 @test__builtin_mips_shilo2(i32 %i0, i32, i64 %a0, i32 %a1) nounwind readnone {
277 %1 = tail call i64 @llvm.mips.shilo(i64 %a0, i32 %a1)
281 define i64 @test__builtin_mips_mthlip1(i32 %i0, i32, i64 %a0, i32 %a1) nounwind {
285 %1 = tail call i64 @llvm.mips.mthlip(i64 %a0, i32 %a1)
289 declare i64 @llvm.mips.mthlip(i64, i32) nounwind
291 define i32 @test__builtin_mips_bposge321(i32 %i0) nounwind readonly {
295 %0 = tail call i32 @llvm.mips.bposge32()
299 declare i32 @llvm.mips.bposge32() nounwind readonly
301 define i64 @test__builtin_mips_madd1(i32 %i0, i32, i64 %a0, i32 %a1, i32 %a2) nounwind readnone {
305 %1 = tail call i64 @llvm.mips.madd(i64 %a0, i32 %a1, i32 %a2)
309 declare i64 @llvm.mips.madd(i64, i32, i32) nounwind readnone
311 define i64 @test__builtin_mips_maddu1(i32 %i0, i32, i64 %a0, i32 %a1, i32 %a2) nounwind readnone {
315 %1 = tail call i64 @llvm.mips.maddu(i64 %a0, i32 %a1, i32 %a2)
319 declare i64 @llvm.mips.maddu(i64, i32, i32) nounwind readnone
321 define i64 @test__builtin_mips_msub1(i32 %i0, i32, i64 %a0, i32 %a1, i32 %a2) nounwind readnone {
325 %1 = tail call i64 @llvm.mips.msub(i64 %a0, i32 %a1, i32 %a2)
329 declare i64 @llvm.mips.msub(i64, i32, i32) nounwind readnone
331 define i64 @test__builtin_mips_msubu1(i32 %i0, i32, i64 %a0, i32 %a1, i32 %a2) nounwind readnone {
335 %1 = tail call i64 @llvm.mips.msubu(i64 %a0, i32 %a1, i32 %a2)
339 declare i64 @llvm.mips.msubu(i64, i32, i32) nounwind readnone
341 define i64 @test__builtin_mips_mult1(i32 %i0, i32 %a0, i32 %a1) nounwind readnone {
345 %0 = tail call i64 @llvm.mips.mult(i32 %a0, i32 %a1)
349 declare i64 @llvm.mips.mult(i32, i32) nounwind readnone
351 define i64 @test__builtin_mips_multu1(i32 %i0, i32 %a0, i32 %a1) nounwind readnone {
355 %0 = tail call i64 @llvm.mips.multu(i32 %a0, i32 %a1)
359 declare i64 @llvm.mips.multu(i32, i32) nounwind readnone