1 ; RUN: llc -march=mipsel -mcpu=mips32 -mattr=+dsp < %s | FileCheck %s
3 define i32 @test__builtin_mips_extr_w1(i32 %i0, i32, i64 %a0) nounwind {
7 %1 = tail call i32 @llvm.mips.extr.w(i64 %a0, i32 15)
11 declare i32 @llvm.mips.extr.w(i64, i32) nounwind
13 define i32 @test__builtin_mips_extr_w2(i32 %i0, i32, i64 %a0, i32 %a1) nounwind {
17 %1 = tail call i32 @llvm.mips.extr.w(i64 %a0, i32 %a1)
21 define i32 @test__builtin_mips_extr_r_w1(i32 %i0, i32, i64 %a0) nounwind {
25 %1 = tail call i32 @llvm.mips.extr.r.w(i64 %a0, i32 15)
29 declare i32 @llvm.mips.extr.r.w(i64, i32) nounwind
31 define i32 @test__builtin_mips_extr_s_h1(i32 %i0, i32, i64 %a0, i32 %a1) nounwind {
35 %1 = tail call i32 @llvm.mips.extr.s.h(i64 %a0, i32 %a1)
39 declare i32 @llvm.mips.extr.s.h(i64, i32) nounwind
41 define i32 @test__builtin_mips_extr_rs_w1(i32 %i0, i32, i64 %a0) nounwind {
45 %1 = tail call i32 @llvm.mips.extr.rs.w(i64 %a0, i32 15)
49 declare i32 @llvm.mips.extr.rs.w(i64, i32) nounwind
51 define i32 @test__builtin_mips_extr_rs_w2(i32 %i0, i32, i64 %a0, i32 %a1) nounwind {
55 %1 = tail call i32 @llvm.mips.extr.rs.w(i64 %a0, i32 %a1)
59 define i32 @test__builtin_mips_extr_s_h2(i32 %i0, i32, i64 %a0) nounwind {
63 %1 = tail call i32 @llvm.mips.extr.s.h(i64 %a0, i32 15)
67 define i32 @test__builtin_mips_extr_r_w2(i32 %i0, i32, i64 %a0, i32 %a1) nounwind {
71 %1 = tail call i32 @llvm.mips.extr.r.w(i64 %a0, i32 %a1)
75 define i32 @test__builtin_mips_extp1(i32 %i0, i32, i64 %a0) nounwind {
77 ; CHECK: extp ${{[0-9]+}}
79 %1 = tail call i32 @llvm.mips.extp(i64 %a0, i32 15)
83 declare i32 @llvm.mips.extp(i64, i32) nounwind
85 define i32 @test__builtin_mips_extp2(i32 %i0, i32, i64 %a0, i32 %a1) nounwind {
89 %1 = tail call i32 @llvm.mips.extp(i64 %a0, i32 %a1)
93 define i32 @test__builtin_mips_extpdp1(i32 %i0, i32, i64 %a0) nounwind {
95 ; CHECK: extpdp ${{[0-9]+}}
97 %1 = tail call i32 @llvm.mips.extpdp(i64 %a0, i32 15)
101 declare i32 @llvm.mips.extpdp(i64, i32) nounwind
103 define i32 @test__builtin_mips_extpdp2(i32 %i0, i32, i64 %a0, i32 %a1) nounwind {
107 %1 = tail call i32 @llvm.mips.extpdp(i64 %a0, i32 %a1)
111 define i64 @test__builtin_mips_dpau_h_qbl1(i32 %i0, i32, i64 %a0, i32 %a1.coerce, i32 %a2.coerce) nounwind readnone {
115 %1 = bitcast i32 %a1.coerce to <4 x i8>
116 %2 = bitcast i32 %a2.coerce to <4 x i8>
117 %3 = tail call i64 @llvm.mips.dpau.h.qbl(i64 %a0, <4 x i8> %1, <4 x i8> %2)
121 declare i64 @llvm.mips.dpau.h.qbl(i64, <4 x i8>, <4 x i8>) nounwind readnone
123 define i64 @test__builtin_mips_dpau_h_qbr1(i32 %i0, i32, i64 %a0, i32 %a1.coerce, i32 %a2.coerce) nounwind readnone {
127 %1 = bitcast i32 %a1.coerce to <4 x i8>
128 %2 = bitcast i32 %a2.coerce to <4 x i8>
129 %3 = tail call i64 @llvm.mips.dpau.h.qbr(i64 %a0, <4 x i8> %1, <4 x i8> %2)
133 declare i64 @llvm.mips.dpau.h.qbr(i64, <4 x i8>, <4 x i8>) nounwind readnone
135 define i64 @test__builtin_mips_dpsu_h_qbl1(i32 %i0, i32, i64 %a0, i32 %a1.coerce, i32 %a2.coerce) nounwind readnone {
139 %1 = bitcast i32 %a1.coerce to <4 x i8>
140 %2 = bitcast i32 %a2.coerce to <4 x i8>
141 %3 = tail call i64 @llvm.mips.dpsu.h.qbl(i64 %a0, <4 x i8> %1, <4 x i8> %2)
145 declare i64 @llvm.mips.dpsu.h.qbl(i64, <4 x i8>, <4 x i8>) nounwind readnone
147 define i64 @test__builtin_mips_dpsu_h_qbr1(i32 %i0, i32, i64 %a0, i32 %a1.coerce, i32 %a2.coerce) nounwind readnone {
151 %1 = bitcast i32 %a1.coerce to <4 x i8>
152 %2 = bitcast i32 %a2.coerce to <4 x i8>
153 %3 = tail call i64 @llvm.mips.dpsu.h.qbr(i64 %a0, <4 x i8> %1, <4 x i8> %2)
157 declare i64 @llvm.mips.dpsu.h.qbr(i64, <4 x i8>, <4 x i8>) nounwind readnone
159 define i64 @test__builtin_mips_dpaq_s_w_ph1(i32 %i0, i32, i64 %a0, i32 %a1.coerce, i32 %a2.coerce) nounwind {
163 %1 = bitcast i32 %a1.coerce to <2 x i16>
164 %2 = bitcast i32 %a2.coerce to <2 x i16>
165 %3 = tail call i64 @llvm.mips.dpaq.s.w.ph(i64 %a0, <2 x i16> %1, <2 x i16> %2)
169 declare i64 @llvm.mips.dpaq.s.w.ph(i64, <2 x i16>, <2 x i16>) nounwind
171 define i64 @test__builtin_mips_dpaq_sa_l_w1(i32 %i0, i32, i64 %a0, i32 %a1, i32 %a2) nounwind {
175 %1 = tail call i64 @llvm.mips.dpaq.sa.l.w(i64 %a0, i32 %a1, i32 %a2)
179 declare i64 @llvm.mips.dpaq.sa.l.w(i64, i32, i32) nounwind
181 define i64 @test__builtin_mips_dpsq_s_w_ph1(i32 %i0, i32, i64 %a0, i32 %a1.coerce, i32 %a2.coerce) nounwind {
185 %1 = bitcast i32 %a1.coerce to <2 x i16>
186 %2 = bitcast i32 %a2.coerce to <2 x i16>
187 %3 = tail call i64 @llvm.mips.dpsq.s.w.ph(i64 %a0, <2 x i16> %1, <2 x i16> %2)
191 declare i64 @llvm.mips.dpsq.s.w.ph(i64, <2 x i16>, <2 x i16>) nounwind
193 define i64 @test__builtin_mips_dpsq_sa_l_w1(i32 %i0, i32, i64 %a0, i32 %a1, i32 %a2) nounwind {
197 %1 = tail call i64 @llvm.mips.dpsq.sa.l.w(i64 %a0, i32 %a1, i32 %a2)
201 declare i64 @llvm.mips.dpsq.sa.l.w(i64, i32, i32) nounwind
203 define i64 @test__builtin_mips_mulsaq_s_w_ph1(i32 %i0, i32, i64 %a0, i32 %a1.coerce, i32 %a2.coerce) nounwind {
205 ; CHECK: mulsaq_s.w.ph
207 %1 = bitcast i32 %a1.coerce to <2 x i16>
208 %2 = bitcast i32 %a2.coerce to <2 x i16>
209 %3 = tail call i64 @llvm.mips.mulsaq.s.w.ph(i64 %a0, <2 x i16> %1, <2 x i16> %2)
213 declare i64 @llvm.mips.mulsaq.s.w.ph(i64, <2 x i16>, <2 x i16>) nounwind
215 define i64 @test__builtin_mips_maq_s_w_phl1(i32 %i0, i32, i64 %a0, i32 %a1.coerce, i32 %a2.coerce) nounwind {
219 %1 = bitcast i32 %a1.coerce to <2 x i16>
220 %2 = bitcast i32 %a2.coerce to <2 x i16>
221 %3 = tail call i64 @llvm.mips.maq.s.w.phl(i64 %a0, <2 x i16> %1, <2 x i16> %2)
225 declare i64 @llvm.mips.maq.s.w.phl(i64, <2 x i16>, <2 x i16>) nounwind
227 define i64 @test__builtin_mips_maq_s_w_phr1(i32 %i0, i32, i64 %a0, i32 %a1.coerce, i32 %a2.coerce) nounwind {
231 %1 = bitcast i32 %a1.coerce to <2 x i16>
232 %2 = bitcast i32 %a2.coerce to <2 x i16>
233 %3 = tail call i64 @llvm.mips.maq.s.w.phr(i64 %a0, <2 x i16> %1, <2 x i16> %2)
237 declare i64 @llvm.mips.maq.s.w.phr(i64, <2 x i16>, <2 x i16>) nounwind
239 define i64 @test__builtin_mips_maq_sa_w_phl1(i32 %i0, i32, i64 %a0, i32 %a1.coerce, i32 %a2.coerce) nounwind {
241 ; CHECK: maq_sa.w.phl
243 %1 = bitcast i32 %a1.coerce to <2 x i16>
244 %2 = bitcast i32 %a2.coerce to <2 x i16>
245 %3 = tail call i64 @llvm.mips.maq.sa.w.phl(i64 %a0, <2 x i16> %1, <2 x i16> %2)
249 declare i64 @llvm.mips.maq.sa.w.phl(i64, <2 x i16>, <2 x i16>) nounwind
251 define i64 @test__builtin_mips_maq_sa_w_phr1(i32 %i0, i32, i64 %a0, i32 %a1.coerce, i32 %a2.coerce) nounwind {
253 ; CHECK: maq_sa.w.phr
255 %1 = bitcast i32 %a1.coerce to <2 x i16>
256 %2 = bitcast i32 %a2.coerce to <2 x i16>
257 %3 = tail call i64 @llvm.mips.maq.sa.w.phr(i64 %a0, <2 x i16> %1, <2 x i16> %2)
261 declare i64 @llvm.mips.maq.sa.w.phr(i64, <2 x i16>, <2 x i16>) nounwind
263 define i64 @test__builtin_mips_shilo1(i32 %i0, i32, i64 %a0) nounwind readnone {
265 ; CHECK: shilo $ac{{[0-9]}}
267 %1 = tail call i64 @llvm.mips.shilo(i64 %a0, i32 0)
271 declare i64 @llvm.mips.shilo(i64, i32) nounwind readnone
273 define i64 @test__builtin_mips_shilo2(i32 %i0, i32, i64 %a0, i32 %a1) nounwind readnone {
277 %1 = tail call i64 @llvm.mips.shilo(i64 %a0, i32 %a1)
281 define i64 @test__builtin_mips_mthlip1(i32 %i0, i32, i64 %a0, i32 %a1) nounwind {
283 ; CHECK: mthlip ${{[0-9]+}}
285 %1 = tail call i64 @llvm.mips.mthlip(i64 %a0, i32 %a1)
289 declare i64 @llvm.mips.mthlip(i64, i32) nounwind
291 define i32 @test__builtin_mips_bposge321(i32 %i0) nounwind readonly {
293 ; CHECK: bposge32 $BB{{[0-9]+}}
295 %0 = tail call i32 @llvm.mips.bposge32()
299 declare i32 @llvm.mips.bposge32() nounwind readonly
301 define i64 @test__builtin_mips_madd1(i32 %i0, i32, i64 %a0, i32 %a1, i32 %a2) nounwind readnone {
303 ; CHECK: madd $ac{{[0-9]}}
305 %1 = tail call i64 @llvm.mips.madd(i64 %a0, i32 %a1, i32 %a2)
309 declare i64 @llvm.mips.madd(i64, i32, i32) nounwind readnone
311 define i64 @test__builtin_mips_maddu1(i32 %i0, i32, i64 %a0, i32 %a1, i32 %a2) nounwind readnone {
313 ; CHECK: maddu $ac{{[0-9]}}
315 %1 = tail call i64 @llvm.mips.maddu(i64 %a0, i32 %a1, i32 %a2)
319 declare i64 @llvm.mips.maddu(i64, i32, i32) nounwind readnone
321 define i64 @test__builtin_mips_msub1(i32 %i0, i32, i64 %a0, i32 %a1, i32 %a2) nounwind readnone {
323 ; CHECK: msub $ac{{[0-9]}}
325 %1 = tail call i64 @llvm.mips.msub(i64 %a0, i32 %a1, i32 %a2)
329 declare i64 @llvm.mips.msub(i64, i32, i32) nounwind readnone
331 define i64 @test__builtin_mips_msubu1(i32 %i0, i32, i64 %a0, i32 %a1, i32 %a2) nounwind readnone {
333 ; CHECK: msubu $ac{{[0-9]}}
335 %1 = tail call i64 @llvm.mips.msubu(i64 %a0, i32 %a1, i32 %a2)
339 declare i64 @llvm.mips.msubu(i64, i32, i32) nounwind readnone
341 define i64 @test__builtin_mips_mult1(i32 %i0, i32 %a0, i32 %a1) nounwind readnone {
343 ; CHECK: mult $ac{{[0-9]}}
345 %0 = tail call i64 @llvm.mips.mult(i32 %a0, i32 %a1)
349 declare i64 @llvm.mips.mult(i32, i32) nounwind readnone
351 define i64 @test__builtin_mips_multu1(i32 %i0, i32 %a0, i32 %a1) nounwind readnone {
353 ; CHECK: multu $ac{{[0-9]}}
355 %0 = tail call i64 @llvm.mips.multu(i32 %a0, i32 %a1)
359 declare i64 @llvm.mips.multu(i32, i32) nounwind readnone
361 define { i32 } @test__builtin_mips_addq_ph1(i32 %i0, i32 %a0.coerce, i32 %a1.coerce) nounwind {
365 %0 = bitcast i32 %a0.coerce to <2 x i16>
366 %1 = bitcast i32 %a1.coerce to <2 x i16>
367 %2 = tail call <2 x i16> @llvm.mips.addq.ph(<2 x i16> %0, <2 x i16> %1)
368 %3 = bitcast <2 x i16> %2 to i32
369 %.fca.0.insert = insertvalue { i32 } undef, i32 %3, 0
370 ret { i32 } %.fca.0.insert
373 declare <2 x i16> @llvm.mips.addq.ph(<2 x i16>, <2 x i16>) nounwind
375 define { i32 } @test__builtin_mips_addq_s_ph1(i32 %i0, i32 %a0.coerce, i32 %a1.coerce) nounwind {
379 %0 = bitcast i32 %a0.coerce to <2 x i16>
380 %1 = bitcast i32 %a1.coerce to <2 x i16>
381 %2 = tail call <2 x i16> @llvm.mips.addq.s.ph(<2 x i16> %0, <2 x i16> %1)
382 %3 = bitcast <2 x i16> %2 to i32
383 %.fca.0.insert = insertvalue { i32 } undef, i32 %3, 0
384 ret { i32 } %.fca.0.insert
387 declare <2 x i16> @llvm.mips.addq.s.ph(<2 x i16>, <2 x i16>) nounwind
389 define i32 @test__builtin_mips_addq_s_w1(i32 %i0, i32 %a0, i32 %a1) nounwind {
393 %0 = tail call i32 @llvm.mips.addq.s.w(i32 %a0, i32 %a1)
397 declare i32 @llvm.mips.addq.s.w(i32, i32) nounwind
399 define { i32 } @test__builtin_mips_addu_qb1(i32 %i0, i32 %a0.coerce, i32 %a1.coerce) nounwind {
403 %0 = bitcast i32 %a0.coerce to <4 x i8>
404 %1 = bitcast i32 %a1.coerce to <4 x i8>
405 %2 = tail call <4 x i8> @llvm.mips.addu.qb(<4 x i8> %0, <4 x i8> %1)
406 %3 = bitcast <4 x i8> %2 to i32
407 %.fca.0.insert = insertvalue { i32 } undef, i32 %3, 0
408 ret { i32 } %.fca.0.insert
411 declare <4 x i8> @llvm.mips.addu.qb(<4 x i8>, <4 x i8>) nounwind
413 define { i32 } @test__builtin_mips_addu_s_qb1(i32 %i0, i32 %a0.coerce, i32 %a1.coerce) nounwind {
417 %0 = bitcast i32 %a0.coerce to <4 x i8>
418 %1 = bitcast i32 %a1.coerce to <4 x i8>
419 %2 = tail call <4 x i8> @llvm.mips.addu.s.qb(<4 x i8> %0, <4 x i8> %1)
420 %3 = bitcast <4 x i8> %2 to i32
421 %.fca.0.insert = insertvalue { i32 } undef, i32 %3, 0
422 ret { i32 } %.fca.0.insert
425 declare <4 x i8> @llvm.mips.addu.s.qb(<4 x i8>, <4 x i8>) nounwind
427 define { i32 } @test__builtin_mips_subq_ph1(i32 %i0, i32 %a0.coerce, i32 %a1.coerce) nounwind {
431 %0 = bitcast i32 %a0.coerce to <2 x i16>
432 %1 = bitcast i32 %a1.coerce to <2 x i16>
433 %2 = tail call <2 x i16> @llvm.mips.subq.ph(<2 x i16> %0, <2 x i16> %1)
434 %3 = bitcast <2 x i16> %2 to i32
435 %.fca.0.insert = insertvalue { i32 } undef, i32 %3, 0
436 ret { i32 } %.fca.0.insert
439 declare <2 x i16> @llvm.mips.subq.ph(<2 x i16>, <2 x i16>) nounwind
441 define { i32 } @test__builtin_mips_subq_s_ph1(i32 %i0, i32 %a0.coerce, i32 %a1.coerce) nounwind {
445 %0 = bitcast i32 %a0.coerce to <2 x i16>
446 %1 = bitcast i32 %a1.coerce to <2 x i16>
447 %2 = tail call <2 x i16> @llvm.mips.subq.s.ph(<2 x i16> %0, <2 x i16> %1)
448 %3 = bitcast <2 x i16> %2 to i32
449 %.fca.0.insert = insertvalue { i32 } undef, i32 %3, 0
450 ret { i32 } %.fca.0.insert
453 declare <2 x i16> @llvm.mips.subq.s.ph(<2 x i16>, <2 x i16>) nounwind
455 define i32 @test__builtin_mips_subq_s_w1(i32 %i0, i32 %a0, i32 %a1) nounwind {
459 %0 = tail call i32 @llvm.mips.subq.s.w(i32 %a0, i32 %a1)
463 declare i32 @llvm.mips.subq.s.w(i32, i32) nounwind
465 define { i32 } @test__builtin_mips_subu_qb1(i32 %i0, i32 %a0.coerce, i32 %a1.coerce) nounwind {
469 %0 = bitcast i32 %a0.coerce to <4 x i8>
470 %1 = bitcast i32 %a1.coerce to <4 x i8>
471 %2 = tail call <4 x i8> @llvm.mips.subu.qb(<4 x i8> %0, <4 x i8> %1)
472 %3 = bitcast <4 x i8> %2 to i32
473 %.fca.0.insert = insertvalue { i32 } undef, i32 %3, 0
474 ret { i32 } %.fca.0.insert
477 declare <4 x i8> @llvm.mips.subu.qb(<4 x i8>, <4 x i8>) nounwind
479 define { i32 } @test__builtin_mips_subu_s_qb1(i32 %i0, i32 %a0.coerce, i32 %a1.coerce) nounwind {
483 %0 = bitcast i32 %a0.coerce to <4 x i8>
484 %1 = bitcast i32 %a1.coerce to <4 x i8>
485 %2 = tail call <4 x i8> @llvm.mips.subu.s.qb(<4 x i8> %0, <4 x i8> %1)
486 %3 = bitcast <4 x i8> %2 to i32
487 %.fca.0.insert = insertvalue { i32 } undef, i32 %3, 0
488 ret { i32 } %.fca.0.insert
491 declare <4 x i8> @llvm.mips.subu.s.qb(<4 x i8>, <4 x i8>) nounwind
493 define i32 @test__builtin_mips_addsc1(i32 %i0, i32 %a0, i32 %a1) nounwind {
495 ; CHECK: addsc ${{[0-9]+}}
497 %0 = tail call i32 @llvm.mips.addsc(i32 %a0, i32 %a1)
501 declare i32 @llvm.mips.addsc(i32, i32) nounwind
503 define i32 @test__builtin_mips_addwc1(i32 %i0, i32 %a0, i32 %a1) nounwind {
505 ; CHECK: addwc ${{[0-9]+}}
507 %0 = tail call i32 @llvm.mips.addwc(i32 %a0, i32 %a1)
511 declare i32 @llvm.mips.addwc(i32, i32) nounwind
513 define i32 @test__builtin_mips_modsub1(i32 %i0, i32 %a0, i32 %a1) nounwind readnone {
515 ; CHECK: modsub ${{[0-9]+}}
517 %0 = tail call i32 @llvm.mips.modsub(i32 %a0, i32 %a1)
521 declare i32 @llvm.mips.modsub(i32, i32) nounwind readnone
523 define i32 @test__builtin_mips_raddu_w_qb1(i32 %i0, i32 %a0.coerce) nounwind readnone {
527 %0 = bitcast i32 %a0.coerce to <4 x i8>
528 %1 = tail call i32 @llvm.mips.raddu.w.qb(<4 x i8> %0)
532 declare i32 @llvm.mips.raddu.w.qb(<4 x i8>) nounwind readnone
534 define { i32 } @test__builtin_mips_muleu_s_ph_qbl1(i32 %i0, i32 %a0.coerce, i32 %a1.coerce) nounwind {
536 ; CHECK: muleu_s.ph.qbl
538 %0 = bitcast i32 %a0.coerce to <4 x i8>
539 %1 = bitcast i32 %a1.coerce to <2 x i16>
540 %2 = tail call <2 x i16> @llvm.mips.muleu.s.ph.qbl(<4 x i8> %0, <2 x i16> %1)
541 %3 = bitcast <2 x i16> %2 to i32
542 %.fca.0.insert = insertvalue { i32 } undef, i32 %3, 0
543 ret { i32 } %.fca.0.insert
546 declare <2 x i16> @llvm.mips.muleu.s.ph.qbl(<4 x i8>, <2 x i16>) nounwind
548 define { i32 } @test__builtin_mips_muleu_s_ph_qbr1(i32 %i0, i32 %a0.coerce, i32 %a1.coerce) nounwind {
550 ; CHECK: muleu_s.ph.qbr
552 %0 = bitcast i32 %a0.coerce to <4 x i8>
553 %1 = bitcast i32 %a1.coerce to <2 x i16>
554 %2 = tail call <2 x i16> @llvm.mips.muleu.s.ph.qbr(<4 x i8> %0, <2 x i16> %1)
555 %3 = bitcast <2 x i16> %2 to i32
556 %.fca.0.insert = insertvalue { i32 } undef, i32 %3, 0
557 ret { i32 } %.fca.0.insert
560 declare <2 x i16> @llvm.mips.muleu.s.ph.qbr(<4 x i8>, <2 x i16>) nounwind
562 define { i32 } @test__builtin_mips_mulq_rs_ph1(i32 %i0, i32 %a0.coerce, i32 %a1.coerce) nounwind {
566 %0 = bitcast i32 %a0.coerce to <2 x i16>
567 %1 = bitcast i32 %a1.coerce to <2 x i16>
568 %2 = tail call <2 x i16> @llvm.mips.mulq.rs.ph(<2 x i16> %0, <2 x i16> %1)
569 %3 = bitcast <2 x i16> %2 to i32
570 %.fca.0.insert = insertvalue { i32 } undef, i32 %3, 0
571 ret { i32 } %.fca.0.insert
574 declare <2 x i16> @llvm.mips.mulq.rs.ph(<2 x i16>, <2 x i16>) nounwind
576 define i32 @test__builtin_mips_muleq_s_w_phl1(i32 %i0, i32 %a0.coerce, i32 %a1.coerce) nounwind {
578 ; CHECK: muleq_s.w.phl
580 %0 = bitcast i32 %a0.coerce to <2 x i16>
581 %1 = bitcast i32 %a1.coerce to <2 x i16>
582 %2 = tail call i32 @llvm.mips.muleq.s.w.phl(<2 x i16> %0, <2 x i16> %1)
586 declare i32 @llvm.mips.muleq.s.w.phl(<2 x i16>, <2 x i16>) nounwind
588 define i32 @test__builtin_mips_muleq_s_w_phr1(i32 %i0, i32 %a0.coerce, i32 %a1.coerce) nounwind {
590 ; CHECK: muleq_s.w.phr
592 %0 = bitcast i32 %a0.coerce to <2 x i16>
593 %1 = bitcast i32 %a1.coerce to <2 x i16>
594 %2 = tail call i32 @llvm.mips.muleq.s.w.phr(<2 x i16> %0, <2 x i16> %1)
598 declare i32 @llvm.mips.muleq.s.w.phr(<2 x i16>, <2 x i16>) nounwind
600 define { i32 } @test__builtin_mips_precrq_qb_ph1(i32 %i0, i32 %a0.coerce, i32 %a1.coerce) nounwind readnone {
602 ; CHECK: precrq.qb.ph
604 %0 = bitcast i32 %a0.coerce to <2 x i16>
605 %1 = bitcast i32 %a1.coerce to <2 x i16>
606 %2 = tail call <4 x i8> @llvm.mips.precrq.qb.ph(<2 x i16> %0, <2 x i16> %1)
607 %3 = bitcast <4 x i8> %2 to i32
608 %.fca.0.insert = insertvalue { i32 } undef, i32 %3, 0
609 ret { i32 } %.fca.0.insert
612 declare <4 x i8> @llvm.mips.precrq.qb.ph(<2 x i16>, <2 x i16>) nounwind readnone
614 define { i32 } @test__builtin_mips_precrq_ph_w1(i32 %i0, i32 %a0, i32 %a1) nounwind readnone {
618 %0 = tail call <2 x i16> @llvm.mips.precrq.ph.w(i32 %a0, i32 %a1)
619 %1 = bitcast <2 x i16> %0 to i32
620 %.fca.0.insert = insertvalue { i32 } undef, i32 %1, 0
621 ret { i32 } %.fca.0.insert
624 declare <2 x i16> @llvm.mips.precrq.ph.w(i32, i32) nounwind readnone
626 define { i32 } @test__builtin_mips_precrq_rs_ph_w1(i32 %i0, i32 %a0, i32 %a1) nounwind {
628 ; CHECK: precrq_rs.ph.w
630 %0 = tail call <2 x i16> @llvm.mips.precrq.rs.ph.w(i32 %a0, i32 %a1)
631 %1 = bitcast <2 x i16> %0 to i32
632 %.fca.0.insert = insertvalue { i32 } undef, i32 %1, 0
633 ret { i32 } %.fca.0.insert
636 declare <2 x i16> @llvm.mips.precrq.rs.ph.w(i32, i32) nounwind
638 define { i32 } @test__builtin_mips_precrqu_s_qb_ph1(i32 %i0, i32 %a0.coerce, i32 %a1.coerce) nounwind {
640 ; CHECK: precrqu_s.qb.ph
642 %0 = bitcast i32 %a0.coerce to <2 x i16>
643 %1 = bitcast i32 %a1.coerce to <2 x i16>
644 %2 = tail call <4 x i8> @llvm.mips.precrqu.s.qb.ph(<2 x i16> %0, <2 x i16> %1)
645 %3 = bitcast <4 x i8> %2 to i32
646 %.fca.0.insert = insertvalue { i32 } undef, i32 %3, 0
647 ret { i32 } %.fca.0.insert
650 declare <4 x i8> @llvm.mips.precrqu.s.qb.ph(<2 x i16>, <2 x i16>) nounwind
653 define i32 @test__builtin_mips_cmpu_eq_qb1(i32 %i0, i32 %a0.coerce, i32 %a1.coerce) nounwind {
657 %0 = bitcast i32 %a0.coerce to <4 x i8>
658 %1 = bitcast i32 %a1.coerce to <4 x i8>
659 tail call void @llvm.mips.cmpu.eq.qb(<4 x i8> %0, <4 x i8> %1)
660 %2 = tail call i32 @llvm.mips.rddsp(i32 31)
664 declare void @llvm.mips.cmpu.eq.qb(<4 x i8>, <4 x i8>) nounwind
666 declare i32 @llvm.mips.rddsp(i32) nounwind readonly
668 define i32 @test__builtin_mips_cmpu_lt_qb1(i32 %i0, i32 %a0.coerce, i32 %a1.coerce) nounwind {
672 %0 = bitcast i32 %a0.coerce to <4 x i8>
673 %1 = bitcast i32 %a1.coerce to <4 x i8>
674 tail call void @llvm.mips.cmpu.lt.qb(<4 x i8> %0, <4 x i8> %1)
675 %2 = tail call i32 @llvm.mips.rddsp(i32 31)
679 declare void @llvm.mips.cmpu.lt.qb(<4 x i8>, <4 x i8>) nounwind
681 define i32 @test__builtin_mips_cmpu_le_qb1(i32 %i0, i32 %a0.coerce, i32 %a1.coerce) nounwind {
685 %0 = bitcast i32 %a0.coerce to <4 x i8>
686 %1 = bitcast i32 %a1.coerce to <4 x i8>
687 tail call void @llvm.mips.cmpu.le.qb(<4 x i8> %0, <4 x i8> %1)
688 %2 = tail call i32 @llvm.mips.rddsp(i32 31)
692 declare void @llvm.mips.cmpu.le.qb(<4 x i8>, <4 x i8>) nounwind
694 define i32 @test__builtin_mips_cmpgu_eq_qb1(i32 %i0, i32 %a0.coerce, i32 %a1.coerce) nounwind {
698 %0 = bitcast i32 %a0.coerce to <4 x i8>
699 %1 = bitcast i32 %a1.coerce to <4 x i8>
700 %2 = tail call i32 @llvm.mips.cmpgu.eq.qb(<4 x i8> %0, <4 x i8> %1)
704 declare i32 @llvm.mips.cmpgu.eq.qb(<4 x i8>, <4 x i8>) nounwind
706 define i32 @test__builtin_mips_cmpgu_lt_qb1(i32 %i0, i32 %a0.coerce, i32 %a1.coerce) nounwind {
710 %0 = bitcast i32 %a0.coerce to <4 x i8>
711 %1 = bitcast i32 %a1.coerce to <4 x i8>
712 %2 = tail call i32 @llvm.mips.cmpgu.lt.qb(<4 x i8> %0, <4 x i8> %1)
716 declare i32 @llvm.mips.cmpgu.lt.qb(<4 x i8>, <4 x i8>) nounwind
718 define i32 @test__builtin_mips_cmpgu_le_qb1(i32 %i0, i32 %a0.coerce, i32 %a1.coerce) nounwind {
722 %0 = bitcast i32 %a0.coerce to <4 x i8>
723 %1 = bitcast i32 %a1.coerce to <4 x i8>
724 %2 = tail call i32 @llvm.mips.cmpgu.le.qb(<4 x i8> %0, <4 x i8> %1)
728 declare i32 @llvm.mips.cmpgu.le.qb(<4 x i8>, <4 x i8>) nounwind
730 define i32 @test__builtin_mips_cmp_eq_ph1(i32 %i0, i32 %a0.coerce, i32 %a1.coerce) nounwind {
734 %0 = bitcast i32 %a0.coerce to <2 x i16>
735 %1 = bitcast i32 %a1.coerce to <2 x i16>
736 tail call void @llvm.mips.cmp.eq.ph(<2 x i16> %0, <2 x i16> %1)
737 %2 = tail call i32 @llvm.mips.rddsp(i32 31)
741 declare void @llvm.mips.cmp.eq.ph(<2 x i16>, <2 x i16>) nounwind
743 define i32 @test__builtin_mips_cmp_lt_ph1(i32 %i0, i32 %a0.coerce, i32 %a1.coerce) nounwind {
747 %0 = bitcast i32 %a0.coerce to <2 x i16>
748 %1 = bitcast i32 %a1.coerce to <2 x i16>
749 tail call void @llvm.mips.cmp.lt.ph(<2 x i16> %0, <2 x i16> %1)
750 %2 = tail call i32 @llvm.mips.rddsp(i32 31)
754 declare void @llvm.mips.cmp.lt.ph(<2 x i16>, <2 x i16>) nounwind
756 define i32 @test__builtin_mips_cmp_le_ph1(i32 %i0, i32 %a0.coerce, i32 %a1.coerce) nounwind {
760 %0 = bitcast i32 %a0.coerce to <2 x i16>
761 %1 = bitcast i32 %a1.coerce to <2 x i16>
762 tail call void @llvm.mips.cmp.le.ph(<2 x i16> %0, <2 x i16> %1)
763 %2 = tail call i32 @llvm.mips.rddsp(i32 31)
767 declare void @llvm.mips.cmp.le.ph(<2 x i16>, <2 x i16>) nounwind
769 define { i32 } @test__builtin_mips_pick_qb1(i32 %i0, i32 %a0.coerce, i32 %a1.coerce) nounwind readonly {
773 %0 = bitcast i32 %a0.coerce to <4 x i8>
774 %1 = bitcast i32 %a1.coerce to <4 x i8>
775 tail call void @llvm.mips.wrdsp(i32 %i0, i32 16)
776 %2 = tail call <4 x i8> @llvm.mips.pick.qb(<4 x i8> %0, <4 x i8> %1)
777 %3 = bitcast <4 x i8> %2 to i32
778 %.fca.0.insert = insertvalue { i32 } undef, i32 %3, 0
779 ret { i32 } %.fca.0.insert
782 declare <4 x i8> @llvm.mips.pick.qb(<4 x i8>, <4 x i8>) nounwind readonly
784 define { i32 } @test__builtin_mips_pick_ph1(i32 %i0, i32 %a0.coerce, i32 %a1.coerce) nounwind readonly {
788 %0 = bitcast i32 %a0.coerce to <2 x i16>
789 %1 = bitcast i32 %a1.coerce to <2 x i16>
790 tail call void @llvm.mips.wrdsp(i32 %i0, i32 16)
791 %2 = tail call <2 x i16> @llvm.mips.pick.ph(<2 x i16> %0, <2 x i16> %1)
792 %3 = bitcast <2 x i16> %2 to i32
793 %.fca.0.insert = insertvalue { i32 } undef, i32 %3, 0
794 ret { i32 } %.fca.0.insert
797 declare <2 x i16> @llvm.mips.pick.ph(<2 x i16>, <2 x i16>) nounwind readonly
799 define { i32 } @test__builtin_mips_packrl_ph1(i32 %i0, i32 %a0.coerce, i32 %a1.coerce) nounwind readnone {
803 %0 = bitcast i32 %a0.coerce to <2 x i16>
804 %1 = bitcast i32 %a1.coerce to <2 x i16>
805 %2 = tail call <2 x i16> @llvm.mips.packrl.ph(<2 x i16> %0, <2 x i16> %1)
806 %3 = bitcast <2 x i16> %2 to i32
807 %.fca.0.insert = insertvalue { i32 } undef, i32 %3, 0
808 ret { i32 } %.fca.0.insert
811 declare <2 x i16> @llvm.mips.packrl.ph(<2 x i16>, <2 x i16>) nounwind readnone
813 define { i32 } @test__builtin_mips_shll_qb1(i32 %i0, i32 %a0.coerce) nounwind {
817 %0 = bitcast i32 %a0.coerce to <4 x i8>
818 %1 = tail call <4 x i8> @llvm.mips.shll.qb(<4 x i8> %0, i32 3)
819 %2 = bitcast <4 x i8> %1 to i32
820 %.fca.0.insert = insertvalue { i32 } undef, i32 %2, 0
821 ret { i32 } %.fca.0.insert
824 declare <4 x i8> @llvm.mips.shll.qb(<4 x i8>, i32) nounwind
826 define { i32 } @test__builtin_mips_shll_qb2(i32 %i0, i32 %a0.coerce, i32 %a1) nounwind {
830 %0 = bitcast i32 %a0.coerce to <4 x i8>
831 %1 = tail call <4 x i8> @llvm.mips.shll.qb(<4 x i8> %0, i32 %a1)
832 %2 = bitcast <4 x i8> %1 to i32
833 %.fca.0.insert = insertvalue { i32 } undef, i32 %2, 0
834 ret { i32 } %.fca.0.insert
837 define { i32 } @test__builtin_mips_shll_ph1(i32 %i0, i32 %a0.coerce) nounwind {
841 %0 = bitcast i32 %a0.coerce to <2 x i16>
842 %1 = tail call <2 x i16> @llvm.mips.shll.ph(<2 x i16> %0, i32 7)
843 %2 = bitcast <2 x i16> %1 to i32
844 %.fca.0.insert = insertvalue { i32 } undef, i32 %2, 0
845 ret { i32 } %.fca.0.insert
848 declare <2 x i16> @llvm.mips.shll.ph(<2 x i16>, i32) nounwind
850 define { i32 } @test__builtin_mips_shll_ph2(i32 %i0, i32 %a0.coerce, i32 %a1) nounwind {
854 %0 = bitcast i32 %a0.coerce to <2 x i16>
855 %1 = tail call <2 x i16> @llvm.mips.shll.ph(<2 x i16> %0, i32 %a1)
856 %2 = bitcast <2 x i16> %1 to i32
857 %.fca.0.insert = insertvalue { i32 } undef, i32 %2, 0
858 ret { i32 } %.fca.0.insert
861 define { i32 } @test__builtin_mips_shll_s_ph1(i32 %i0, i32 %a0.coerce) nounwind {
865 %0 = bitcast i32 %a0.coerce to <2 x i16>
866 %1 = tail call <2 x i16> @llvm.mips.shll.s.ph(<2 x i16> %0, i32 7)
867 %2 = bitcast <2 x i16> %1 to i32
868 %.fca.0.insert = insertvalue { i32 } undef, i32 %2, 0
869 ret { i32 } %.fca.0.insert
872 declare <2 x i16> @llvm.mips.shll.s.ph(<2 x i16>, i32) nounwind
874 define { i32 } @test__builtin_mips_shll_s_ph2(i32 %i0, i32 %a0.coerce, i32 %a1) nounwind {
878 %0 = bitcast i32 %a0.coerce to <2 x i16>
879 %1 = tail call <2 x i16> @llvm.mips.shll.s.ph(<2 x i16> %0, i32 %a1)
880 %2 = bitcast <2 x i16> %1 to i32
881 %.fca.0.insert = insertvalue { i32 } undef, i32 %2, 0
882 ret { i32 } %.fca.0.insert
885 define i32 @test__builtin_mips_shll_s_w1(i32 %i0, i32 %a0) nounwind {
889 %0 = tail call i32 @llvm.mips.shll.s.w(i32 %a0, i32 15)
893 declare i32 @llvm.mips.shll.s.w(i32, i32) nounwind
895 define i32 @test__builtin_mips_shll_s_w2(i32 %i0, i32 %a0, i32 %a1) nounwind {
899 %0 = tail call i32 @llvm.mips.shll.s.w(i32 %a0, i32 %a1)
903 define { i32 } @test__builtin_mips_shrl_qb1(i32 %i0, i32 %a0.coerce) nounwind readnone {
907 %0 = bitcast i32 %a0.coerce to <4 x i8>
908 %1 = tail call <4 x i8> @llvm.mips.shrl.qb(<4 x i8> %0, i32 3)
909 %2 = bitcast <4 x i8> %1 to i32
910 %.fca.0.insert = insertvalue { i32 } undef, i32 %2, 0
911 ret { i32 } %.fca.0.insert
914 declare <4 x i8> @llvm.mips.shrl.qb(<4 x i8>, i32) nounwind readnone
916 define { i32 } @test__builtin_mips_shrl_qb2(i32 %i0, i32 %a0.coerce, i32 %a1) nounwind readnone {
920 %0 = bitcast i32 %a0.coerce to <4 x i8>
921 %1 = tail call <4 x i8> @llvm.mips.shrl.qb(<4 x i8> %0, i32 %a1)
922 %2 = bitcast <4 x i8> %1 to i32
923 %.fca.0.insert = insertvalue { i32 } undef, i32 %2, 0
924 ret { i32 } %.fca.0.insert
927 define { i32 } @test__builtin_mips_shra_ph1(i32 %i0, i32 %a0.coerce) nounwind readnone {
931 %0 = bitcast i32 %a0.coerce to <2 x i16>
932 %1 = tail call <2 x i16> @llvm.mips.shra.ph(<2 x i16> %0, i32 7)
933 %2 = bitcast <2 x i16> %1 to i32
934 %.fca.0.insert = insertvalue { i32 } undef, i32 %2, 0
935 ret { i32 } %.fca.0.insert
938 declare <2 x i16> @llvm.mips.shra.ph(<2 x i16>, i32) nounwind readnone
940 define { i32 } @test__builtin_mips_shra_ph2(i32 %i0, i32 %a0.coerce, i32 %a1) nounwind readnone {
944 %0 = bitcast i32 %a0.coerce to <2 x i16>
945 %1 = tail call <2 x i16> @llvm.mips.shra.ph(<2 x i16> %0, i32 %a1)
946 %2 = bitcast <2 x i16> %1 to i32
947 %.fca.0.insert = insertvalue { i32 } undef, i32 %2, 0
948 ret { i32 } %.fca.0.insert
951 define { i32 } @test__builtin_mips_shra_r_ph1(i32 %i0, i32 %a0.coerce) nounwind readnone {
955 %0 = bitcast i32 %a0.coerce to <2 x i16>
956 %1 = tail call <2 x i16> @llvm.mips.shra.r.ph(<2 x i16> %0, i32 7)
957 %2 = bitcast <2 x i16> %1 to i32
958 %.fca.0.insert = insertvalue { i32 } undef, i32 %2, 0
959 ret { i32 } %.fca.0.insert
962 declare <2 x i16> @llvm.mips.shra.r.ph(<2 x i16>, i32) nounwind readnone
964 define { i32 } @test__builtin_mips_shra_r_ph2(i32 %i0, i32 %a0.coerce, i32 %a1) nounwind readnone {
968 %0 = bitcast i32 %a0.coerce to <2 x i16>
969 %1 = tail call <2 x i16> @llvm.mips.shra.r.ph(<2 x i16> %0, i32 %a1)
970 %2 = bitcast <2 x i16> %1 to i32
971 %.fca.0.insert = insertvalue { i32 } undef, i32 %2, 0
972 ret { i32 } %.fca.0.insert
975 define i32 @test__builtin_mips_shra_r_w1(i32 %i0, i32 %a0) nounwind readnone {
979 %0 = tail call i32 @llvm.mips.shra.r.w(i32 %a0, i32 15)
983 declare i32 @llvm.mips.shra.r.w(i32, i32) nounwind readnone
985 define i32 @test__builtin_mips_shra_r_w2(i32 %i0, i32 %a0, i32 %a1) nounwind readnone {
989 %0 = tail call i32 @llvm.mips.shra.r.w(i32 %a0, i32 %a1)
993 define { i32 } @test__builtin_mips_absq_s_ph1(i32 %i0, i32 %a0.coerce) nounwind {
997 %0 = bitcast i32 %a0.coerce to <2 x i16>
998 %1 = tail call <2 x i16> @llvm.mips.absq.s.ph(<2 x i16> %0)
999 %2 = bitcast <2 x i16> %1 to i32
1000 %.fca.0.insert = insertvalue { i32 } undef, i32 %2, 0
1001 ret { i32 } %.fca.0.insert
1004 declare <2 x i16> @llvm.mips.absq.s.ph(<2 x i16>) nounwind
1006 define i32 @test__builtin_mips_absq_s_w1(i32 %i0, i32 %a0) nounwind {
1010 %0 = tail call i32 @llvm.mips.absq.s.w(i32 %a0)
1014 declare i32 @llvm.mips.absq.s.w(i32) nounwind
1016 define i32 @test__builtin_mips_preceq_w_phl1(i32 %i0, i32 %a0.coerce) nounwind readnone {
1018 ; CHECK: preceq.w.phl
1020 %0 = bitcast i32 %a0.coerce to <2 x i16>
1021 %1 = tail call i32 @llvm.mips.preceq.w.phl(<2 x i16> %0)
1025 declare i32 @llvm.mips.preceq.w.phl(<2 x i16>) nounwind readnone
1027 define i32 @test__builtin_mips_preceq_w_phr1(i32 %i0, i32 %a0.coerce) nounwind readnone {
1029 ; CHECK: preceq.w.phr
1031 %0 = bitcast i32 %a0.coerce to <2 x i16>
1032 %1 = tail call i32 @llvm.mips.preceq.w.phr(<2 x i16> %0)
1036 declare i32 @llvm.mips.preceq.w.phr(<2 x i16>) nounwind readnone
1038 define { i32 } @test__builtin_mips_precequ_ph_qbl1(i32 %i0, i32 %a0.coerce) nounwind readnone {
1040 ; CHECK: precequ.ph.qbl
1042 %0 = bitcast i32 %a0.coerce to <4 x i8>
1043 %1 = tail call <2 x i16> @llvm.mips.precequ.ph.qbl(<4 x i8> %0)
1044 %2 = bitcast <2 x i16> %1 to i32
1045 %.fca.0.insert = insertvalue { i32 } undef, i32 %2, 0
1046 ret { i32 } %.fca.0.insert
1049 declare <2 x i16> @llvm.mips.precequ.ph.qbl(<4 x i8>) nounwind readnone
1051 define { i32 } @test__builtin_mips_precequ_ph_qbr1(i32 %i0, i32 %a0.coerce) nounwind readnone {
1053 ; CHECK: precequ.ph.qbr
1055 %0 = bitcast i32 %a0.coerce to <4 x i8>
1056 %1 = tail call <2 x i16> @llvm.mips.precequ.ph.qbr(<4 x i8> %0)
1057 %2 = bitcast <2 x i16> %1 to i32
1058 %.fca.0.insert = insertvalue { i32 } undef, i32 %2, 0
1059 ret { i32 } %.fca.0.insert
1062 declare <2 x i16> @llvm.mips.precequ.ph.qbr(<4 x i8>) nounwind readnone
1064 define { i32 } @test__builtin_mips_precequ_ph_qbla1(i32 %i0, i32 %a0.coerce) nounwind readnone {
1066 ; CHECK: precequ.ph.qbla
1068 %0 = bitcast i32 %a0.coerce to <4 x i8>
1069 %1 = tail call <2 x i16> @llvm.mips.precequ.ph.qbla(<4 x i8> %0)
1070 %2 = bitcast <2 x i16> %1 to i32
1071 %.fca.0.insert = insertvalue { i32 } undef, i32 %2, 0
1072 ret { i32 } %.fca.0.insert
1075 declare <2 x i16> @llvm.mips.precequ.ph.qbla(<4 x i8>) nounwind readnone
1077 define { i32 } @test__builtin_mips_precequ_ph_qbra1(i32 %i0, i32 %a0.coerce) nounwind readnone {
1079 ; CHECK: precequ.ph.qbra
1081 %0 = bitcast i32 %a0.coerce to <4 x i8>
1082 %1 = tail call <2 x i16> @llvm.mips.precequ.ph.qbra(<4 x i8> %0)
1083 %2 = bitcast <2 x i16> %1 to i32
1084 %.fca.0.insert = insertvalue { i32 } undef, i32 %2, 0
1085 ret { i32 } %.fca.0.insert
1088 declare <2 x i16> @llvm.mips.precequ.ph.qbra(<4 x i8>) nounwind readnone
1090 define { i32 } @test__builtin_mips_preceu_ph_qbl1(i32 %i0, i32 %a0.coerce) nounwind readnone {
1092 ; CHECK: preceu.ph.qbl
1094 %0 = bitcast i32 %a0.coerce to <4 x i8>
1095 %1 = tail call <2 x i16> @llvm.mips.preceu.ph.qbl(<4 x i8> %0)
1096 %2 = bitcast <2 x i16> %1 to i32
1097 %.fca.0.insert = insertvalue { i32 } undef, i32 %2, 0
1098 ret { i32 } %.fca.0.insert
1101 declare <2 x i16> @llvm.mips.preceu.ph.qbl(<4 x i8>) nounwind readnone
1103 define { i32 } @test__builtin_mips_preceu_ph_qbr1(i32 %i0, i32 %a0.coerce) nounwind readnone {
1105 ; CHECK: preceu.ph.qbr
1107 %0 = bitcast i32 %a0.coerce to <4 x i8>
1108 %1 = tail call <2 x i16> @llvm.mips.preceu.ph.qbr(<4 x i8> %0)
1109 %2 = bitcast <2 x i16> %1 to i32
1110 %.fca.0.insert = insertvalue { i32 } undef, i32 %2, 0
1111 ret { i32 } %.fca.0.insert
1114 declare <2 x i16> @llvm.mips.preceu.ph.qbr(<4 x i8>) nounwind readnone
1116 define { i32 } @test__builtin_mips_preceu_ph_qbla1(i32 %i0, i32 %a0.coerce) nounwind readnone {
1118 ; CHECK: preceu.ph.qbla
1120 %0 = bitcast i32 %a0.coerce to <4 x i8>
1121 %1 = tail call <2 x i16> @llvm.mips.preceu.ph.qbla(<4 x i8> %0)
1122 %2 = bitcast <2 x i16> %1 to i32
1123 %.fca.0.insert = insertvalue { i32 } undef, i32 %2, 0
1124 ret { i32 } %.fca.0.insert
1127 declare <2 x i16> @llvm.mips.preceu.ph.qbla(<4 x i8>) nounwind readnone
1129 define { i32 } @test__builtin_mips_preceu_ph_qbra1(i32 %i0, i32 %a0.coerce) nounwind readnone {
1131 ; CHECK: preceu.ph.qbra
1133 %0 = bitcast i32 %a0.coerce to <4 x i8>
1134 %1 = tail call <2 x i16> @llvm.mips.preceu.ph.qbra(<4 x i8> %0)
1135 %2 = bitcast <2 x i16> %1 to i32
1136 %.fca.0.insert = insertvalue { i32 } undef, i32 %2, 0
1137 ret { i32 } %.fca.0.insert
1140 declare <2 x i16> @llvm.mips.preceu.ph.qbra(<4 x i8>) nounwind readnone
1142 define { i32 } @test__builtin_mips_repl_qb1(i32 %i0) nounwind readnone {
1146 %0 = tail call <4 x i8> @llvm.mips.repl.qb(i32 127)
1147 %1 = bitcast <4 x i8> %0 to i32
1148 %.fca.0.insert = insertvalue { i32 } undef, i32 %1, 0
1149 ret { i32 } %.fca.0.insert
1152 declare <4 x i8> @llvm.mips.repl.qb(i32) nounwind readnone
1154 define { i32 } @test__builtin_mips_repl_qb2(i32 %i0, i32 %a0) nounwind readnone {
1158 %0 = tail call <4 x i8> @llvm.mips.repl.qb(i32 %a0)
1159 %1 = bitcast <4 x i8> %0 to i32
1160 %.fca.0.insert = insertvalue { i32 } undef, i32 %1, 0
1161 ret { i32 } %.fca.0.insert
1164 define { i32 } @test__builtin_mips_repl_ph1(i32 %i0) nounwind readnone {
1168 %0 = tail call <2 x i16> @llvm.mips.repl.ph(i32 0)
1169 %1 = bitcast <2 x i16> %0 to i32
1170 %.fca.0.insert = insertvalue { i32 } undef, i32 %1, 0
1171 ret { i32 } %.fca.0.insert
1174 declare <2 x i16> @llvm.mips.repl.ph(i32) nounwind readnone
1176 define { i32 } @test__builtin_mips_repl_ph2(i32 %i0, i32 %a0) nounwind readnone {
1180 %0 = tail call <2 x i16> @llvm.mips.repl.ph(i32 %a0)
1181 %1 = bitcast <2 x i16> %0 to i32
1182 %.fca.0.insert = insertvalue { i32 } undef, i32 %1, 0
1183 ret { i32 } %.fca.0.insert
1186 define i32 @test__builtin_mips_bitrev1(i32 %i0, i32 %a0) nounwind readnone {
1188 ; CHECK: bitrev ${{[0-9]+}}
1190 %0 = tail call i32 @llvm.mips.bitrev(i32 %a0)
1194 declare i32 @llvm.mips.bitrev(i32) nounwind readnone
1196 define i32 @test__builtin_mips_lbux1(i32 %i0, i8* %a0, i32 %a1) nounwind readonly {
1198 ; CHECK: lbux ${{[0-9]+}}
1200 %0 = tail call i32 @llvm.mips.lbux(i8* %a0, i32 %a1)
1204 declare i32 @llvm.mips.lbux(i8*, i32) nounwind readonly
1206 define i32 @test__builtin_mips_lhx1(i32 %i0, i8* %a0, i32 %a1) nounwind readonly {
1208 ; CHECK: lhx ${{[0-9]+}}
1210 %0 = tail call i32 @llvm.mips.lhx(i8* %a0, i32 %a1)
1214 declare i32 @llvm.mips.lhx(i8*, i32) nounwind readonly
1216 define i32 @test__builtin_mips_lwx1(i32 %i0, i8* %a0, i32 %a1) nounwind readonly {
1218 ; CHECK: lwx ${{[0-9]+}}
1220 %0 = tail call i32 @llvm.mips.lwx(i8* %a0, i32 %a1)
1224 declare i32 @llvm.mips.lwx(i8*, i32) nounwind readonly
1226 define i32 @test__builtin_mips_wrdsp1(i32 %i0, i32 %a0) nounwind {
1228 ; CHECK: wrdsp ${{[0-9]+}}
1229 ; CHECK: rddsp ${{[0-9]+}}
1231 tail call void @llvm.mips.wrdsp(i32 %a0, i32 31)
1232 %0 = tail call i32 @llvm.mips.rddsp(i32 31)
1236 declare void @llvm.mips.wrdsp(i32, i32) nounwind