1 ; RUN: llc < %s -march=mips -mcpu=mips32 | \
2 ; RUN: FileCheck %s -check-prefix=ALL -check-prefix=32-C
3 ; RUN: llc < %s -march=mips -mcpu=mips32r2 | \
4 ; RUN: FileCheck %s -check-prefix=ALL -check-prefix=32-C
5 ; RUN: llc < %s -march=mips -mcpu=mips32r6 | \
6 ; RUN: FileCheck %s -check-prefix=ALL -check-prefix=32-CMP
7 ; RUN: llc < %s -march=mips64 -mcpu=mips4 | \
8 ; RUN: FileCheck %s -check-prefix=ALL -check-prefix=64-C
9 ; RUN: llc < %s -march=mips64 -mcpu=mips64 | \
10 ; RUN: FileCheck %s -check-prefix=ALL -check-prefix=64-C
11 ; RUN: llc < %s -march=mips64 -mcpu=mips64r2 | \
12 ; RUN: FileCheck %s -check-prefix=ALL -check-prefix=64-C
13 ; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | \
14 ; RUN: FileCheck %s -check-prefix=ALL -check-prefix=64-CMP
16 define i32 @false_f32(float %a, float %b) nounwind {
17 ; ALL-LABEL: false_f32:
18 ; ALL: addiu $2, $zero, 0
20 %1 = fcmp false float %a, %b
21 %2 = zext i1 %1 to i32
25 define i32 @oeq_f32(float %a, float %b) nounwind {
28 ; 32-C-DAG: addiu $2, $zero, 1
29 ; 32-C-DAG: c.eq.s $f12, $f14
30 ; 32-C: movf $2, $zero, $fcc0
32 ; 64-C-DAG: addiu $2, $zero, 1
33 ; 64-C-DAG: c.eq.s $f12, $f13
34 ; 64-C: movf $2, $zero, $fcc0
36 ; 32-CMP-DAG: cmp.eq.s $[[T0:f[0-9]+]], $f12, $f14
37 ; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
38 ; 32-CMP-DAG: andi $2, $[[T1]], 1
40 ; 64-CMP-DAG: cmp.eq.s $[[T0:f[0-9]+]], $f12, $f13
41 ; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
42 ; 64-CMP-DAG: andi $2, $[[T1]], 1
44 %1 = fcmp oeq float %a, %b
45 %2 = zext i1 %1 to i32
49 define i32 @ogt_f32(float %a, float %b) nounwind {
52 ; 32-C-DAG: addiu $2, $zero, 1
53 ; 32-C-DAG: c.ule.s $f12, $f14
54 ; 32-C: movt $2, $zero, $fcc0
56 ; 64-C-DAG: addiu $2, $zero, 1
57 ; 64-C-DAG: c.ule.s $f12, $f13
58 ; 64-C: movt $2, $zero, $fcc0
60 ; 32-CMP-DAG: cmp.lt.s $[[T0:f[0-9]+]], $f14, $f12
61 ; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
62 ; 32-CMP-DAG: andi $2, $[[T1]], 1
64 ; 64-CMP-DAG: cmp.lt.s $[[T0:f[0-9]+]], $f13, $f12
65 ; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
66 ; 64-CMP-DAG: andi $2, $[[T1]], 1
68 %1 = fcmp ogt float %a, %b
69 %2 = zext i1 %1 to i32
73 define i32 @oge_f32(float %a, float %b) nounwind {
76 ; 32-C-DAG: addiu $2, $zero, 1
77 ; 32-C-DAG: c.ult.s $f12, $f14
78 ; 32-C: movt $2, $zero, $fcc0
80 ; 64-C-DAG: addiu $2, $zero, 1
81 ; 64-C-DAG: c.ult.s $f12, $f13
82 ; 64-C: movt $2, $zero, $fcc0
84 ; 32-CMP-DAG: cmp.le.s $[[T0:f[0-9]+]], $f14, $f12
85 ; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
86 ; 32-CMP-DAG: andi $2, $[[T1]], 1
88 ; 64-CMP-DAG: cmp.le.s $[[T0:f[0-9]+]], $f13, $f12
89 ; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
90 ; 64-CMP-DAG: andi $2, $[[T1]], 1
92 %1 = fcmp oge float %a, %b
93 %2 = zext i1 %1 to i32
97 define i32 @olt_f32(float %a, float %b) nounwind {
100 ; 32-C-DAG: addiu $2, $zero, 1
101 ; 32-C-DAG: c.olt.s $f12, $f14
102 ; 32-C: movf $2, $zero, $fcc0
104 ; 64-C-DAG: addiu $2, $zero, 1
105 ; 64-C-DAG: c.olt.s $f12, $f13
106 ; 64-C: movf $2, $zero, $fcc0
108 ; 32-CMP-DAG: cmp.lt.s $[[T0:f[0-9]+]], $f12, $f14
109 ; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
110 ; 32-CMP-DAG: andi $2, $[[T1]], 1
112 ; 64-CMP-DAG: cmp.lt.s $[[T0:f[0-9]+]], $f12, $f13
113 ; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
114 ; 64-CMP-DAG: andi $2, $[[T1]], 1
116 %1 = fcmp olt float %a, %b
117 %2 = zext i1 %1 to i32
121 define i32 @ole_f32(float %a, float %b) nounwind {
122 ; ALL-LABEL: ole_f32:
124 ; 32-C-DAG: addiu $2, $zero, 1
125 ; 32-C-DAG: c.ole.s $f12, $f14
126 ; 32-C: movf $2, $zero, $fcc0
128 ; 64-C-DAG: addiu $2, $zero, 1
129 ; 64-C-DAG: c.ole.s $f12, $f13
130 ; 64-C: movf $2, $zero, $fcc0
132 ; 32-CMP-DAG: cmp.le.s $[[T0:f[0-9]+]], $f12, $f14
133 ; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
134 ; 32-CMP-DAG: andi $2, $[[T1]], 1
136 ; 64-CMP-DAG: cmp.le.s $[[T0:f[0-9]+]], $f12, $f13
137 ; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
138 ; 64-CMP-DAG: andi $2, $[[T1]], 1
140 %1 = fcmp ole float %a, %b
141 %2 = zext i1 %1 to i32
145 define i32 @one_f32(float %a, float %b) nounwind {
146 ; ALL-LABEL: one_f32:
148 ; 32-C-DAG: addiu $2, $zero, 1
149 ; 32-C-DAG: c.ueq.s $f12, $f14
150 ; 32-C: movt $2, $zero, $fcc0
152 ; 64-C-DAG: addiu $2, $zero, 1
153 ; 64-C-DAG: c.ueq.s $f12, $f13
154 ; 64-C: movt $2, $zero, $fcc0
156 ; 32-CMP-DAG: cmp.ueq.s $[[T0:f[0-9]+]], $f12, $f14
157 ; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
158 ; 32-CMP-DAG: not $[[T2:[0-9]+]], $[[T1]]
159 ; 32-CMP-DAG: andi $2, $[[T2]], 1
161 ; 64-CMP-DAG: cmp.ueq.s $[[T0:f[0-9]+]], $f12, $f13
162 ; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
163 ; 64-CMP-DAG: not $[[T2:[0-9]+]], $[[T1]]
164 ; 64-CMP-DAG: andi $2, $[[T2]], 1
166 %1 = fcmp one float %a, %b
167 %2 = zext i1 %1 to i32
171 define i32 @ord_f32(float %a, float %b) nounwind {
172 ; ALL-LABEL: ord_f32:
174 ; 32-C-DAG: addiu $2, $zero, 1
175 ; 32-C-DAG: c.un.s $f12, $f14
176 ; 32-C: movt $2, $zero, $fcc0
178 ; 64-C-DAG: addiu $2, $zero, 1
179 ; 64-C-DAG: c.un.s $f12, $f13
180 ; 64-C: movt $2, $zero, $fcc0
182 ; 32-CMP-DAG: cmp.un.s $[[T0:f[0-9]+]], $f12, $f14
183 ; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
184 ; 32-CMP-DAG: not $[[T2:[0-9]+]], $[[T1]]
185 ; 32-CMP-DAG: andi $2, $[[T2]], 1
187 ; 64-CMP-DAG: cmp.un.s $[[T0:f[0-9]+]], $f12, $f13
188 ; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
189 ; 64-CMP-DAG: not $[[T2:[0-9]+]], $[[T1]]
190 ; 64-CMP-DAG: andi $2, $[[T2]], 1
192 %1 = fcmp ord float %a, %b
193 %2 = zext i1 %1 to i32
197 define i32 @ueq_f32(float %a, float %b) nounwind {
198 ; ALL-LABEL: ueq_f32:
200 ; 32-C-DAG: addiu $2, $zero, 1
201 ; 32-C-DAG: c.ueq.s $f12, $f14
202 ; 32-C: movf $2, $zero, $fcc0
204 ; 64-C-DAG: addiu $2, $zero, 1
205 ; 64-C-DAG: c.ueq.s $f12, $f13
206 ; 64-C: movf $2, $zero, $fcc0
208 ; 32-CMP-DAG: cmp.ueq.s $[[T0:f[0-9]+]], $f12, $f14
209 ; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
210 ; 32-CMP-DAG: andi $2, $[[T1]], 1
212 ; 64-CMP-DAG: cmp.ueq.s $[[T0:f[0-9]+]], $f12, $f13
213 ; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
214 ; 64-CMP-DAG: andi $2, $[[T1]], 1
216 %1 = fcmp ueq float %a, %b
217 %2 = zext i1 %1 to i32
221 define i32 @ugt_f32(float %a, float %b) nounwind {
222 ; ALL-LABEL: ugt_f32:
224 ; 32-C-DAG: addiu $2, $zero, 1
225 ; 32-C-DAG: c.ole.s $f12, $f14
226 ; 32-C: movt $2, $zero, $fcc0
228 ; 64-C-DAG: addiu $2, $zero, 1
229 ; 64-C-DAG: c.ole.s $f12, $f13
230 ; 64-C: movt $2, $zero, $fcc0
232 ; 32-CMP-DAG: cmp.ult.s $[[T0:f[0-9]+]], $f14, $f12
233 ; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
234 ; 32-CMP-DAG: andi $2, $[[T1]], 1
236 ; 64-CMP-DAG: cmp.ult.s $[[T0:f[0-9]+]], $f13, $f12
237 ; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
238 ; 64-CMP-DAG: andi $2, $[[T1]], 1
240 %1 = fcmp ugt float %a, %b
241 %2 = zext i1 %1 to i32
245 define i32 @uge_f32(float %a, float %b) nounwind {
246 ; ALL-LABEL: uge_f32:
248 ; 32-C-DAG: addiu $2, $zero, 1
249 ; 32-C-DAG: c.olt.s $f12, $f14
250 ; 32-C: movt $2, $zero, $fcc0
252 ; 64-C-DAG: addiu $2, $zero, 1
253 ; 64-C-DAG: c.olt.s $f12, $f13
254 ; 64-C: movt $2, $zero, $fcc0
256 ; 32-CMP-DAG: cmp.ule.s $[[T0:f[0-9]+]], $f14, $f12
257 ; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
258 ; 32-CMP-DAG: andi $2, $[[T1]], 1
260 ; 64-CMP-DAG: cmp.ule.s $[[T0:f[0-9]+]], $f13, $f12
261 ; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
262 ; 64-CMP-DAG: andi $2, $[[T1]], 1
264 %1 = fcmp uge float %a, %b
265 %2 = zext i1 %1 to i32
269 define i32 @ult_f32(float %a, float %b) nounwind {
270 ; ALL-LABEL: ult_f32:
272 ; 32-C-DAG: addiu $2, $zero, 1
273 ; 32-C-DAG: c.ult.s $f12, $f14
274 ; 32-C: movf $2, $zero, $fcc0
276 ; 64-C-DAG: addiu $2, $zero, 1
277 ; 64-C-DAG: c.ult.s $f12, $f13
278 ; 64-C: movf $2, $zero, $fcc0
280 ; 32-CMP-DAG: cmp.ult.s $[[T0:f[0-9]+]], $f12, $f14
281 ; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
282 ; 32-CMP-DAG: andi $2, $[[T1]], 1
284 ; 64-CMP-DAG: cmp.ult.s $[[T0:f[0-9]+]], $f12, $f13
285 ; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
286 ; 64-CMP-DAG: andi $2, $[[T1]], 1
289 %1 = fcmp ult float %a, %b
290 %2 = zext i1 %1 to i32
294 define i32 @ule_f32(float %a, float %b) nounwind {
295 ; ALL-LABEL: ule_f32:
297 ; 32-C-DAG: addiu $2, $zero, 1
298 ; 32-C-DAG: c.ule.s $f12, $f14
299 ; 32-C: movf $2, $zero, $fcc0
301 ; 64-C-DAG: addiu $2, $zero, 1
302 ; 64-C-DAG: c.ule.s $f12, $f13
303 ; 64-C: movf $2, $zero, $fcc0
305 ; 32-CMP-DAG: cmp.ule.s $[[T0:f[0-9]+]], $f12, $f14
306 ; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
307 ; 32-CMP-DAG: andi $2, $[[T1]], 1
309 ; 64-CMP-DAG: cmp.ule.s $[[T0:f[0-9]+]], $f12, $f13
310 ; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
311 ; 64-CMP-DAG: andi $2, $[[T1]], 1
313 %1 = fcmp ule float %a, %b
314 %2 = zext i1 %1 to i32
318 define i32 @une_f32(float %a, float %b) nounwind {
319 ; ALL-LABEL: une_f32:
321 ; 32-C-DAG: addiu $2, $zero, 1
322 ; 32-C-DAG: c.eq.s $f12, $f14
323 ; 32-C: movt $2, $zero, $fcc0
325 ; 64-C-DAG: addiu $2, $zero, 1
326 ; 64-C-DAG: c.eq.s $f12, $f13
327 ; 64-C: movt $2, $zero, $fcc0
329 ; 32-CMP-DAG: cmp.eq.s $[[T0:f[0-9]+]], $f12, $f14
330 ; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
331 ; 32-CMP-DAG: not $[[T2:[0-9]+]], $[[T1]]
332 ; 32-CMP-DAG: andi $2, $[[T2]], 1
334 ; 64-CMP-DAG: cmp.eq.s $[[T0:f[0-9]+]], $f12, $f13
335 ; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
336 ; 64-CMP-DAG: not $[[T2:[0-9]+]], $[[T1]]
337 ; 64-CMP-DAG: andi $2, $[[T2]], 1
339 %1 = fcmp une float %a, %b
340 %2 = zext i1 %1 to i32
344 define i32 @uno_f32(float %a, float %b) nounwind {
345 ; ALL-LABEL: uno_f32:
347 ; 32-C-DAG: addiu $2, $zero, 1
348 ; 32-C-DAG: c.un.s $f12, $f14
349 ; 32-C: movf $2, $zero, $fcc0
351 ; 64-C-DAG: addiu $2, $zero, 1
352 ; 64-C-DAG: c.un.s $f12, $f13
353 ; 64-C: movf $2, $zero, $fcc0
355 ; 32-CMP-DAG: cmp.un.s $[[T0:f[0-9]+]], $f12, $f14
356 ; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
357 ; 32-CMP-DAG: andi $2, $[[T1]], 1
359 ; 64-CMP-DAG: cmp.un.s $[[T0:f[0-9]+]], $f12, $f13
360 ; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
361 ; 64-CMP-DAG: andi $2, $[[T1]], 1
363 %1 = fcmp uno float %a, %b
364 %2 = zext i1 %1 to i32
368 define i32 @true_f32(float %a, float %b) nounwind {
369 ; ALL-LABEL: true_f32:
370 ; ALL: addiu $2, $zero, 1
372 %1 = fcmp true float %a, %b
373 %2 = zext i1 %1 to i32
377 define i32 @false_f64(double %a, double %b) nounwind {
378 ; ALL-LABEL: false_f64:
379 ; ALL: addiu $2, $zero, 0
381 %1 = fcmp false double %a, %b
382 %2 = zext i1 %1 to i32
386 define i32 @oeq_f64(double %a, double %b) nounwind {
387 ; ALL-LABEL: oeq_f64:
389 ; 32-C-DAG: addiu $2, $zero, 1
390 ; 32-C-DAG: c.eq.d $f12, $f14
391 ; 32-C: movf $2, $zero, $fcc0
393 ; 64-C-DAG: addiu $2, $zero, 1
394 ; 64-C-DAG: c.eq.d $f12, $f13
395 ; 64-C: movf $2, $zero, $fcc0
397 ; 32-CMP-DAG: cmp.eq.d $[[T0:f[0-9]+]], $f12, $f14
398 ; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
399 ; 32-CMP-DAG: andi $2, $[[T1]], 1
401 ; 64-CMP-DAG: cmp.eq.d $[[T0:f[0-9]+]], $f12, $f13
402 ; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
403 ; 64-CMP-DAG: andi $2, $[[T1]], 1
405 %1 = fcmp oeq double %a, %b
406 %2 = zext i1 %1 to i32
410 define i32 @ogt_f64(double %a, double %b) nounwind {
411 ; ALL-LABEL: ogt_f64:
413 ; 32-C-DAG: addiu $2, $zero, 1
414 ; 32-C-DAG: c.ule.d $f12, $f14
415 ; 32-C: movt $2, $zero, $fcc0
417 ; 64-C-DAG: addiu $2, $zero, 1
418 ; 64-C-DAG: c.ule.d $f12, $f13
419 ; 64-C: movt $2, $zero, $fcc0
421 ; 32-CMP-DAG: cmp.lt.d $[[T0:f[0-9]+]], $f14, $f12
422 ; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
423 ; 32-CMP-DAG: andi $2, $[[T1]], 1
425 ; 64-CMP-DAG: cmp.lt.d $[[T0:f[0-9]+]], $f13, $f12
426 ; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
427 ; 64-CMP-DAG: andi $2, $[[T1]], 1
429 %1 = fcmp ogt double %a, %b
430 %2 = zext i1 %1 to i32
434 define i32 @oge_f64(double %a, double %b) nounwind {
435 ; ALL-LABEL: oge_f64:
437 ; 32-C-DAG: addiu $2, $zero, 1
438 ; 32-C-DAG: c.ult.d $f12, $f14
439 ; 32-C: movt $2, $zero, $fcc0
441 ; 64-C-DAG: addiu $2, $zero, 1
442 ; 64-C-DAG: c.ult.d $f12, $f13
443 ; 64-C: movt $2, $zero, $fcc0
445 ; 32-CMP-DAG: cmp.le.d $[[T0:f[0-9]+]], $f14, $f12
446 ; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
447 ; 32-CMP-DAG: andi $2, $[[T1]], 1
449 ; 64-CMP-DAG: cmp.le.d $[[T0:f[0-9]+]], $f13, $f12
450 ; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
451 ; 64-CMP-DAG: andi $2, $[[T1]], 1
453 %1 = fcmp oge double %a, %b
454 %2 = zext i1 %1 to i32
458 define i32 @olt_f64(double %a, double %b) nounwind {
459 ; ALL-LABEL: olt_f64:
461 ; 32-C-DAG: addiu $2, $zero, 1
462 ; 32-C-DAG: c.olt.d $f12, $f14
463 ; 32-C: movf $2, $zero, $fcc0
465 ; 64-C-DAG: addiu $2, $zero, 1
466 ; 64-C-DAG: c.olt.d $f12, $f13
467 ; 64-C: movf $2, $zero, $fcc0
469 ; 32-CMP-DAG: cmp.lt.d $[[T0:f[0-9]+]], $f12, $f14
470 ; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
471 ; 32-CMP-DAG: andi $2, $[[T1]], 1
473 ; 64-CMP-DAG: cmp.lt.d $[[T0:f[0-9]+]], $f12, $f13
474 ; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
475 ; 64-CMP-DAG: andi $2, $[[T1]], 1
477 %1 = fcmp olt double %a, %b
478 %2 = zext i1 %1 to i32
482 define i32 @ole_f64(double %a, double %b) nounwind {
483 ; ALL-LABEL: ole_f64:
485 ; 32-C-DAG: addiu $2, $zero, 1
486 ; 32-C-DAG: c.ole.d $f12, $f14
487 ; 32-C: movf $2, $zero, $fcc0
489 ; 64-C-DAG: addiu $2, $zero, 1
490 ; 64-C-DAG: c.ole.d $f12, $f13
491 ; 64-C: movf $2, $zero, $fcc0
493 ; 32-CMP-DAG: cmp.le.d $[[T0:f[0-9]+]], $f12, $f14
494 ; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
495 ; 32-CMP-DAG: andi $2, $[[T1]], 1
497 ; 64-CMP-DAG: cmp.le.d $[[T0:f[0-9]+]], $f12, $f13
498 ; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
499 ; 64-CMP-DAG: andi $2, $[[T1]], 1
501 %1 = fcmp ole double %a, %b
502 %2 = zext i1 %1 to i32
506 define i32 @one_f64(double %a, double %b) nounwind {
507 ; ALL-LABEL: one_f64:
509 ; 32-C-DAG: addiu $2, $zero, 1
510 ; 32-C-DAG: c.ueq.d $f12, $f14
511 ; 32-C: movt $2, $zero, $fcc0
513 ; 64-C-DAG: addiu $2, $zero, 1
514 ; 64-C-DAG: c.ueq.d $f12, $f13
515 ; 64-C: movt $2, $zero, $fcc0
517 ; 32-CMP-DAG: cmp.ueq.d $[[T0:f[0-9]+]], $f12, $f14
518 ; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
519 ; 32-CMP-DAG: not $[[T2:[0-9]+]], $[[T1]]
520 ; 32-CMP-DAG: andi $2, $[[T2]], 1
522 ; 64-CMP-DAG: cmp.ueq.d $[[T0:f[0-9]+]], $f12, $f13
523 ; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
524 ; 64-CMP-DAG: not $[[T2:[0-9]+]], $[[T1]]
525 ; 64-CMP-DAG: andi $2, $[[T2]], 1
527 %1 = fcmp one double %a, %b
528 %2 = zext i1 %1 to i32
532 define i32 @ord_f64(double %a, double %b) nounwind {
533 ; ALL-LABEL: ord_f64:
535 ; 32-C-DAG: addiu $2, $zero, 1
536 ; 32-C-DAG: c.un.d $f12, $f14
537 ; 32-C: movt $2, $zero, $fcc0
539 ; 64-C-DAG: addiu $2, $zero, 1
540 ; 64-C-DAG: c.un.d $f12, $f13
541 ; 64-C: movt $2, $zero, $fcc0
543 ; 32-CMP-DAG: cmp.un.d $[[T0:f[0-9]+]], $f12, $f14
544 ; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
545 ; 32-CMP-DAG: not $[[T2:[0-9]+]], $[[T1]]
546 ; 32-CMP-DAG: andi $2, $[[T2]], 1
548 ; 64-CMP-DAG: cmp.un.d $[[T0:f[0-9]+]], $f12, $f13
549 ; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
550 ; 64-CMP-DAG: not $[[T2:[0-9]+]], $[[T1]]
551 ; 64-CMP-DAG: andi $2, $[[T2]], 1
553 %1 = fcmp ord double %a, %b
554 %2 = zext i1 %1 to i32
558 define i32 @ueq_f64(double %a, double %b) nounwind {
559 ; ALL-LABEL: ueq_f64:
561 ; 32-C-DAG: addiu $2, $zero, 1
562 ; 32-C-DAG: c.ueq.d $f12, $f14
563 ; 32-C: movf $2, $zero, $fcc0
565 ; 64-C-DAG: addiu $2, $zero, 1
566 ; 64-C-DAG: c.ueq.d $f12, $f13
567 ; 64-C: movf $2, $zero, $fcc0
569 ; 32-CMP-DAG: cmp.ueq.d $[[T0:f[0-9]+]], $f12, $f14
570 ; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
571 ; 32-CMP-DAG: andi $2, $[[T1]], 1
573 ; 64-CMP-DAG: cmp.ueq.d $[[T0:f[0-9]+]], $f12, $f13
574 ; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
575 ; 64-CMP-DAG: andi $2, $[[T1]], 1
577 %1 = fcmp ueq double %a, %b
578 %2 = zext i1 %1 to i32
582 define i32 @ugt_f64(double %a, double %b) nounwind {
583 ; ALL-LABEL: ugt_f64:
585 ; 32-C-DAG: addiu $2, $zero, 1
586 ; 32-C-DAG: c.ole.d $f12, $f14
587 ; 32-C: movt $2, $zero, $fcc0
589 ; 64-C-DAG: addiu $2, $zero, 1
590 ; 64-C-DAG: c.ole.d $f12, $f13
591 ; 64-C: movt $2, $zero, $fcc0
593 ; 32-CMP-DAG: cmp.ult.d $[[T0:f[0-9]+]], $f14, $f12
594 ; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
595 ; 32-CMP-DAG: andi $2, $[[T1]], 1
597 ; 64-CMP-DAG: cmp.ult.d $[[T0:f[0-9]+]], $f13, $f12
598 ; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
599 ; 64-CMP-DAG: andi $2, $[[T1]], 1
601 %1 = fcmp ugt double %a, %b
602 %2 = zext i1 %1 to i32
606 define i32 @uge_f64(double %a, double %b) nounwind {
607 ; ALL-LABEL: uge_f64:
609 ; 32-C-DAG: addiu $2, $zero, 1
610 ; 32-C-DAG: c.olt.d $f12, $f14
611 ; 32-C: movt $2, $zero, $fcc0
613 ; 64-C-DAG: addiu $2, $zero, 1
614 ; 64-C-DAG: c.olt.d $f12, $f13
615 ; 64-C: movt $2, $zero, $fcc0
617 ; 32-CMP-DAG: cmp.ule.d $[[T0:f[0-9]+]], $f14, $f12
618 ; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
619 ; 32-CMP-DAG: andi $2, $[[T1]], 1
621 ; 64-CMP-DAG: cmp.ule.d $[[T0:f[0-9]+]], $f13, $f12
622 ; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
623 ; 64-CMP-DAG: andi $2, $[[T1]], 1
625 %1 = fcmp uge double %a, %b
626 %2 = zext i1 %1 to i32
630 define i32 @ult_f64(double %a, double %b) nounwind {
631 ; ALL-LABEL: ult_f64:
633 ; 32-C-DAG: addiu $2, $zero, 1
634 ; 32-C-DAG: c.ult.d $f12, $f14
635 ; 32-C: movf $2, $zero, $fcc0
637 ; 64-C-DAG: addiu $2, $zero, 1
638 ; 64-C-DAG: c.ult.d $f12, $f13
639 ; 64-C: movf $2, $zero, $fcc0
641 ; 32-CMP-DAG: cmp.ult.d $[[T0:f[0-9]+]], $f12, $f14
642 ; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
643 ; 32-CMP-DAG: andi $2, $[[T1]], 1
645 ; 64-CMP-DAG: cmp.ult.d $[[T0:f[0-9]+]], $f12, $f13
646 ; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
647 ; 64-CMP-DAG: andi $2, $[[T1]], 1
649 %1 = fcmp ult double %a, %b
650 %2 = zext i1 %1 to i32
654 define i32 @ule_f64(double %a, double %b) nounwind {
655 ; ALL-LABEL: ule_f64:
657 ; 32-C-DAG: addiu $2, $zero, 1
658 ; 32-C-DAG: c.ule.d $f12, $f14
659 ; 32-C: movf $2, $zero, $fcc0
661 ; 64-C-DAG: addiu $2, $zero, 1
662 ; 64-C-DAG: c.ule.d $f12, $f13
663 ; 64-C: movf $2, $zero, $fcc0
665 ; 32-CMP-DAG: cmp.ule.d $[[T0:f[0-9]+]], $f12, $f14
666 ; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
667 ; 32-CMP-DAG: andi $2, $[[T1]], 1
669 ; 64-CMP-DAG: cmp.ule.d $[[T0:f[0-9]+]], $f12, $f13
670 ; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
671 ; 64-CMP-DAG: andi $2, $[[T1]], 1
673 %1 = fcmp ule double %a, %b
674 %2 = zext i1 %1 to i32
678 define i32 @une_f64(double %a, double %b) nounwind {
679 ; ALL-LABEL: une_f64:
681 ; 32-C-DAG: addiu $2, $zero, 1
682 ; 32-C-DAG: c.eq.d $f12, $f14
683 ; 32-C: movt $2, $zero, $fcc0
685 ; 64-C-DAG: addiu $2, $zero, 1
686 ; 64-C-DAG: c.eq.d $f12, $f13
687 ; 64-C: movt $2, $zero, $fcc0
689 ; 32-CMP-DAG: cmp.eq.d $[[T0:f[0-9]+]], $f12, $f14
690 ; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
691 ; 32-CMP-DAG: not $[[T2:[0-9]+]], $[[T1]]
692 ; 32-CMP-DAG: andi $2, $[[T2]], 1
694 ; 64-CMP-DAG: cmp.eq.d $[[T0:f[0-9]+]], $f12, $f13
695 ; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
696 ; 64-CMP-DAG: not $[[T2:[0-9]+]], $[[T1]]
697 ; 64-CMP-DAG: andi $2, $[[T2]], 1
699 %1 = fcmp une double %a, %b
700 %2 = zext i1 %1 to i32
704 define i32 @uno_f64(double %a, double %b) nounwind {
705 ; ALL-LABEL: uno_f64:
707 ; 32-C-DAG: addiu $2, $zero, 1
708 ; 32-C-DAG: c.un.d $f12, $f14
709 ; 32-C: movf $2, $zero, $fcc0
711 ; 64-C-DAG: addiu $2, $zero, 1
712 ; 64-C-DAG: c.un.d $f12, $f13
713 ; 64-C: movf $2, $zero, $fcc0
715 ; 32-CMP-DAG: cmp.un.d $[[T0:f[0-9]+]], $f12, $f14
716 ; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
717 ; 32-CMP-DAG: andi $2, $[[T1]], 1
719 ; 64-CMP-DAG: cmp.un.d $[[T0:f[0-9]+]], $f12, $f13
720 ; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
721 ; 64-CMP-DAG: andi $2, $[[T1]], 1
723 %1 = fcmp uno double %a, %b
724 %2 = zext i1 %1 to i32
728 define i32 @true_f64(double %a, double %b) nounwind {
729 ; ALL-LABEL: true_f64:
730 ; ALL: addiu $2, $zero, 1
732 %1 = fcmp true double %a, %b
733 %2 = zext i1 %1 to i32
737 ; The optimizers sometimes produce setlt instead of setolt/setult.
738 define float @bug1_f32(float %angle, float %at) #0 {
740 ; ALL-LABEL: bug1_f32:
742 ; 32-C-DAG: add.s $[[T0:f[0-9]+]], $f14, $f12
743 ; 32-C-DAG: lwc1 $[[T1:f[0-9]+]], %lo($CPI32_0)(
744 ; 32-C-DAG: c.ole.s $[[T0]], $[[T1]]
747 ; 32-CMP-DAG: add.s $[[T0:f[0-9]+]], $f14, $f12
748 ; 32-CMP-DAG: lwc1 $[[T1:f[0-9]+]], %lo($CPI32_0)(
749 ; 32-CMP-DAG: cmp.le.s $[[T2:f[0-9]+]], $[[T0]], $[[T1]]
750 ; 32-CMP-DAG: mfc1 $[[T3:[0-9]+]], $[[T2]]
751 ; FIXME: This instruction is redundant.
752 ; 32-CMP-DAG: andi $[[T4:[0-9]+]], $[[T3]], 1
753 ; 32-CMP-DAG: bnez $[[T4]],
755 ; 64-C-DAG: add.s $[[T0:f[0-9]+]], $f13, $f12
756 ; 64-C-DAG: lwc1 $[[T1:f[0-9]+]], %got_ofst($CPI32_0)(
757 ; 64-C-DAG: c.ole.s $[[T0]], $[[T1]]
760 ; 64-CMP-DAG: add.s $[[T0:f[0-9]+]], $f13, $f12
761 ; 64-CMP-DAG: lwc1 $[[T1:f[0-9]+]], %got_ofst($CPI32_0)(
762 ; 64-CMP-DAG: cmp.le.s $[[T2:f[0-9]+]], $[[T0]], $[[T1]]
763 ; 64-CMP-DAG: mfc1 $[[T3:[0-9]+]], $[[T2]]
764 ; FIXME: This instruction is redundant.
765 ; 64-CMP-DAG: andi $[[T4:[0-9]+]], $[[T3]], 1
766 ; 64-CMP-DAG: bnez $[[T4]],
768 %add = fadd fast float %at, %angle
769 %cmp = fcmp ogt float %add, 1.000000e+00
770 br i1 %cmp, label %if.then, label %if.end
773 %sub = fadd fast float %add, -1.000000e+00
777 %theta.0 = phi float [ %sub, %if.then ], [ %add, %entry ]
781 ; The optimizers sometimes produce setlt instead of setolt/setult.
782 define double @bug1_f64(double %angle, double %at) #0 {
784 ; ALL-LABEL: bug1_f64:
786 ; 32-C-DAG: add.d $[[T0:f[0-9]+]], $f14, $f12
787 ; 32-C-DAG: ldc1 $[[T1:f[0-9]+]], %lo($CPI33_0)(
788 ; 32-C-DAG: c.ole.d $[[T0]], $[[T1]]
791 ; 32-CMP-DAG: add.d $[[T0:f[0-9]+]], $f14, $f12
792 ; 32-CMP-DAG: ldc1 $[[T1:f[0-9]+]], %lo($CPI33_0)(
793 ; 32-CMP-DAG: cmp.le.d $[[T2:f[0-9]+]], $[[T0]], $[[T1]]
794 ; 32-CMP-DAG: mfc1 $[[T3:[0-9]+]], $[[T2]]
795 ; FIXME: This instruction is redundant.
796 ; 32-CMP-DAG: andi $[[T4:[0-9]+]], $[[T3]], 1
797 ; 32-CMP-DAG: bnez $[[T4]],
799 ; 64-C-DAG: add.d $[[T0:f[0-9]+]], $f13, $f12
800 ; 64-C-DAG: ldc1 $[[T1:f[0-9]+]], %got_ofst($CPI33_0)(
801 ; 64-C-DAG: c.ole.d $[[T0]], $[[T1]]
804 ; 64-CMP-DAG: add.d $[[T0:f[0-9]+]], $f13, $f12
805 ; 64-CMP-DAG: ldc1 $[[T1:f[0-9]+]], %got_ofst($CPI33_0)(
806 ; 64-CMP-DAG: cmp.le.d $[[T2:f[0-9]+]], $[[T0]], $[[T1]]
807 ; 64-CMP-DAG: mfc1 $[[T3:[0-9]+]], $[[T2]]
808 ; FIXME: This instruction is redundant.
809 ; 64-CMP-DAG: andi $[[T4:[0-9]+]], $[[T3]], 1
810 ; 64-CMP-DAG: bnez $[[T4]],
812 %add = fadd fast double %at, %angle
813 %cmp = fcmp ogt double %add, 1.000000e+00
814 br i1 %cmp, label %if.then, label %if.end
817 %sub = fadd fast double %add, -1.000000e+00
821 %theta.0 = phi double [ %sub, %if.then ], [ %add, %entry ]
825 attributes #0 = { nounwind readnone "no-nans-fp-math"="true" }