1 ; RUN: llc < %s -march=mipsel -mcpu=mips32 | FileCheck %s -check-prefix=ALL -check-prefix=32-C
2 ; RUN: llc < %s -march=mipsel -mcpu=mips32r2 | FileCheck %s -check-prefix=ALL -check-prefix=32-C
3 ; RUN: llc < %s -march=mipsel -mcpu=mips32r6 | FileCheck %s -check-prefix=ALL -check-prefix=32-CMP
4 ; RUN: llc < %s -march=mips64el -mcpu=mips4 | FileCheck %s -check-prefix=ALL -check-prefix=64-C
5 ; RUN: llc < %s -march=mips64el -mcpu=mips64 | FileCheck %s -check-prefix=ALL -check-prefix=64-C
6 ; RUN: llc < %s -march=mips64el -mcpu=mips64r2 | FileCheck %s -check-prefix=ALL -check-prefix=64-C
7 ; RUN: llc < %s -march=mips64el -mcpu=mips64r6 | FileCheck %s -check-prefix=ALL -check-prefix=64-CMP
9 define i32 @false_f32(float %a, float %b) nounwind {
10 ; ALL-LABEL: false_f32:
11 ; ALL: addiu $2, $zero, 0
13 %1 = fcmp false float %a, %b
14 %2 = zext i1 %1 to i32
18 define i32 @oeq_f32(float %a, float %b) nounwind {
21 ; 32-C-DAG: addiu $[[T0:2]], $zero, 0
22 ; 32-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1
23 ; 32-C-DAG: c.eq.s $f12, $f14
24 ; 32-C-DAG: movt $[[T0]], $1, $fcc0
26 ; 64-C-DAG: addiu $[[T0:2]], $zero, 0
27 ; 64-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1
28 ; 64-C-DAG: c.eq.s $f12, $f13
29 ; 64-C-DAG: movt $[[T0]], $1, $fcc0
31 ; 32-CMP-DAG: cmp.eq.s $[[T0:f[0-9]+]], $f12, $f14
32 ; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
33 ; 32-CMP-DAG: andi $2, $[[T1]], 1
35 ; 64-CMP-DAG: cmp.eq.s $[[T0:f[0-9]+]], $f12, $f13
36 ; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
37 ; 64-CMP-DAG: andi $2, $[[T1]], 1
39 %1 = fcmp oeq float %a, %b
40 %2 = zext i1 %1 to i32
44 define i32 @ogt_f32(float %a, float %b) nounwind {
47 ; 32-C-DAG: addiu $[[T0:2]], $zero, 0
48 ; 32-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1
49 ; 32-C-DAG: c.ule.s $f12, $f14
50 ; 32-C-DAG: movf $[[T0]], $1, $fcc0
52 ; 64-C-DAG: addiu $[[T0:2]], $zero, 0
53 ; 64-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1
54 ; 64-C-DAG: c.ule.s $f12, $f13
55 ; 64-C-DAG: movf $[[T0]], $1, $fcc0
57 ; 32-CMP-DAG: cmp.lt.s $[[T0:f[0-9]+]], $f14, $f12
58 ; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
59 ; 32-CMP-DAG: andi $2, $[[T1]], 1
61 ; 64-CMP-DAG: cmp.lt.s $[[T0:f[0-9]+]], $f13, $f12
62 ; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
63 ; 64-CMP-DAG: andi $2, $[[T1]], 1
65 %1 = fcmp ogt float %a, %b
66 %2 = zext i1 %1 to i32
70 define i32 @oge_f32(float %a, float %b) nounwind {
73 ; 32-C-DAG: addiu $[[T0:2]], $zero, 0
74 ; 32-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1
75 ; 32-C-DAG: c.ult.s $f12, $f14
76 ; 32-C-DAG: movf $[[T0]], $1, $fcc0
78 ; 64-C-DAG: addiu $[[T0:2]], $zero, 0
79 ; 64-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1
80 ; 64-C-DAG: c.ult.s $f12, $f13
81 ; 64-C-DAG: movf $[[T0]], $1, $fcc0
83 ; 32-CMP-DAG: cmp.le.s $[[T0:f[0-9]+]], $f14, $f12
84 ; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
85 ; 32-CMP-DAG: andi $2, $[[T1]], 1
87 ; 64-CMP-DAG: cmp.le.s $[[T0:f[0-9]+]], $f13, $f12
88 ; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
89 ; 64-CMP-DAG: andi $2, $[[T1]], 1
91 %1 = fcmp oge float %a, %b
92 %2 = zext i1 %1 to i32
96 define i32 @olt_f32(float %a, float %b) nounwind {
99 ; 32-C-DAG: addiu $[[T0:2]], $zero, 0
100 ; 32-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1
101 ; 32-C-DAG: c.olt.s $f12, $f14
102 ; 32-C-DAG: movt $[[T0]], $1, $fcc0
104 ; 64-C-DAG: addiu $[[T0:2]], $zero, 0
105 ; 64-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1
106 ; 64-C-DAG: c.olt.s $f12, $f13
107 ; 64-C-DAG: movt $[[T0]], $1, $fcc0
109 ; 32-CMP-DAG: cmp.lt.s $[[T0:f[0-9]+]], $f12, $f14
110 ; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
111 ; 32-CMP-DAG: andi $2, $[[T1]], 1
113 ; 64-CMP-DAG: cmp.lt.s $[[T0:f[0-9]+]], $f12, $f13
114 ; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
115 ; 64-CMP-DAG: andi $2, $[[T1]], 1
117 %1 = fcmp olt float %a, %b
118 %2 = zext i1 %1 to i32
122 define i32 @ole_f32(float %a, float %b) nounwind {
123 ; ALL-LABEL: ole_f32:
125 ; 32-C-DAG: addiu $[[T0:2]], $zero, 0
126 ; 32-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1
127 ; 32-C-DAG: c.ole.s $f12, $f14
128 ; 32-C-DAG: movt $[[T0]], $1, $fcc0
130 ; 64-C-DAG: addiu $[[T0:2]], $zero, 0
131 ; 64-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1
132 ; 64-C-DAG: c.ole.s $f12, $f13
133 ; 64-C-DAG: movt $[[T0]], $1, $fcc0
135 ; 32-CMP-DAG: cmp.le.s $[[T0:f[0-9]+]], $f12, $f14
136 ; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
137 ; 32-CMP-DAG: andi $2, $[[T1]], 1
139 ; 64-CMP-DAG: cmp.le.s $[[T0:f[0-9]+]], $f12, $f13
140 ; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
141 ; 64-CMP-DAG: andi $2, $[[T1]], 1
143 %1 = fcmp ole float %a, %b
144 %2 = zext i1 %1 to i32
148 define i32 @one_f32(float %a, float %b) nounwind {
149 ; ALL-LABEL: one_f32:
151 ; 32-C-DAG: addiu $[[T0:2]], $zero, 0
152 ; 32-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1
153 ; 32-C-DAG: c.ueq.s $f12, $f14
154 ; 32-C-DAG: movf $[[T0]], $1, $fcc0
156 ; 64-C-DAG: addiu $[[T0:2]], $zero, 0
157 ; 64-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1
158 ; 64-C-DAG: c.ueq.s $f12, $f13
159 ; 64-C-DAG: movf $[[T0]], $1, $fcc0
161 ; 32-CMP-DAG: cmp.ueq.s $[[T0:f[0-9]+]], $f12, $f14
162 ; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
163 ; 32-CMP-DAG: not $[[T2:[0-9]+]], $[[T1]]
164 ; 32-CMP-DAG: andi $2, $[[T2]], 1
166 ; 64-CMP-DAG: cmp.ueq.s $[[T0:f[0-9]+]], $f12, $f13
167 ; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
168 ; 64-CMP-DAG: not $[[T2:[0-9]+]], $[[T1]]
169 ; 64-CMP-DAG: andi $2, $[[T2]], 1
171 %1 = fcmp one float %a, %b
172 %2 = zext i1 %1 to i32
176 define i32 @ord_f32(float %a, float %b) nounwind {
177 ; ALL-LABEL: ord_f32:
179 ; 32-C-DAG: addiu $[[T0:2]], $zero, 0
180 ; 32-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1
181 ; 32-C-DAG: c.un.s $f12, $f14
182 ; 32-C-DAG: movf $[[T0]], $1, $fcc0
184 ; 64-C-DAG: addiu $[[T0:2]], $zero, 0
185 ; 64-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1
186 ; 64-C-DAG: c.un.s $f12, $f13
187 ; 64-C-DAG: movf $[[T0]], $1, $fcc0
189 ; 32-CMP-DAG: cmp.un.s $[[T0:f[0-9]+]], $f12, $f14
190 ; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
191 ; 32-CMP-DAG: not $[[T2:[0-9]+]], $[[T1]]
192 ; 32-CMP-DAG: andi $2, $[[T2]], 1
194 ; 64-CMP-DAG: cmp.un.s $[[T0:f[0-9]+]], $f12, $f13
195 ; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
196 ; 64-CMP-DAG: not $[[T2:[0-9]+]], $[[T1]]
197 ; 64-CMP-DAG: andi $2, $[[T2]], 1
199 %1 = fcmp ord float %a, %b
200 %2 = zext i1 %1 to i32
204 define i32 @ueq_f32(float %a, float %b) nounwind {
205 ; ALL-LABEL: ueq_f32:
207 ; 32-C-DAG: addiu $[[T0:2]], $zero, 0
208 ; 32-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1
209 ; 32-C-DAG: c.ueq.s $f12, $f14
210 ; 32-C-DAG: movt $[[T0]], $1, $fcc0
212 ; 64-C-DAG: addiu $[[T0:2]], $zero, 0
213 ; 64-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1
214 ; 64-C-DAG: c.ueq.s $f12, $f13
215 ; 64-C-DAG: movt $[[T0]], $1, $fcc0
217 ; 32-CMP-DAG: cmp.ueq.s $[[T0:f[0-9]+]], $f12, $f14
218 ; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
219 ; 32-CMP-DAG: andi $2, $[[T1]], 1
221 ; 64-CMP-DAG: cmp.ueq.s $[[T0:f[0-9]+]], $f12, $f13
222 ; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
223 ; 64-CMP-DAG: andi $2, $[[T1]], 1
225 %1 = fcmp ueq float %a, %b
226 %2 = zext i1 %1 to i32
230 define i32 @ugt_f32(float %a, float %b) nounwind {
231 ; ALL-LABEL: ugt_f32:
233 ; 32-C-DAG: addiu $[[T0:2]], $zero, 0
234 ; 32-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1
235 ; 32-C-DAG: c.ole.s $f12, $f14
236 ; 32-C-DAG: movf $[[T0]], $1, $fcc0
238 ; 64-C-DAG: addiu $[[T0:2]], $zero, 0
239 ; 64-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1
240 ; 64-C-DAG: c.ole.s $f12, $f13
241 ; 64-C-DAG: movf $[[T0]], $1, $fcc0
243 ; 32-CMP-DAG: cmp.ult.s $[[T0:f[0-9]+]], $f14, $f12
244 ; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
245 ; 32-CMP-DAG: andi $2, $[[T1]], 1
247 ; 64-CMP-DAG: cmp.ult.s $[[T0:f[0-9]+]], $f13, $f12
248 ; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
249 ; 64-CMP-DAG: andi $2, $[[T1]], 1
251 %1 = fcmp ugt float %a, %b
252 %2 = zext i1 %1 to i32
256 define i32 @uge_f32(float %a, float %b) nounwind {
257 ; ALL-LABEL: uge_f32:
259 ; 32-C-DAG: addiu $[[T0:2]], $zero, 0
260 ; 32-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1
261 ; 32-C-DAG: c.olt.s $f12, $f14
262 ; 32-C-DAG: movf $[[T0]], $1, $fcc0
264 ; 64-C-DAG: addiu $[[T0:2]], $zero, 0
265 ; 64-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1
266 ; 64-C-DAG: c.olt.s $f12, $f13
267 ; 64-C-DAG: movf $[[T0]], $1, $fcc0
269 ; 32-CMP-DAG: cmp.ule.s $[[T0:f[0-9]+]], $f14, $f12
270 ; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
271 ; 32-CMP-DAG: andi $2, $[[T1]], 1
273 ; 64-CMP-DAG: cmp.ule.s $[[T0:f[0-9]+]], $f13, $f12
274 ; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
275 ; 64-CMP-DAG: andi $2, $[[T1]], 1
277 %1 = fcmp uge float %a, %b
278 %2 = zext i1 %1 to i32
282 define i32 @ult_f32(float %a, float %b) nounwind {
283 ; ALL-LABEL: ult_f32:
285 ; 32-C-DAG: addiu $[[T0:2]], $zero, 0
286 ; 32-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1
287 ; 32-C-DAG: c.ult.s $f12, $f14
288 ; 32-C-DAG: movt $[[T0]], $1, $fcc0
290 ; 64-C-DAG: addiu $[[T0:2]], $zero, 0
291 ; 64-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1
292 ; 64-C-DAG: c.ult.s $f12, $f13
293 ; 64-C-DAG: movt $[[T0]], $1, $fcc0
295 ; 32-CMP-DAG: cmp.ult.s $[[T0:f[0-9]+]], $f12, $f14
296 ; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
297 ; 32-CMP-DAG: andi $2, $[[T1]], 1
299 ; 64-CMP-DAG: cmp.ult.s $[[T0:f[0-9]+]], $f12, $f13
300 ; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
301 ; 64-CMP-DAG: andi $2, $[[T1]], 1
303 %1 = fcmp ult float %a, %b
304 %2 = zext i1 %1 to i32
308 define i32 @ule_f32(float %a, float %b) nounwind {
309 ; ALL-LABEL: ule_f32:
311 ; 32-C-DAG: addiu $[[T0:2]], $zero, 0
312 ; 32-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1
313 ; 32-C-DAG: c.ule.s $f12, $f14
314 ; 32-C-DAG: movt $[[T0]], $1, $fcc0
316 ; 64-C-DAG: addiu $[[T0:2]], $zero, 0
317 ; 64-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1
318 ; 64-C-DAG: c.ule.s $f12, $f13
319 ; 64-C-DAG: movt $[[T0]], $1, $fcc0
321 ; 32-CMP-DAG: cmp.ule.s $[[T0:f[0-9]+]], $f12, $f14
322 ; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
323 ; 32-CMP-DAG: andi $2, $[[T1]], 1
325 ; 64-CMP-DAG: cmp.ule.s $[[T0:f[0-9]+]], $f12, $f13
326 ; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
327 ; 64-CMP-DAG: andi $2, $[[T1]], 1
329 %1 = fcmp ule float %a, %b
330 %2 = zext i1 %1 to i32
334 define i32 @une_f32(float %a, float %b) nounwind {
335 ; ALL-LABEL: une_f32:
337 ; 32-C-DAG: addiu $[[T0:2]], $zero, 0
338 ; 32-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1
339 ; 32-C-DAG: c.eq.s $f12, $f14
340 ; 32-C-DAG: movf $[[T0]], $1, $fcc0
342 ; 64-C-DAG: addiu $[[T0:2]], $zero, 0
343 ; 64-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1
344 ; 64-C-DAG: c.eq.s $f12, $f13
345 ; 64-C-DAG: movf $[[T0]], $1, $fcc0
347 ; 32-CMP-DAG: cmp.eq.s $[[T0:f[0-9]+]], $f12, $f14
348 ; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
349 ; 32-CMP-DAG: not $[[T2:[0-9]+]], $[[T1]]
350 ; 32-CMP-DAG: andi $2, $[[T2]], 1
352 ; 64-CMP-DAG: cmp.eq.s $[[T0:f[0-9]+]], $f12, $f13
353 ; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
354 ; 64-CMP-DAG: not $[[T2:[0-9]+]], $[[T1]]
355 ; 64-CMP-DAG: andi $2, $[[T2]], 1
357 %1 = fcmp une float %a, %b
358 %2 = zext i1 %1 to i32
362 define i32 @uno_f32(float %a, float %b) nounwind {
363 ; ALL-LABEL: uno_f32:
365 ; 32-C-DAG: addiu $[[T0:2]], $zero, 0
366 ; 32-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1
367 ; 32-C-DAG: c.un.s $f12, $f14
368 ; 32-C-DAG: movt $[[T0]], $1, $fcc0
370 ; 64-C-DAG: addiu $[[T0:2]], $zero, 0
371 ; 64-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1
372 ; 64-C-DAG: c.un.s $f12, $f13
373 ; 64-C-DAG: movt $[[T0]], $1, $fcc0
375 ; 32-CMP-DAG: cmp.un.s $[[T0:f[0-9]+]], $f12, $f14
376 ; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
377 ; 32-CMP-DAG: andi $2, $[[T1]], 1
379 ; 64-CMP-DAG: cmp.un.s $[[T0:f[0-9]+]], $f12, $f13
380 ; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
381 ; 64-CMP-DAG: andi $2, $[[T1]], 1
383 %1 = fcmp uno float %a, %b
384 %2 = zext i1 %1 to i32
388 define i32 @true_f32(float %a, float %b) nounwind {
389 ; ALL-LABEL: true_f32:
390 ; ALL: addiu $2, $zero, 1
392 %1 = fcmp true float %a, %b
393 %2 = zext i1 %1 to i32
397 define i32 @false_f64(double %a, double %b) nounwind {
398 ; ALL-LABEL: false_f64:
399 ; ALL: addiu $2, $zero, 0
401 %1 = fcmp false double %a, %b
402 %2 = zext i1 %1 to i32
406 define i32 @oeq_f64(double %a, double %b) nounwind {
407 ; ALL-LABEL: oeq_f64:
409 ; 32-C-DAG: addiu $[[T0:2]], $zero, 0
410 ; 32-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1
411 ; 32-C-DAG: c.eq.d $f12, $f14
412 ; 32-C-DAG: movt $[[T0]], $1, $fcc0
414 ; 64-C-DAG: addiu $[[T0:2]], $zero, 0
415 ; 64-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1
416 ; 64-C-DAG: c.eq.d $f12, $f13
417 ; 64-C-DAG: movt $[[T0]], $1, $fcc0
419 ; 32-CMP-DAG: cmp.eq.d $[[T0:f[0-9]+]], $f12, $f14
420 ; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
421 ; 32-CMP-DAG: andi $2, $[[T1]], 1
423 ; 64-CMP-DAG: cmp.eq.d $[[T0:f[0-9]+]], $f12, $f13
424 ; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
425 ; 64-CMP-DAG: andi $2, $[[T1]], 1
427 %1 = fcmp oeq double %a, %b
428 %2 = zext i1 %1 to i32
432 define i32 @ogt_f64(double %a, double %b) nounwind {
433 ; ALL-LABEL: ogt_f64:
435 ; 32-C-DAG: addiu $[[T0:2]], $zero, 0
436 ; 32-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1
437 ; 32-C-DAG: c.ule.d $f12, $f14
438 ; 32-C-DAG: movf $[[T0]], $1, $fcc0
440 ; 64-C-DAG: addiu $[[T0:2]], $zero, 0
441 ; 64-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1
442 ; 64-C-DAG: c.ule.d $f12, $f13
443 ; 64-C-DAG: movf $[[T0]], $1, $fcc0
445 ; 32-CMP-DAG: cmp.lt.d $[[T0:f[0-9]+]], $f14, $f12
446 ; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
447 ; 32-CMP-DAG: andi $2, $[[T1]], 1
449 ; 64-CMP-DAG: cmp.lt.d $[[T0:f[0-9]+]], $f13, $f12
450 ; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
451 ; 64-CMP-DAG: andi $2, $[[T1]], 1
453 %1 = fcmp ogt double %a, %b
454 %2 = zext i1 %1 to i32
458 define i32 @oge_f64(double %a, double %b) nounwind {
459 ; ALL-LABEL: oge_f64:
461 ; 32-C-DAG: addiu $[[T0:2]], $zero, 0
462 ; 32-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1
463 ; 32-C-DAG: c.ult.d $f12, $f14
464 ; 32-C-DAG: movf $[[T0]], $1, $fcc0
466 ; 64-C-DAG: addiu $[[T0:2]], $zero, 0
467 ; 64-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1
468 ; 64-C-DAG: c.ult.d $f12, $f13
469 ; 64-C-DAG: movf $[[T0]], $1, $fcc0
471 ; 32-CMP-DAG: cmp.le.d $[[T0:f[0-9]+]], $f14, $f12
472 ; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
473 ; 32-CMP-DAG: andi $2, $[[T1]], 1
475 ; 64-CMP-DAG: cmp.le.d $[[T0:f[0-9]+]], $f13, $f12
476 ; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
477 ; 64-CMP-DAG: andi $2, $[[T1]], 1
479 %1 = fcmp oge double %a, %b
480 %2 = zext i1 %1 to i32
484 define i32 @olt_f64(double %a, double %b) nounwind {
485 ; ALL-LABEL: olt_f64:
487 ; 32-C-DAG: addiu $[[T0:2]], $zero, 0
488 ; 32-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1
489 ; 32-C-DAG: c.olt.d $f12, $f14
490 ; 32-C-DAG: movt $[[T0]], $1, $fcc0
492 ; 64-C-DAG: addiu $[[T0:2]], $zero, 0
493 ; 64-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1
494 ; 64-C-DAG: c.olt.d $f12, $f13
495 ; 64-C-DAG: movt $[[T0]], $1, $fcc0
497 ; 32-CMP-DAG: cmp.lt.d $[[T0:f[0-9]+]], $f12, $f14
498 ; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
499 ; 32-CMP-DAG: andi $2, $[[T1]], 1
501 ; 64-CMP-DAG: cmp.lt.d $[[T0:f[0-9]+]], $f12, $f13
502 ; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
503 ; 64-CMP-DAG: andi $2, $[[T1]], 1
505 %1 = fcmp olt double %a, %b
506 %2 = zext i1 %1 to i32
510 define i32 @ole_f64(double %a, double %b) nounwind {
511 ; ALL-LABEL: ole_f64:
513 ; 32-C-DAG: addiu $[[T0:2]], $zero, 0
514 ; 32-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1
515 ; 32-C-DAG: c.ole.d $f12, $f14
516 ; 32-C-DAG: movt $[[T0]], $1, $fcc0
518 ; 64-C-DAG: addiu $[[T0:2]], $zero, 0
519 ; 64-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1
520 ; 64-C-DAG: c.ole.d $f12, $f13
521 ; 64-C-DAG: movt $[[T0]], $1, $fcc0
523 ; 32-CMP-DAG: cmp.le.d $[[T0:f[0-9]+]], $f12, $f14
524 ; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
525 ; 32-CMP-DAG: andi $2, $[[T1]], 1
527 ; 64-CMP-DAG: cmp.le.d $[[T0:f[0-9]+]], $f12, $f13
528 ; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
529 ; 64-CMP-DAG: andi $2, $[[T1]], 1
531 %1 = fcmp ole double %a, %b
532 %2 = zext i1 %1 to i32
536 define i32 @one_f64(double %a, double %b) nounwind {
537 ; ALL-LABEL: one_f64:
539 ; 32-C-DAG: addiu $[[T0:2]], $zero, 0
540 ; 32-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1
541 ; 32-C-DAG: c.ueq.d $f12, $f14
542 ; 32-C-DAG: movf $[[T0]], $1, $fcc0
544 ; 64-C-DAG: addiu $[[T0:2]], $zero, 0
545 ; 64-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1
546 ; 64-C-DAG: c.ueq.d $f12, $f13
547 ; 64-C-DAG: movf $[[T0]], $1, $fcc0
549 ; 32-CMP-DAG: cmp.ueq.d $[[T0:f[0-9]+]], $f12, $f14
550 ; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
551 ; 32-CMP-DAG: not $[[T2:[0-9]+]], $[[T1]]
552 ; 32-CMP-DAG: andi $2, $[[T2]], 1
554 ; 64-CMP-DAG: cmp.ueq.d $[[T0:f[0-9]+]], $f12, $f13
555 ; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
556 ; 64-CMP-DAG: not $[[T2:[0-9]+]], $[[T1]]
557 ; 64-CMP-DAG: andi $2, $[[T2]], 1
559 %1 = fcmp one double %a, %b
560 %2 = zext i1 %1 to i32
564 define i32 @ord_f64(double %a, double %b) nounwind {
565 ; ALL-LABEL: ord_f64:
567 ; 32-C-DAG: addiu $[[T0:2]], $zero, 0
568 ; 32-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1
569 ; 32-C-DAG: c.un.d $f12, $f14
570 ; 32-C-DAG: movf $[[T0]], $1, $fcc0
572 ; 64-C-DAG: addiu $[[T0:2]], $zero, 0
573 ; 64-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1
574 ; 64-C-DAG: c.un.d $f12, $f13
575 ; 64-C-DAG: movf $[[T0]], $1, $fcc0
577 ; 32-CMP-DAG: cmp.un.d $[[T0:f[0-9]+]], $f12, $f14
578 ; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
579 ; 32-CMP-DAG: not $[[T2:[0-9]+]], $[[T1]]
580 ; 32-CMP-DAG: andi $2, $[[T2]], 1
582 ; 64-CMP-DAG: cmp.un.d $[[T0:f[0-9]+]], $f12, $f13
583 ; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
584 ; 64-CMP-DAG: not $[[T2:[0-9]+]], $[[T1]]
585 ; 64-CMP-DAG: andi $2, $[[T2]], 1
587 %1 = fcmp ord double %a, %b
588 %2 = zext i1 %1 to i32
592 define i32 @ueq_f64(double %a, double %b) nounwind {
593 ; ALL-LABEL: ueq_f64:
595 ; 32-C-DAG: addiu $[[T0:2]], $zero, 0
596 ; 32-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1
597 ; 32-C-DAG: c.ueq.d $f12, $f14
598 ; 32-C-DAG: movt $[[T0]], $1, $fcc0
600 ; 64-C-DAG: addiu $[[T0:2]], $zero, 0
601 ; 64-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1
602 ; 64-C-DAG: c.ueq.d $f12, $f13
603 ; 64-C-DAG: movt $[[T0]], $1, $fcc0
605 ; 32-CMP-DAG: cmp.ueq.d $[[T0:f[0-9]+]], $f12, $f14
606 ; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
607 ; 32-CMP-DAG: andi $2, $[[T1]], 1
609 ; 64-CMP-DAG: cmp.ueq.d $[[T0:f[0-9]+]], $f12, $f13
610 ; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
611 ; 64-CMP-DAG: andi $2, $[[T1]], 1
613 %1 = fcmp ueq double %a, %b
614 %2 = zext i1 %1 to i32
618 define i32 @ugt_f64(double %a, double %b) nounwind {
619 ; ALL-LABEL: ugt_f64:
621 ; 32-C-DAG: addiu $[[T0:2]], $zero, 0
622 ; 32-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1
623 ; 32-C-DAG: c.ole.d $f12, $f14
624 ; 32-C-DAG: movf $[[T0]], $1, $fcc0
626 ; 64-C-DAG: addiu $[[T0:2]], $zero, 0
627 ; 64-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1
628 ; 64-C-DAG: c.ole.d $f12, $f13
629 ; 64-C-DAG: movf $[[T0]], $1, $fcc0
631 ; 32-CMP-DAG: cmp.ult.d $[[T0:f[0-9]+]], $f14, $f12
632 ; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
633 ; 32-CMP-DAG: andi $2, $[[T1]], 1
635 ; 64-CMP-DAG: cmp.ult.d $[[T0:f[0-9]+]], $f13, $f12
636 ; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
637 ; 64-CMP-DAG: andi $2, $[[T1]], 1
639 %1 = fcmp ugt double %a, %b
640 %2 = zext i1 %1 to i32
644 define i32 @uge_f64(double %a, double %b) nounwind {
645 ; ALL-LABEL: uge_f64:
647 ; 32-C-DAG: addiu $[[T0:2]], $zero, 0
648 ; 32-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1
649 ; 32-C-DAG: c.olt.d $f12, $f14
650 ; 32-C-DAG: movf $[[T0]], $1, $fcc0
652 ; 64-C-DAG: addiu $[[T0:2]], $zero, 0
653 ; 64-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1
654 ; 64-C-DAG: c.olt.d $f12, $f13
655 ; 64-C-DAG: movf $[[T0]], $1, $fcc0
657 ; 32-CMP-DAG: cmp.ule.d $[[T0:f[0-9]+]], $f14, $f12
658 ; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
659 ; 32-CMP-DAG: andi $2, $[[T1]], 1
661 ; 64-CMP-DAG: cmp.ule.d $[[T0:f[0-9]+]], $f13, $f12
662 ; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
663 ; 64-CMP-DAG: andi $2, $[[T1]], 1
665 %1 = fcmp uge double %a, %b
666 %2 = zext i1 %1 to i32
670 define i32 @ult_f64(double %a, double %b) nounwind {
671 ; ALL-LABEL: ult_f64:
673 ; 32-C-DAG: addiu $[[T0:2]], $zero, 0
674 ; 32-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1
675 ; 32-C-DAG: c.ult.d $f12, $f14
676 ; 32-C-DAG: movt $[[T0]], $1, $fcc0
678 ; 64-C-DAG: addiu $[[T0:2]], $zero, 0
679 ; 64-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1
680 ; 64-C-DAG: c.ult.d $f12, $f13
681 ; 64-C-DAG: movt $[[T0]], $1, $fcc0
683 ; 32-CMP-DAG: cmp.ult.d $[[T0:f[0-9]+]], $f12, $f14
684 ; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
685 ; 32-CMP-DAG: andi $2, $[[T1]], 1
687 ; 64-CMP-DAG: cmp.ult.d $[[T0:f[0-9]+]], $f12, $f13
688 ; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
689 ; 64-CMP-DAG: andi $2, $[[T1]], 1
691 %1 = fcmp ult double %a, %b
692 %2 = zext i1 %1 to i32
696 define i32 @ule_f64(double %a, double %b) nounwind {
697 ; ALL-LABEL: ule_f64:
699 ; 32-C-DAG: addiu $[[T0:2]], $zero, 0
700 ; 32-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1
701 ; 32-C-DAG: c.ule.d $f12, $f14
702 ; 32-C-DAG: movt $[[T0]], $1, $fcc0
704 ; 64-C-DAG: addiu $[[T0:2]], $zero, 0
705 ; 64-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1
706 ; 64-C-DAG: c.ule.d $f12, $f13
707 ; 64-C-DAG: movt $[[T0]], $1, $fcc0
709 ; 32-CMP-DAG: cmp.ule.d $[[T0:f[0-9]+]], $f12, $f14
710 ; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
711 ; 32-CMP-DAG: andi $2, $[[T1]], 1
713 ; 64-CMP-DAG: cmp.ule.d $[[T0:f[0-9]+]], $f12, $f13
714 ; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
715 ; 64-CMP-DAG: andi $2, $[[T1]], 1
717 %1 = fcmp ule double %a, %b
718 %2 = zext i1 %1 to i32
722 define i32 @une_f64(double %a, double %b) nounwind {
723 ; ALL-LABEL: une_f64:
725 ; 32-C-DAG: addiu $[[T0:2]], $zero, 0
726 ; 32-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1
727 ; 32-C-DAG: c.eq.d $f12, $f14
728 ; 32-C-DAG: movf $[[T0]], $1, $fcc0
730 ; 64-C-DAG: addiu $[[T0:2]], $zero, 0
731 ; 64-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1
732 ; 64-C-DAG: c.eq.d $f12, $f13
733 ; 64-C-DAG: movf $[[T0]], $1, $fcc0
735 ; 32-CMP-DAG: cmp.eq.d $[[T0:f[0-9]+]], $f12, $f14
736 ; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
737 ; 32-CMP-DAG: not $[[T2:[0-9]+]], $[[T1]]
738 ; 32-CMP-DAG: andi $2, $[[T2]], 1
740 ; 64-CMP-DAG: cmp.eq.d $[[T0:f[0-9]+]], $f12, $f13
741 ; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
742 ; 64-CMP-DAG: not $[[T2:[0-9]+]], $[[T1]]
743 ; 64-CMP-DAG: andi $2, $[[T2]], 1
745 %1 = fcmp une double %a, %b
746 %2 = zext i1 %1 to i32
750 define i32 @uno_f64(double %a, double %b) nounwind {
751 ; ALL-LABEL: uno_f64:
753 ; 32-C-DAG: addiu $[[T0:2]], $zero, 0
754 ; 32-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1
755 ; 32-C-DAG: c.un.d $f12, $f14
756 ; 32-C-DAG: movt $[[T0]], $1, $fcc0
758 ; 64-C-DAG: addiu $[[T0:2]], $zero, 0
759 ; 64-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1
760 ; 64-C-DAG: c.un.d $f12, $f13
761 ; 64-C-DAG: movt $[[T0]], $1, $fcc0
763 ; 32-CMP-DAG: cmp.un.d $[[T0:f[0-9]+]], $f12, $f14
764 ; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
765 ; 32-CMP-DAG: andi $2, $[[T1]], 1
767 ; 64-CMP-DAG: cmp.un.d $[[T0:f[0-9]+]], $f12, $f13
768 ; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
769 ; 64-CMP-DAG: andi $2, $[[T1]], 1
771 %1 = fcmp uno double %a, %b
772 %2 = zext i1 %1 to i32
776 define i32 @true_f64(double %a, double %b) nounwind {
777 ; ALL-LABEL: true_f64:
778 ; ALL: addiu $2, $zero, 1
780 %1 = fcmp true double %a, %b
781 %2 = zext i1 %1 to i32