1 ; Positive test for inline register constraints
3 ; RUN: llc -no-integrated-as -march=mipsel < %s | \
4 ; RUN: FileCheck -check-prefix=ALL -check-prefix=LE32 -check-prefix=GAS %s
5 ; RUN: llc -no-integrated-as -march=mips < %s | \
6 ; RUN: FileCheck -check-prefix=ALL -check-prefix=BE32 -check-prefix=GAS %s
8 %union.u_tag = type { i64 }
9 %struct.anon = type { i32, i32 }
10 @uval = common global %union.u_tag zeroinitializer, align 8
13 define i32 @constraint_X() nounwind {
15 ; ALL-LABEL: constraint_X:
17 ; GAS: addiu ${{[0-9]+}}, ${{[0-9]+}}, 0xfffffffffffffffd
19 tail call i32 asm sideeffect "addiu $0, $1, ${2:X}", "=r,r,I"(i32 7, i32 -3) ;
24 define i32 @constraint_x() nounwind {
26 ; ALL-LABEL: constraint_x:
28 ; GAS: addiu ${{[0-9]+}}, ${{[0-9]+}}, 0xfffd
30 tail call i32 asm sideeffect "addiu $0, $1, ${2:x}", "=r,r,I"(i32 7, i32 -3) ;
35 define i32 @constraint_d() nounwind {
37 ; ALL-LABEL: constraint_d:
39 ; ALL: addiu ${{[0-9]+}}, ${{[0-9]+}}, -3
41 tail call i32 asm sideeffect "addiu $0, $1, ${2:d}", "=r,r,I"(i32 7, i32 -3) ;
46 define i32 @constraint_m() nounwind {
48 ; ALL-LABEL: constraint_m:
50 ; ALL: addiu ${{[0-9]+}}, ${{[0-9]+}}, -4
52 tail call i32 asm sideeffect "addiu $0, $1, ${2:m}", "=r,r,I"(i32 7, i32 -3) ;
57 define i32 @constraint_z() nounwind {
59 ; ALL-LABEL: constraint_z:
61 ; ALL: addiu ${{[0-9]+}}, ${{[0-9]+}}, -3
63 tail call i32 asm sideeffect "addiu $0, $1, ${2:z}", "=r,r,I"(i32 7, i32 -3) ;
67 ; GAS: addiu ${{[0-9]+}}, ${{[0-9]+}}, $0
69 tail call i32 asm sideeffect "addiu $0, $1, ${2:z}", "=r,r,I"(i32 7, i32 0) nounwind
71 ; z with non-zero and the "r"(register) and "J"(integer zero) constraints
73 ; ALL: mtc0 ${{[1-9][0-9]?}}, ${{[0-9]+}}
75 call void asm sideeffect "mtc0 ${0:z}, $$12", "Jr"(i32 7) nounwind
77 ; z with zero and the "r"(register) and "J"(integer zero) constraints
79 ; ALL: mtc0 $0, ${{[0-9]+}}
81 call void asm sideeffect "mtc0 ${0:z}, $$12", "Jr"(i32 0) nounwind
83 ; z with non-zero and just the "r"(register) constraint
85 ; ALL: mtc0 ${{[1-9][0-9]?}}, ${{[0-9]+}}
87 call void asm sideeffect "mtc0 ${0:z}, $$12", "r"(i32 7) nounwind
89 ; z with zero and just the "r"(register) constraint
90 ; FIXME: Check for $0, instead of other registers.
91 ; We should be using $0 directly in this case, not real registers.
92 ; When the materialization of 0 gets fixed, this test will fail.
94 ; ALL: mtc0 ${{[1-9][0-9]?}}, ${{[0-9]+}}
96 call void asm sideeffect "mtc0 ${0:z}, $$12", "r"(i32 0) nounwind
100 ; A long long in 32 bit mode (use to assert)
101 define i32 @constraint_longlong() nounwind {
103 ; ALL-LABEL: constraint_longlong:
105 ; ALL: addiu ${{[0-9]+}}, ${{[0-9]+}}, 3
107 tail call i64 asm sideeffect "addiu $0, $1, $2 \0A\09", "=r,r,X"(i64 1229801703532086340, i64 3) nounwind
111 ; In little endian the source reg will be 4 bytes into the long long
112 ; In big endian the source reg will also be 4 bytes into the long long
113 define i32 @constraint_D() nounwind {
115 ; ALL-LABEL: constraint_D:
116 ; ALL: lw ${{[0-9]+}}, %got(uval)(${{[0-9,a-z]+}})
117 ; ALL: lw $[[SECOND:[0-9]+]], 4(${{[0-9]+}})
118 ; ALL: lw $[[FIRST:[0-9]+]], 0(${{[0-9]+}})
120 ; LE32: or ${{[0-9]+}}, $[[SECOND]], ${{[0-9]+}}
121 ; BE32: or ${{[0-9]+}}, $[[SECOND]], ${{[0-9]+}}
123 %bosco = load i64, i64* getelementptr inbounds (%union.u_tag, %union.u_tag* @uval, i32 0, i32 0), align 8
124 %trunc1 = trunc i64 %bosco to i32
125 tail call i32 asm sideeffect "or $0, ${1:D}, $2", "=r,r,r"(i64 %bosco, i32 %trunc1) nounwind
129 ; In little endian the source reg will be 0 bytes into the long long
130 ; In big endian the source reg will be 4 bytes into the long long
131 define i32 @constraint_L() nounwind {
133 ; ALL-LABEL: constraint_L:
134 ; ALL: lw ${{[0-9]+}}, %got(uval)(${{[0-9,a-z]+}})
135 ; ALL: lw $[[SECOND:[0-9]+]], 4(${{[0-9]+}})
136 ; ALL: lw $[[FIRST:[0-9]+]], 0(${{[0-9]+}})
138 ; LE32: or ${{[0-9]+}}, $[[FIRST]], ${{[0-9]+}}
139 ; BE32: or ${{[0-9]+}}, $[[SECOND]], ${{[0-9]+}}
141 %bosco = load i64, i64* getelementptr inbounds (%union.u_tag, %union.u_tag* @uval, i32 0, i32 0), align 8
142 %trunc1 = trunc i64 %bosco to i32
143 tail call i32 asm sideeffect "or $0, ${1:L}, $2", "=r,r,r"(i64 %bosco, i32 %trunc1) nounwind
147 ; In little endian the source reg will be 4 bytes into the long long
148 ; In big endian the source reg will be 0 bytes into the long long
149 define i32 @constraint_M() nounwind {
151 ; ALL-LABEL: constraint_M:
152 ; ALL: lw ${{[0-9]+}}, %got(uval)(${{[0-9,a-z]+}})
153 ; ALL: lw $[[SECOND:[0-9]+]], 4(${{[0-9]+}})
154 ; ALL: lw $[[FIRST:[0-9]+]], 0(${{[0-9]+}})
156 ; LE32: or ${{[0-9]+}}, $[[SECOND]], ${{[0-9]+}}
157 ; BE32: or ${{[0-9]+}}, $[[FIRST]], ${{[0-9]+}}
159 %bosco = load i64, i64* getelementptr inbounds (%union.u_tag, %union.u_tag* @uval, i32 0, i32 0), align 8
160 %trunc1 = trunc i64 %bosco to i32
161 tail call i32 asm sideeffect "or $0, ${1:M}, $2", "=r,r,r"(i64 %bosco, i32 %trunc1) nounwind