1 ; RUN: llc < %s -march=mips -mcpu=mips2 | FileCheck %s \
2 ; RUN: -check-prefix=ALL -check-prefix=NOT-R2-R6 -check-prefix=GP32
3 ; RUN: llc < %s -march=mips -mcpu=mips32 | FileCheck %s \
4 ; RUN: -check-prefix=ALL -check-prefix=NOT-R2-R6 -check-prefix=GP32
5 ; RUN: llc < %s -march=mips -mcpu=mips32r2 | FileCheck %s \
6 ; RUN: -check-prefix=ALL -check-prefix=R2-R6 -check-prefix=GP32
7 ; RUN: llc < %s -march=mips -mcpu=mips32r6 | FileCheck %s \
8 ; RUN: -check-prefix=ALL -check-prefix=R2-R6 -check-prefix=GP32
9 ; RUN: llc < %s -march=mips64 -mcpu=mips3 | FileCheck %s \
10 ; RUN: -check-prefix=ALL -check-prefix=NOT-R2-R6 -check-prefix=GP64
11 ; RUN: llc < %s -march=mips64 -mcpu=mips4 | FileCheck %s \
12 ; RUN: -check-prefix=ALL -check-prefix=NOT-R2-R6 -check-prefix=GP64
13 ; RUN: llc < %s -march=mips64 -mcpu=mips64 | FileCheck %s \
14 ; RUN: -check-prefix=ALL -check-prefix=NOT-R2-R6 -check-prefix=GP64
15 ; RUN: llc < %s -march=mips64 -mcpu=mips64r2 | FileCheck %s \
16 ; RUN: -check-prefix=ALL -check-prefix=R2-R6 -check-prefix=GP64
17 ; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s \
18 ; RUN: -check-prefix=ALL -check-prefix=R2-R6 -check-prefix=GP64
20 define signext i1 @add_i1(i1 signext %a, i1 signext %b) {
24 ; ALL: addu $[[T0:[0-9]+]], $4, $5
25 ; ALL: sll $[[T0]], $[[T0]], 31
26 ; ALL: sra $2, $[[T0]], 31
32 define signext i8 @add_i8(i8 signext %a, i8 signext %b) {
36 ; NOT-R2-R6: addu $[[T0:[0-9]+]], $4, $5
37 ; NOT-R2-R6: sll $[[T0]], $[[T0]], 24
38 ; NOT-R2-R6: sra $2, $[[T0]], 24
40 ; R2-R6: addu $[[T0:[0-9]+]], $4, $5
41 ; R2-R6: seb $2, $[[T0:[0-9]+]]
47 define signext i16 @add_i16(i16 signext %a, i16 signext %b) {
51 ; NOT-R2-R6: addu $[[T0:[0-9]+]], $4, $5
52 ; NOT-R2-R6: sll $[[T0]], $[[T0]], 16
53 ; NOT-R2-R6: sra $2, $[[T0]], 16
55 ; R2-R6: addu $[[T0:[0-9]+]], $4, $5
56 ; R2-R6: seh $2, $[[T0:[0-9]+]]
62 define signext i32 @add_i32(i32 signext %a, i32 signext %b) {
66 ; ALL: addu $2, $4, $5
72 define signext i64 @add_i64(i64 signext %a, i64 signext %b) {
76 ; GP32: addu $3, $5, $7
77 ; GP32: sltu $[[T0:[0-9]+]], $3, $7
78 ; GP32: addu $[[T1:[0-9]+]], $[[T0]], $6
79 ; GP32: addu $2, $4, $[[T1]]
81 ; GP64: daddu $2, $4, $5
87 define signext i128 @add_i128(i128 signext %a, i128 signext %b) {
89 ; ALL-LABEL: add_i128:
91 ; GP32: lw $[[T0:[0-9]+]], 28($sp)
92 ; GP32: addu $[[T1:[0-9]+]], $7, $[[T0]]
93 ; GP32: sltu $[[T2:[0-9]+]], $[[T1]], $[[T0]]
94 ; GP32: lw $[[T3:[0-9]+]], 24($sp)
95 ; GP32: addu $[[T4:[0-9]+]], $[[T2]], $[[T3]]
96 ; GP32: addu $[[T5:[0-9]+]], $6, $[[T4]]
97 ; GP32: sltu $[[T6:[0-9]+]], $[[T5]], $[[T3]]
98 ; GP32: lw $[[T7:[0-9]+]], 20($sp)
99 ; GP32: addu $[[T8:[0-9]+]], $[[T6]], $[[T7]]
100 ; GP32: lw $[[T9:[0-9]+]], 16($sp)
101 ; GP32: addu $3, $5, $[[T8]]
102 ; GP32: sltu $[[T10:[0-9]+]], $3, $[[T7]]
103 ; GP32: addu $[[T11:[0-9]+]], $[[T10]], $[[T9]]
104 ; GP32: addu $2, $4, $[[T11]]
105 ; GP32: move $4, $[[T5]]
106 ; GP32: move $5, $[[T1]]
108 ; GP64: daddu $3, $5, $7
109 ; GP64: sltu $[[T0:[0-9]+]], $3, $7
110 ; GP64: daddu $[[T1:[0-9]+]], $[[T0]], $6
111 ; GP64: daddu $2, $4, $[[T1]]