1 ; Test all important variants of the 'ret' instruction.
3 ; For non-void returns it is necessary to have something to return so we also
4 ; test constant generation here.
6 ; We'll test pointer returns in a separate file since the relocation model
7 ; affects it and it's undesirable to repeat the non-pointer returns for each
10 ; RUN: llc -march=mips -mcpu=mips32 -asm-show-inst < %s | FileCheck %s -check-prefix=ALL -check-prefix=GPR32 -check-prefix=NO-MTHC1 -check-prefix=NOT-R6
11 ; RUN: llc -march=mips -mcpu=mips32r2 -asm-show-inst < %s | FileCheck %s -check-prefix=ALL -check-prefix=GPR32 -check-prefix=MTHC1 -check-prefix=NOT-R6
12 ; RUN: llc -march=mips -mcpu=mips32r6 -asm-show-inst < %s | FileCheck %s -check-prefix=ALL -check-prefix=GPR32 -check-prefix=MTHC1 -check-prefix=R6
13 ; RUN: llc -march=mips64 -mcpu=mips4 -asm-show-inst < %s | FileCheck %s -check-prefix=ALL -check-prefix=GPR64 -check-prefix=DMTC1 -check-prefix=NOT-R6
14 ; RUN: llc -march=mips64 -mcpu=mips64 -asm-show-inst < %s | FileCheck %s -check-prefix=ALL -check-prefix=GPR64 -check-prefix=DMTC1 -check-prefix=NOT-R6
15 ; RUN: llc -march=mips64 -mcpu=mips64r2 -asm-show-inst < %s | FileCheck %s -check-prefix=ALL -check-prefix=GPR64 -check-prefix=DMTC1 -check-prefix=NOT-R6
16 ; RUN: llc -march=mips64 -mcpu=mips64r6 -asm-show-inst < %s | FileCheck %s -check-prefix=ALL -check-prefix=GPR64 -check-prefix=DMTC1 -check-prefix=R6
18 define void @ret_void() {
19 ; ALL-LABEL: ret_void:
21 ; NOT-R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JR
22 ; R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JALR
29 ; ALL-DAG: addiu $2, $zero, 3
31 ; NOT-R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JR
32 ; R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JALR
37 define i16 @ret_i16_3() {
38 ; ALL-LABEL: ret_i16_3:
39 ; ALL-DAG: addiu $2, $zero, 3
41 ; NOT-R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JR
42 ; R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JALR
47 define i16 @ret_i16_256() {
48 ; ALL-LABEL: ret_i16_256:
49 ; ALL-DAG: addiu $2, $zero, 256
51 ; NOT-R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JR
52 ; R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JALR
57 define i16 @ret_i16_257() {
58 ; ALL-LABEL: ret_i16_257:
59 ; ALL-DAG: addiu $2, $zero, 257
61 ; NOT-R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JR
62 ; R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JALR
67 define i32 @ret_i32_257() {
68 ; ALL-LABEL: ret_i32_257:
69 ; ALL-DAG: addiu $2, $zero, 257
71 ; NOT-R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JR
72 ; R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JALR
77 define i32 @ret_i32_65536() {
78 ; ALL-LABEL: ret_i32_65536:
81 ; NOT-R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JR
82 ; R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JALR
87 define i32 @ret_i32_65537() {
88 ; ALL-LABEL: ret_i32_65537:
89 ; ALL: lui $[[T0:[0-9]+]], 1
90 ; ALL-DAG: ori $2, $[[T0]], 1
92 ; NOT-R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JR
93 ; R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JALR
98 define i64 @ret_i64_65537() {
99 ; ALL-LABEL: ret_i64_65537:
100 ; ALL: lui $[[T0:[0-9]+]], 1
102 ; GPR32-DAG: ori $3, $[[T0]], 1
103 ; GPR32-DAG: addiu $2, $zero, 0
105 ; GPR64-DAG: daddiu $2, $[[T0]], 1
107 ; NOT-R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JR
108 ; R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JALR
113 define i64 @ret_i64_281479271677952() {
114 ; ALL-LABEL: ret_i64_281479271677952:
115 ; ALL-DAG: lui $[[T0:[0-9]+]], 1
117 ; GPR32-DAG: ori $2, $[[T0]], 1
118 ; GPR32-DAG: addiu $3, $zero, 0
120 ; GPR64-DAG: daddiu $[[T1:[0-9]+]], $[[T0]], 1
121 ; GPR64-DAG: dsll $2, $[[T1]], 32
123 ; NOT-R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JR
124 ; R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JALR
126 ret i64 281479271677952
129 define i64 @ret_i64_281479271809026() {
130 ; ALL-LABEL: ret_i64_281479271809026:
131 ; GPR32-DAG: lui $[[T0:[0-9]+]], 1
132 ; GPR32-DAG: lui $[[T1:[0-9]+]], 2
133 ; GPR32-DAG: ori $2, $[[T0]], 1
134 ; GPR32-DAG: ori $3, $[[T1]], 2
136 ; GPR64-DAG: ori $[[T0:[0-9]+]], $zero, 32769
137 ; GPR64-DAG: dsll $[[T1:[0-9]+]], $[[T0]], 16
138 ; GPR64-DAG: daddiu $[[T0:[0-9]+]], $[[T0]], -32767
139 ; GPR64-DAG: dsll $[[T1:[0-9]+]], $[[T0]], 17
140 ; GPR64-DAG: daddiu $2, $[[T1]], 2
142 ; NOT-R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JR
143 ; R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JALR
145 ret i64 281479271809026
148 define float @ret_float_0x0() {
149 ; ALL-LABEL: ret_float_0x0:
151 ; NO-MTHC1-DAG: mtc1 $zero, $f0
153 ; MTHC1-DAG: mtc1 $zero, $f0
155 ; DMTC-DAG: dmtc1 $zero, $f0
157 ; NOT-R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JR
158 ; R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JALR
160 ret float 0x0000000000000000
163 define float @ret_float_0x3() {
164 ; ALL-LABEL: ret_float_0x3:
166 ; Use a constant pool
167 ; O32-DAG: lwc1 $f0, %lo($CPI
168 ; N64-DAG: lwc1 $f0, %got_ofst($CPI
170 ; NOT-R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JR
171 ; R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JALR
173 ; float constants are written as double constants
174 ret float 0x36b8000000000000
177 define double @ret_double_0x0() {
178 ; ALL-LABEL: ret_double_0x0:
180 ; NO-MTHC1-DAG: mtc1 $zero, $f0
181 ; NO-MTHC1-DAG: mtc1 $zero, $f1
183 ; MTHC1-DAG: mtc1 $zero, $f0
184 ; MTHC1-DAG: mthc1 $zero, $f0
186 ; DMTC-DAG: dmtc1 $zero, $f0
188 ; NOT-R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JR
189 ; R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JALR
191 ret double 0x0000000000000000
194 define double @ret_double_0x3() {
195 ; ALL-LABEL: ret_double_0x3:
197 ; Use a constant pool
198 ; O32-DAG: ldc1 $f0, %lo($CPI
199 ; N64-DAG: ldc1 $f0, %got_ofst($CPI
201 ; NOT-R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JR
202 ; R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JALR
204 ret double 0x0000000000000003