1 ; RUN: llc -march=mipsel < %s | FileCheck %s
2 ; RUN: llc -march=mipsel -force-mips-long-branch -O3 < %s \
3 ; RUN: | FileCheck %s -check-prefix=O32
4 ; RUN: llc -march=mips64el -mcpu=mips4 -mattr=n64 -force-mips-long-branch -O3 \
5 ; RUN: < %s | FileCheck %s -check-prefix=N64
6 ; RUN: llc -march=mips64el -mcpu=mips64 -mattr=n64 -force-mips-long-branch -O3 \
7 ; RUN: < %s | FileCheck %s -check-prefix=N64
8 ; RUN: llc -march=mipsel -mcpu=mips32r2 -mattr=micromips \
9 ; RUN: -force-mips-long-branch -O3 < %s | FileCheck %s -check-prefix=MICROMIPS
12 @x = external global i32
14 define void @test1(i32 %s) {
16 %cmp = icmp eq i32 %s, 0
17 br i1 %cmp, label %end, label %then
20 store i32 1, i32* @x, align 4
27 ; First check the normal version (without long branch). beqz jumps to return,
28 ; and fallthrough block stores 1 to global variable.
30 ; CHECK: lui $[[R0:[0-9]+]], %hi(_gp_disp)
31 ; CHECK: addiu $[[R0]], $[[R0]], %lo(_gp_disp)
32 ; CHECK: beqz $4, $[[BB0:BB[0-9_]+]]
33 ; CHECK: addu $[[GP:[0-9]+]], $[[R0]], $25
34 ; CHECK: lw $[[R1:[0-9]+]], %got(x)($[[GP]])
35 ; CHECK: addiu $[[R2:[0-9]+]], $zero, 1
36 ; CHECK: sw $[[R2]], 0($[[R1]])
42 ; Check the MIPS32 version. Check that branch logic is inverted, so that the
43 ; target of the new branch (bnez) is the fallthrough block of the original
44 ; branch. Check that fallthrough block of the new branch contains long branch
45 ; expansion which at the end indirectly jumps to the target of the original
48 ; O32: lui $[[R0:[0-9]+]], %hi(_gp_disp)
49 ; O32: addiu $[[R0]], $[[R0]], %lo(_gp_disp)
50 ; O32: bnez $4, $[[BB0:BB[0-9_]+]]
51 ; O32: addu $[[GP:[0-9]+]], $[[R0]], $25
53 ; Check for long branch expansion:
54 ; O32: addiu $sp, $sp, -8
55 ; O32-NEXT: sw $ra, 0($sp)
56 ; O32-NEXT: lui $1, %hi(($[[BB2:BB[0-9_]+]])-($[[BB1:BB[0-9_]+]]))
57 ; O32-NEXT: bal $[[BB1]]
58 ; O32-NEXT: addiu $1, $1, %lo(($[[BB2]])-($[[BB1]]))
60 ; O32-NEXT: addu $1, $ra, $1
61 ; O32-NEXT: lw $ra, 0($sp)
63 ; O32-NEXT: addiu $sp, $sp, 8
66 ; O32: lw $[[R1:[0-9]+]], %got(x)($[[GP]])
67 ; O32: addiu $[[R2:[0-9]+]], $zero, 1
68 ; O32: sw $[[R2]], 0($[[R1]])
74 ; Check the MIPS64 version.
76 ; N64: lui $[[R0:[0-9]+]], %hi(%neg(%gp_rel(test1)))
77 ; N64: bnez $4, $[[BB0:BB[0-9_]+]]
78 ; N64: daddu $[[R1:[0-9]+]], $[[R0]], $25
80 ; Check for long branch expansion:
81 ; N64: daddiu $sp, $sp, -16
82 ; N64-NEXT: sd $ra, 0($sp)
83 ; N64-NEXT: lui $1, %highest(($[[BB2:BB[0-9_]+]])-($[[BB1:BB[0-9_]+]]))
84 ; N64-NEXT: daddiu $1, $1, %higher(($[[BB2]])-($[[BB1]]))
85 ; N64-NEXT: dsll $1, $1, 16
86 ; N64-NEXT: daddiu $1, $1, %hi(($[[BB2]])-($[[BB1]]))
87 ; N64-NEXT: dsll $1, $1, 16
88 ; N64-NEXT: bal $[[BB1]]
89 ; N64-NEXT: daddiu $1, $1, %lo(($[[BB2]])-($[[BB1]]))
91 ; N64-NEXT: daddu $1, $ra, $1
92 ; N64-NEXT: ld $ra, 0($sp)
94 ; N64-NEXT: daddiu $sp, $sp, 16
97 ; N64: daddiu $[[GP:[0-9]+]], $[[R1]], %lo(%neg(%gp_rel(test1)))
98 ; N64: ld $[[R2:[0-9]+]], %got_disp(x)($[[GP]])
99 ; N64: addiu $[[R3:[0-9]+]], $zero, 1
100 ; N64: sw $[[R3]], 0($[[R2]])
106 ; Check the microMIPS version.
108 ; MICROMIPS: lui $[[R0:[0-9]+]], %hi(_gp_disp)
109 ; MICROMIPS: addiu $[[R0]], $[[R0]], %lo(_gp_disp)
110 ; MICROMIPS: bnez $4, $[[BB0:BB[0-9_]+]]
111 ; MICROMIPS: addu $[[GP:[0-9]+]], $[[R0]], $25
113 ; Check for long branch expansion:
114 ; MICROMIPS: addiu $sp, $sp, -8
115 ; MICROMIPS-NEXT: sw $ra, 0($sp)
116 ; MICROMIPS-NEXT: lui $1, %hi(($[[BB2:BB[0-9_]+]])-($[[BB1:BB[0-9_]+]]))
117 ; MICROMIPS-NEXT: bal $[[BB1]]
118 ; MICROMIPS-NEXT: addiu $1, $1, %lo(($[[BB2]])-($[[BB1]]))
119 ; MICROMIPS-NEXT: $[[BB1]]:
120 ; MICROMIPS-NEXT: addu $1, $ra, $1
121 ; MICROMIPS-NEXT: lw $ra, 0($sp)
122 ; MICROMIPS-NEXT: jr $1
123 ; MICROMIPS-NEXT: addiu $sp, $sp, 8
125 ; MICROMIPS: $[[BB0]]:
126 ; MICROMIPS: lw $[[R1:[0-9]+]], %got(x)($[[GP]])
127 ; MICROMIPS: addiu $[[R2:[0-9]+]], $zero, 1
128 ; MICROMIPS: sw $[[R2]], 0($[[R1]])
129 ; MICROMIPS: $[[BB2]]: