1 ; Test the MSA intrinsics that are encoded with the 2R instruction format and
2 ; convert scalars to vectors.
4 ; RUN: llc -march=mips -mattr=+msa < %s | FileCheck %s
6 @llvm_mips_fill_b_ARG1 = global i32 23, align 16
7 @llvm_mips_fill_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16
9 define void @llvm_mips_fill_b_test() nounwind {
11 %0 = load i32* @llvm_mips_fill_b_ARG1
12 %1 = tail call <16 x i8> @llvm.mips.fill.b(i32 %0)
13 store <16 x i8> %1, <16 x i8>* @llvm_mips_fill_b_RES
17 declare <16 x i8> @llvm.mips.fill.b(i32) nounwind
19 ; CHECK: llvm_mips_fill_b_test:
23 ; CHECK: .size llvm_mips_fill_b_test
25 @llvm_mips_fill_h_ARG1 = global i32 23, align 16
26 @llvm_mips_fill_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16
28 define void @llvm_mips_fill_h_test() nounwind {
30 %0 = load i32* @llvm_mips_fill_h_ARG1
31 %1 = tail call <8 x i16> @llvm.mips.fill.h(i32 %0)
32 store <8 x i16> %1, <8 x i16>* @llvm_mips_fill_h_RES
36 declare <8 x i16> @llvm.mips.fill.h(i32) nounwind
38 ; CHECK: llvm_mips_fill_h_test:
42 ; CHECK: .size llvm_mips_fill_h_test
44 @llvm_mips_fill_w_ARG1 = global i32 23, align 16
45 @llvm_mips_fill_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16
47 define void @llvm_mips_fill_w_test() nounwind {
49 %0 = load i32* @llvm_mips_fill_w_ARG1
50 %1 = tail call <4 x i32> @llvm.mips.fill.w(i32 %0)
51 store <4 x i32> %1, <4 x i32>* @llvm_mips_fill_w_RES
55 declare <4 x i32> @llvm.mips.fill.w(i32) nounwind
57 ; CHECK: llvm_mips_fill_w_test:
61 ; CHECK: .size llvm_mips_fill_w_test