1 ; Test the MSA fixed-point to floating point conversion intrinsics that are
2 ; encoded with the 2RF instruction format.
4 ; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s
6 @llvm_mips_ffql_w_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16
7 @llvm_mips_ffql_w_RES = global <4 x float> <float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00>, align 16
9 define void @llvm_mips_ffql_w_test() nounwind {
11 %0 = load <8 x i16>* @llvm_mips_ffql_w_ARG1
12 %1 = tail call <4 x float> @llvm.mips.ffql.w(<8 x i16> %0)
13 store <4 x float> %1, <4 x float>* @llvm_mips_ffql_w_RES
17 declare <4 x float> @llvm.mips.ffql.w(<8 x i16>) nounwind
19 ; CHECK: llvm_mips_ffql_w_test:
23 ; CHECK: .size llvm_mips_ffql_w_test
25 @llvm_mips_ffql_d_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16
26 @llvm_mips_ffql_d_RES = global <2 x double> <double 0.000000e+00, double 0.000000e+00>, align 16
28 define void @llvm_mips_ffql_d_test() nounwind {
30 %0 = load <4 x i32>* @llvm_mips_ffql_d_ARG1
31 %1 = tail call <2 x double> @llvm.mips.ffql.d(<4 x i32> %0)
32 store <2 x double> %1, <2 x double>* @llvm_mips_ffql_d_RES
36 declare <2 x double> @llvm.mips.ffql.d(<4 x i32>) nounwind
38 ; CHECK: llvm_mips_ffql_d_test:
42 ; CHECK: .size llvm_mips_ffql_d_test
44 @llvm_mips_ffqr_w_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16
45 @llvm_mips_ffqr_w_RES = global <4 x float> <float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00>, align 16
47 define void @llvm_mips_ffqr_w_test() nounwind {
49 %0 = load <8 x i16>* @llvm_mips_ffqr_w_ARG1
50 %1 = tail call <4 x float> @llvm.mips.ffqr.w(<8 x i16> %0)
51 store <4 x float> %1, <4 x float>* @llvm_mips_ffqr_w_RES
55 declare <4 x float> @llvm.mips.ffqr.w(<8 x i16>) nounwind
57 ; CHECK: llvm_mips_ffqr_w_test:
61 ; CHECK: .size llvm_mips_ffqr_w_test
63 @llvm_mips_ffqr_d_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16
64 @llvm_mips_ffqr_d_RES = global <2 x double> <double 0.000000e+00, double 0.000000e+00>, align 16
66 define void @llvm_mips_ffqr_d_test() nounwind {
68 %0 = load <4 x i32>* @llvm_mips_ffqr_d_ARG1
69 %1 = tail call <2 x double> @llvm.mips.ffqr.d(<4 x i32> %0)
70 store <2 x double> %1, <2 x double>* @llvm_mips_ffqr_d_RES
74 declare <2 x double> @llvm.mips.ffqr.d(<4 x i32>) nounwind
76 ; CHECK: llvm_mips_ffqr_d_test:
80 ; CHECK: .size llvm_mips_ffqr_d_test