1 ; Test the MSA intrinsics that are encoded with the 3R instruction format.
2 ; There are lots of these so this covers those beginning with 'i'
4 ; RUN: llc -march=mips -mattr=+msa < %s | FileCheck %s
6 @llvm_mips_ilvev_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
7 @llvm_mips_ilvev_b_ARG2 = global <16 x i8> <i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23, i8 24, i8 25, i8 26, i8 27, i8 28, i8 29, i8 30, i8 31>, align 16
8 @llvm_mips_ilvev_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16
10 define void @llvm_mips_ilvev_b_test() nounwind {
12 %0 = load <16 x i8>* @llvm_mips_ilvev_b_ARG1
13 %1 = load <16 x i8>* @llvm_mips_ilvev_b_ARG2
14 %2 = tail call <16 x i8> @llvm.mips.ilvev.b(<16 x i8> %0, <16 x i8> %1)
15 store <16 x i8> %2, <16 x i8>* @llvm_mips_ilvev_b_RES
19 declare <16 x i8> @llvm.mips.ilvev.b(<16 x i8>, <16 x i8>) nounwind
21 ; CHECK: llvm_mips_ilvev_b_test:
26 ; CHECK: .size llvm_mips_ilvev_b_test
28 @llvm_mips_ilvev_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16
29 @llvm_mips_ilvev_h_ARG2 = global <8 x i16> <i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15>, align 16
30 @llvm_mips_ilvev_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16
32 define void @llvm_mips_ilvev_h_test() nounwind {
34 %0 = load <8 x i16>* @llvm_mips_ilvev_h_ARG1
35 %1 = load <8 x i16>* @llvm_mips_ilvev_h_ARG2
36 %2 = tail call <8 x i16> @llvm.mips.ilvev.h(<8 x i16> %0, <8 x i16> %1)
37 store <8 x i16> %2, <8 x i16>* @llvm_mips_ilvev_h_RES
41 declare <8 x i16> @llvm.mips.ilvev.h(<8 x i16>, <8 x i16>) nounwind
43 ; CHECK: llvm_mips_ilvev_h_test:
48 ; CHECK: .size llvm_mips_ilvev_h_test
50 @llvm_mips_ilvev_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16
51 @llvm_mips_ilvev_w_ARG2 = global <4 x i32> <i32 4, i32 5, i32 6, i32 7>, align 16
52 @llvm_mips_ilvev_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16
54 define void @llvm_mips_ilvev_w_test() nounwind {
56 %0 = load <4 x i32>* @llvm_mips_ilvev_w_ARG1
57 %1 = load <4 x i32>* @llvm_mips_ilvev_w_ARG2
58 %2 = tail call <4 x i32> @llvm.mips.ilvev.w(<4 x i32> %0, <4 x i32> %1)
59 store <4 x i32> %2, <4 x i32>* @llvm_mips_ilvev_w_RES
63 declare <4 x i32> @llvm.mips.ilvev.w(<4 x i32>, <4 x i32>) nounwind
65 ; CHECK: llvm_mips_ilvev_w_test:
70 ; CHECK: .size llvm_mips_ilvev_w_test
72 @llvm_mips_ilvev_d_ARG1 = global <2 x i64> <i64 0, i64 1>, align 16
73 @llvm_mips_ilvev_d_ARG2 = global <2 x i64> <i64 2, i64 3>, align 16
74 @llvm_mips_ilvev_d_RES = global <2 x i64> <i64 0, i64 0>, align 16
76 define void @llvm_mips_ilvev_d_test() nounwind {
78 %0 = load <2 x i64>* @llvm_mips_ilvev_d_ARG1
79 %1 = load <2 x i64>* @llvm_mips_ilvev_d_ARG2
80 %2 = tail call <2 x i64> @llvm.mips.ilvev.d(<2 x i64> %0, <2 x i64> %1)
81 store <2 x i64> %2, <2 x i64>* @llvm_mips_ilvev_d_RES
85 declare <2 x i64> @llvm.mips.ilvev.d(<2 x i64>, <2 x i64>) nounwind
87 ; CHECK: llvm_mips_ilvev_d_test:
92 ; CHECK: .size llvm_mips_ilvev_d_test
94 @llvm_mips_ilvl_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
95 @llvm_mips_ilvl_b_ARG2 = global <16 x i8> <i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23, i8 24, i8 25, i8 26, i8 27, i8 28, i8 29, i8 30, i8 31>, align 16
96 @llvm_mips_ilvl_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16
98 define void @llvm_mips_ilvl_b_test() nounwind {
100 %0 = load <16 x i8>* @llvm_mips_ilvl_b_ARG1
101 %1 = load <16 x i8>* @llvm_mips_ilvl_b_ARG2
102 %2 = tail call <16 x i8> @llvm.mips.ilvl.b(<16 x i8> %0, <16 x i8> %1)
103 store <16 x i8> %2, <16 x i8>* @llvm_mips_ilvl_b_RES
107 declare <16 x i8> @llvm.mips.ilvl.b(<16 x i8>, <16 x i8>) nounwind
109 ; CHECK: llvm_mips_ilvl_b_test:
114 ; CHECK: .size llvm_mips_ilvl_b_test
116 @llvm_mips_ilvl_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16
117 @llvm_mips_ilvl_h_ARG2 = global <8 x i16> <i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15>, align 16
118 @llvm_mips_ilvl_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16
120 define void @llvm_mips_ilvl_h_test() nounwind {
122 %0 = load <8 x i16>* @llvm_mips_ilvl_h_ARG1
123 %1 = load <8 x i16>* @llvm_mips_ilvl_h_ARG2
124 %2 = tail call <8 x i16> @llvm.mips.ilvl.h(<8 x i16> %0, <8 x i16> %1)
125 store <8 x i16> %2, <8 x i16>* @llvm_mips_ilvl_h_RES
129 declare <8 x i16> @llvm.mips.ilvl.h(<8 x i16>, <8 x i16>) nounwind
131 ; CHECK: llvm_mips_ilvl_h_test:
136 ; CHECK: .size llvm_mips_ilvl_h_test
138 @llvm_mips_ilvl_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16
139 @llvm_mips_ilvl_w_ARG2 = global <4 x i32> <i32 4, i32 5, i32 6, i32 7>, align 16
140 @llvm_mips_ilvl_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16
142 define void @llvm_mips_ilvl_w_test() nounwind {
144 %0 = load <4 x i32>* @llvm_mips_ilvl_w_ARG1
145 %1 = load <4 x i32>* @llvm_mips_ilvl_w_ARG2
146 %2 = tail call <4 x i32> @llvm.mips.ilvl.w(<4 x i32> %0, <4 x i32> %1)
147 store <4 x i32> %2, <4 x i32>* @llvm_mips_ilvl_w_RES
151 declare <4 x i32> @llvm.mips.ilvl.w(<4 x i32>, <4 x i32>) nounwind
153 ; CHECK: llvm_mips_ilvl_w_test:
158 ; CHECK: .size llvm_mips_ilvl_w_test
160 @llvm_mips_ilvl_d_ARG1 = global <2 x i64> <i64 0, i64 1>, align 16
161 @llvm_mips_ilvl_d_ARG2 = global <2 x i64> <i64 2, i64 3>, align 16
162 @llvm_mips_ilvl_d_RES = global <2 x i64> <i64 0, i64 0>, align 16
164 define void @llvm_mips_ilvl_d_test() nounwind {
166 %0 = load <2 x i64>* @llvm_mips_ilvl_d_ARG1
167 %1 = load <2 x i64>* @llvm_mips_ilvl_d_ARG2
168 %2 = tail call <2 x i64> @llvm.mips.ilvl.d(<2 x i64> %0, <2 x i64> %1)
169 store <2 x i64> %2, <2 x i64>* @llvm_mips_ilvl_d_RES
173 declare <2 x i64> @llvm.mips.ilvl.d(<2 x i64>, <2 x i64>) nounwind
175 ; CHECK: llvm_mips_ilvl_d_test:
180 ; CHECK: .size llvm_mips_ilvl_d_test
182 @llvm_mips_ilvod_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
183 @llvm_mips_ilvod_b_ARG2 = global <16 x i8> <i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23, i8 24, i8 25, i8 26, i8 27, i8 28, i8 29, i8 30, i8 31>, align 16
184 @llvm_mips_ilvod_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16
186 define void @llvm_mips_ilvod_b_test() nounwind {
188 %0 = load <16 x i8>* @llvm_mips_ilvod_b_ARG1
189 %1 = load <16 x i8>* @llvm_mips_ilvod_b_ARG2
190 %2 = tail call <16 x i8> @llvm.mips.ilvod.b(<16 x i8> %0, <16 x i8> %1)
191 store <16 x i8> %2, <16 x i8>* @llvm_mips_ilvod_b_RES
195 declare <16 x i8> @llvm.mips.ilvod.b(<16 x i8>, <16 x i8>) nounwind
197 ; CHECK: llvm_mips_ilvod_b_test:
202 ; CHECK: .size llvm_mips_ilvod_b_test
204 @llvm_mips_ilvod_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16
205 @llvm_mips_ilvod_h_ARG2 = global <8 x i16> <i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15>, align 16
206 @llvm_mips_ilvod_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16
208 define void @llvm_mips_ilvod_h_test() nounwind {
210 %0 = load <8 x i16>* @llvm_mips_ilvod_h_ARG1
211 %1 = load <8 x i16>* @llvm_mips_ilvod_h_ARG2
212 %2 = tail call <8 x i16> @llvm.mips.ilvod.h(<8 x i16> %0, <8 x i16> %1)
213 store <8 x i16> %2, <8 x i16>* @llvm_mips_ilvod_h_RES
217 declare <8 x i16> @llvm.mips.ilvod.h(<8 x i16>, <8 x i16>) nounwind
219 ; CHECK: llvm_mips_ilvod_h_test:
224 ; CHECK: .size llvm_mips_ilvod_h_test
226 @llvm_mips_ilvod_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16
227 @llvm_mips_ilvod_w_ARG2 = global <4 x i32> <i32 4, i32 5, i32 6, i32 7>, align 16
228 @llvm_mips_ilvod_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16
230 define void @llvm_mips_ilvod_w_test() nounwind {
232 %0 = load <4 x i32>* @llvm_mips_ilvod_w_ARG1
233 %1 = load <4 x i32>* @llvm_mips_ilvod_w_ARG2
234 %2 = tail call <4 x i32> @llvm.mips.ilvod.w(<4 x i32> %0, <4 x i32> %1)
235 store <4 x i32> %2, <4 x i32>* @llvm_mips_ilvod_w_RES
239 declare <4 x i32> @llvm.mips.ilvod.w(<4 x i32>, <4 x i32>) nounwind
241 ; CHECK: llvm_mips_ilvod_w_test:
246 ; CHECK: .size llvm_mips_ilvod_w_test
248 @llvm_mips_ilvod_d_ARG1 = global <2 x i64> <i64 0, i64 1>, align 16
249 @llvm_mips_ilvod_d_ARG2 = global <2 x i64> <i64 2, i64 3>, align 16
250 @llvm_mips_ilvod_d_RES = global <2 x i64> <i64 0, i64 0>, align 16
252 define void @llvm_mips_ilvod_d_test() nounwind {
254 %0 = load <2 x i64>* @llvm_mips_ilvod_d_ARG1
255 %1 = load <2 x i64>* @llvm_mips_ilvod_d_ARG2
256 %2 = tail call <2 x i64> @llvm.mips.ilvod.d(<2 x i64> %0, <2 x i64> %1)
257 store <2 x i64> %2, <2 x i64>* @llvm_mips_ilvod_d_RES
261 declare <2 x i64> @llvm.mips.ilvod.d(<2 x i64>, <2 x i64>) nounwind
263 ; CHECK: llvm_mips_ilvod_d_test:
268 ; CHECK: .size llvm_mips_ilvod_d_test
270 @llvm_mips_ilvr_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
271 @llvm_mips_ilvr_b_ARG2 = global <16 x i8> <i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23, i8 24, i8 25, i8 26, i8 27, i8 28, i8 29, i8 30, i8 31>, align 16
272 @llvm_mips_ilvr_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16
274 define void @llvm_mips_ilvr_b_test() nounwind {
276 %0 = load <16 x i8>* @llvm_mips_ilvr_b_ARG1
277 %1 = load <16 x i8>* @llvm_mips_ilvr_b_ARG2
278 %2 = tail call <16 x i8> @llvm.mips.ilvr.b(<16 x i8> %0, <16 x i8> %1)
279 store <16 x i8> %2, <16 x i8>* @llvm_mips_ilvr_b_RES
283 declare <16 x i8> @llvm.mips.ilvr.b(<16 x i8>, <16 x i8>) nounwind
285 ; CHECK: llvm_mips_ilvr_b_test:
290 ; CHECK: .size llvm_mips_ilvr_b_test
292 @llvm_mips_ilvr_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16
293 @llvm_mips_ilvr_h_ARG2 = global <8 x i16> <i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15>, align 16
294 @llvm_mips_ilvr_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16
296 define void @llvm_mips_ilvr_h_test() nounwind {
298 %0 = load <8 x i16>* @llvm_mips_ilvr_h_ARG1
299 %1 = load <8 x i16>* @llvm_mips_ilvr_h_ARG2
300 %2 = tail call <8 x i16> @llvm.mips.ilvr.h(<8 x i16> %0, <8 x i16> %1)
301 store <8 x i16> %2, <8 x i16>* @llvm_mips_ilvr_h_RES
305 declare <8 x i16> @llvm.mips.ilvr.h(<8 x i16>, <8 x i16>) nounwind
307 ; CHECK: llvm_mips_ilvr_h_test:
312 ; CHECK: .size llvm_mips_ilvr_h_test
314 @llvm_mips_ilvr_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16
315 @llvm_mips_ilvr_w_ARG2 = global <4 x i32> <i32 4, i32 5, i32 6, i32 7>, align 16
316 @llvm_mips_ilvr_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16
318 define void @llvm_mips_ilvr_w_test() nounwind {
320 %0 = load <4 x i32>* @llvm_mips_ilvr_w_ARG1
321 %1 = load <4 x i32>* @llvm_mips_ilvr_w_ARG2
322 %2 = tail call <4 x i32> @llvm.mips.ilvr.w(<4 x i32> %0, <4 x i32> %1)
323 store <4 x i32> %2, <4 x i32>* @llvm_mips_ilvr_w_RES
327 declare <4 x i32> @llvm.mips.ilvr.w(<4 x i32>, <4 x i32>) nounwind
329 ; CHECK: llvm_mips_ilvr_w_test:
334 ; CHECK: .size llvm_mips_ilvr_w_test
336 @llvm_mips_ilvr_d_ARG1 = global <2 x i64> <i64 0, i64 1>, align 16
337 @llvm_mips_ilvr_d_ARG2 = global <2 x i64> <i64 2, i64 3>, align 16
338 @llvm_mips_ilvr_d_RES = global <2 x i64> <i64 0, i64 0>, align 16
340 define void @llvm_mips_ilvr_d_test() nounwind {
342 %0 = load <2 x i64>* @llvm_mips_ilvr_d_ARG1
343 %1 = load <2 x i64>* @llvm_mips_ilvr_d_ARG2
344 %2 = tail call <2 x i64> @llvm.mips.ilvr.d(<2 x i64> %0, <2 x i64> %1)
345 store <2 x i64> %2, <2 x i64>* @llvm_mips_ilvr_d_RES
349 declare <2 x i64> @llvm.mips.ilvr.d(<2 x i64>, <2 x i64>) nounwind
351 ; CHECK: llvm_mips_ilvr_d_test:
356 ; CHECK: .size llvm_mips_ilvr_d_test