1 ; Test the MSA intrinsics that are encoded with the 3R instruction format.
2 ; There are lots of these so this covers those beginning with 'm'
4 ; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s
6 @llvm_mips_max_a_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
7 @llvm_mips_max_a_b_ARG2 = global <16 x i8> <i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23, i8 24, i8 25, i8 26, i8 27, i8 28, i8 29, i8 30, i8 31>, align 16
8 @llvm_mips_max_a_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16
10 define void @llvm_mips_max_a_b_test() nounwind {
12 %0 = load <16 x i8>* @llvm_mips_max_a_b_ARG1
13 %1 = load <16 x i8>* @llvm_mips_max_a_b_ARG2
14 %2 = tail call <16 x i8> @llvm.mips.max.a.b(<16 x i8> %0, <16 x i8> %1)
15 store <16 x i8> %2, <16 x i8>* @llvm_mips_max_a_b_RES
19 declare <16 x i8> @llvm.mips.max.a.b(<16 x i8>, <16 x i8>) nounwind
21 ; CHECK: llvm_mips_max_a_b_test:
26 ; CHECK: .size llvm_mips_max_a_b_test
28 @llvm_mips_max_a_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16
29 @llvm_mips_max_a_h_ARG2 = global <8 x i16> <i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15>, align 16
30 @llvm_mips_max_a_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16
32 define void @llvm_mips_max_a_h_test() nounwind {
34 %0 = load <8 x i16>* @llvm_mips_max_a_h_ARG1
35 %1 = load <8 x i16>* @llvm_mips_max_a_h_ARG2
36 %2 = tail call <8 x i16> @llvm.mips.max.a.h(<8 x i16> %0, <8 x i16> %1)
37 store <8 x i16> %2, <8 x i16>* @llvm_mips_max_a_h_RES
41 declare <8 x i16> @llvm.mips.max.a.h(<8 x i16>, <8 x i16>) nounwind
43 ; CHECK: llvm_mips_max_a_h_test:
48 ; CHECK: .size llvm_mips_max_a_h_test
50 @llvm_mips_max_a_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16
51 @llvm_mips_max_a_w_ARG2 = global <4 x i32> <i32 4, i32 5, i32 6, i32 7>, align 16
52 @llvm_mips_max_a_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16
54 define void @llvm_mips_max_a_w_test() nounwind {
56 %0 = load <4 x i32>* @llvm_mips_max_a_w_ARG1
57 %1 = load <4 x i32>* @llvm_mips_max_a_w_ARG2
58 %2 = tail call <4 x i32> @llvm.mips.max.a.w(<4 x i32> %0, <4 x i32> %1)
59 store <4 x i32> %2, <4 x i32>* @llvm_mips_max_a_w_RES
63 declare <4 x i32> @llvm.mips.max.a.w(<4 x i32>, <4 x i32>) nounwind
65 ; CHECK: llvm_mips_max_a_w_test:
70 ; CHECK: .size llvm_mips_max_a_w_test
72 @llvm_mips_max_a_d_ARG1 = global <2 x i64> <i64 0, i64 1>, align 16
73 @llvm_mips_max_a_d_ARG2 = global <2 x i64> <i64 2, i64 3>, align 16
74 @llvm_mips_max_a_d_RES = global <2 x i64> <i64 0, i64 0>, align 16
76 define void @llvm_mips_max_a_d_test() nounwind {
78 %0 = load <2 x i64>* @llvm_mips_max_a_d_ARG1
79 %1 = load <2 x i64>* @llvm_mips_max_a_d_ARG2
80 %2 = tail call <2 x i64> @llvm.mips.max.a.d(<2 x i64> %0, <2 x i64> %1)
81 store <2 x i64> %2, <2 x i64>* @llvm_mips_max_a_d_RES
85 declare <2 x i64> @llvm.mips.max.a.d(<2 x i64>, <2 x i64>) nounwind
87 ; CHECK: llvm_mips_max_a_d_test:
92 ; CHECK: .size llvm_mips_max_a_d_test
94 @llvm_mips_max_s_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
95 @llvm_mips_max_s_b_ARG2 = global <16 x i8> <i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23, i8 24, i8 25, i8 26, i8 27, i8 28, i8 29, i8 30, i8 31>, align 16
96 @llvm_mips_max_s_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16
98 define void @llvm_mips_max_s_b_test() nounwind {
100 %0 = load <16 x i8>* @llvm_mips_max_s_b_ARG1
101 %1 = load <16 x i8>* @llvm_mips_max_s_b_ARG2
102 %2 = tail call <16 x i8> @llvm.mips.max.s.b(<16 x i8> %0, <16 x i8> %1)
103 store <16 x i8> %2, <16 x i8>* @llvm_mips_max_s_b_RES
107 declare <16 x i8> @llvm.mips.max.s.b(<16 x i8>, <16 x i8>) nounwind
109 ; CHECK: llvm_mips_max_s_b_test:
114 ; CHECK: .size llvm_mips_max_s_b_test
116 @llvm_mips_max_s_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16
117 @llvm_mips_max_s_h_ARG2 = global <8 x i16> <i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15>, align 16
118 @llvm_mips_max_s_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16
120 define void @llvm_mips_max_s_h_test() nounwind {
122 %0 = load <8 x i16>* @llvm_mips_max_s_h_ARG1
123 %1 = load <8 x i16>* @llvm_mips_max_s_h_ARG2
124 %2 = tail call <8 x i16> @llvm.mips.max.s.h(<8 x i16> %0, <8 x i16> %1)
125 store <8 x i16> %2, <8 x i16>* @llvm_mips_max_s_h_RES
129 declare <8 x i16> @llvm.mips.max.s.h(<8 x i16>, <8 x i16>) nounwind
131 ; CHECK: llvm_mips_max_s_h_test:
136 ; CHECK: .size llvm_mips_max_s_h_test
138 @llvm_mips_max_s_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16
139 @llvm_mips_max_s_w_ARG2 = global <4 x i32> <i32 4, i32 5, i32 6, i32 7>, align 16
140 @llvm_mips_max_s_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16
142 define void @llvm_mips_max_s_w_test() nounwind {
144 %0 = load <4 x i32>* @llvm_mips_max_s_w_ARG1
145 %1 = load <4 x i32>* @llvm_mips_max_s_w_ARG2
146 %2 = tail call <4 x i32> @llvm.mips.max.s.w(<4 x i32> %0, <4 x i32> %1)
147 store <4 x i32> %2, <4 x i32>* @llvm_mips_max_s_w_RES
151 declare <4 x i32> @llvm.mips.max.s.w(<4 x i32>, <4 x i32>) nounwind
153 ; CHECK: llvm_mips_max_s_w_test:
158 ; CHECK: .size llvm_mips_max_s_w_test
160 @llvm_mips_max_s_d_ARG1 = global <2 x i64> <i64 0, i64 1>, align 16
161 @llvm_mips_max_s_d_ARG2 = global <2 x i64> <i64 2, i64 3>, align 16
162 @llvm_mips_max_s_d_RES = global <2 x i64> <i64 0, i64 0>, align 16
164 define void @llvm_mips_max_s_d_test() nounwind {
166 %0 = load <2 x i64>* @llvm_mips_max_s_d_ARG1
167 %1 = load <2 x i64>* @llvm_mips_max_s_d_ARG2
168 %2 = tail call <2 x i64> @llvm.mips.max.s.d(<2 x i64> %0, <2 x i64> %1)
169 store <2 x i64> %2, <2 x i64>* @llvm_mips_max_s_d_RES
173 declare <2 x i64> @llvm.mips.max.s.d(<2 x i64>, <2 x i64>) nounwind
175 ; CHECK: llvm_mips_max_s_d_test:
180 ; CHECK: .size llvm_mips_max_s_d_test
182 @llvm_mips_max_u_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
183 @llvm_mips_max_u_b_ARG2 = global <16 x i8> <i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23, i8 24, i8 25, i8 26, i8 27, i8 28, i8 29, i8 30, i8 31>, align 16
184 @llvm_mips_max_u_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16
186 define void @llvm_mips_max_u_b_test() nounwind {
188 %0 = load <16 x i8>* @llvm_mips_max_u_b_ARG1
189 %1 = load <16 x i8>* @llvm_mips_max_u_b_ARG2
190 %2 = tail call <16 x i8> @llvm.mips.max.u.b(<16 x i8> %0, <16 x i8> %1)
191 store <16 x i8> %2, <16 x i8>* @llvm_mips_max_u_b_RES
195 declare <16 x i8> @llvm.mips.max.u.b(<16 x i8>, <16 x i8>) nounwind
197 ; CHECK: llvm_mips_max_u_b_test:
202 ; CHECK: .size llvm_mips_max_u_b_test
204 @llvm_mips_max_u_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16
205 @llvm_mips_max_u_h_ARG2 = global <8 x i16> <i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15>, align 16
206 @llvm_mips_max_u_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16
208 define void @llvm_mips_max_u_h_test() nounwind {
210 %0 = load <8 x i16>* @llvm_mips_max_u_h_ARG1
211 %1 = load <8 x i16>* @llvm_mips_max_u_h_ARG2
212 %2 = tail call <8 x i16> @llvm.mips.max.u.h(<8 x i16> %0, <8 x i16> %1)
213 store <8 x i16> %2, <8 x i16>* @llvm_mips_max_u_h_RES
217 declare <8 x i16> @llvm.mips.max.u.h(<8 x i16>, <8 x i16>) nounwind
219 ; CHECK: llvm_mips_max_u_h_test:
224 ; CHECK: .size llvm_mips_max_u_h_test
226 @llvm_mips_max_u_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16
227 @llvm_mips_max_u_w_ARG2 = global <4 x i32> <i32 4, i32 5, i32 6, i32 7>, align 16
228 @llvm_mips_max_u_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16
230 define void @llvm_mips_max_u_w_test() nounwind {
232 %0 = load <4 x i32>* @llvm_mips_max_u_w_ARG1
233 %1 = load <4 x i32>* @llvm_mips_max_u_w_ARG2
234 %2 = tail call <4 x i32> @llvm.mips.max.u.w(<4 x i32> %0, <4 x i32> %1)
235 store <4 x i32> %2, <4 x i32>* @llvm_mips_max_u_w_RES
239 declare <4 x i32> @llvm.mips.max.u.w(<4 x i32>, <4 x i32>) nounwind
241 ; CHECK: llvm_mips_max_u_w_test:
246 ; CHECK: .size llvm_mips_max_u_w_test
248 @llvm_mips_max_u_d_ARG1 = global <2 x i64> <i64 0, i64 1>, align 16
249 @llvm_mips_max_u_d_ARG2 = global <2 x i64> <i64 2, i64 3>, align 16
250 @llvm_mips_max_u_d_RES = global <2 x i64> <i64 0, i64 0>, align 16
252 define void @llvm_mips_max_u_d_test() nounwind {
254 %0 = load <2 x i64>* @llvm_mips_max_u_d_ARG1
255 %1 = load <2 x i64>* @llvm_mips_max_u_d_ARG2
256 %2 = tail call <2 x i64> @llvm.mips.max.u.d(<2 x i64> %0, <2 x i64> %1)
257 store <2 x i64> %2, <2 x i64>* @llvm_mips_max_u_d_RES
261 declare <2 x i64> @llvm.mips.max.u.d(<2 x i64>, <2 x i64>) nounwind
263 ; CHECK: llvm_mips_max_u_d_test:
268 ; CHECK: .size llvm_mips_max_u_d_test
270 @llvm_mips_min_a_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
271 @llvm_mips_min_a_b_ARG2 = global <16 x i8> <i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23, i8 24, i8 25, i8 26, i8 27, i8 28, i8 29, i8 30, i8 31>, align 16
272 @llvm_mips_min_a_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16
274 define void @llvm_mips_min_a_b_test() nounwind {
276 %0 = load <16 x i8>* @llvm_mips_min_a_b_ARG1
277 %1 = load <16 x i8>* @llvm_mips_min_a_b_ARG2
278 %2 = tail call <16 x i8> @llvm.mips.min.a.b(<16 x i8> %0, <16 x i8> %1)
279 store <16 x i8> %2, <16 x i8>* @llvm_mips_min_a_b_RES
283 declare <16 x i8> @llvm.mips.min.a.b(<16 x i8>, <16 x i8>) nounwind
285 ; CHECK: llvm_mips_min_a_b_test:
290 ; CHECK: .size llvm_mips_min_a_b_test
292 @llvm_mips_min_a_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16
293 @llvm_mips_min_a_h_ARG2 = global <8 x i16> <i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15>, align 16
294 @llvm_mips_min_a_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16
296 define void @llvm_mips_min_a_h_test() nounwind {
298 %0 = load <8 x i16>* @llvm_mips_min_a_h_ARG1
299 %1 = load <8 x i16>* @llvm_mips_min_a_h_ARG2
300 %2 = tail call <8 x i16> @llvm.mips.min.a.h(<8 x i16> %0, <8 x i16> %1)
301 store <8 x i16> %2, <8 x i16>* @llvm_mips_min_a_h_RES
305 declare <8 x i16> @llvm.mips.min.a.h(<8 x i16>, <8 x i16>) nounwind
307 ; CHECK: llvm_mips_min_a_h_test:
312 ; CHECK: .size llvm_mips_min_a_h_test
314 @llvm_mips_min_a_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16
315 @llvm_mips_min_a_w_ARG2 = global <4 x i32> <i32 4, i32 5, i32 6, i32 7>, align 16
316 @llvm_mips_min_a_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16
318 define void @llvm_mips_min_a_w_test() nounwind {
320 %0 = load <4 x i32>* @llvm_mips_min_a_w_ARG1
321 %1 = load <4 x i32>* @llvm_mips_min_a_w_ARG2
322 %2 = tail call <4 x i32> @llvm.mips.min.a.w(<4 x i32> %0, <4 x i32> %1)
323 store <4 x i32> %2, <4 x i32>* @llvm_mips_min_a_w_RES
327 declare <4 x i32> @llvm.mips.min.a.w(<4 x i32>, <4 x i32>) nounwind
329 ; CHECK: llvm_mips_min_a_w_test:
334 ; CHECK: .size llvm_mips_min_a_w_test
336 @llvm_mips_min_a_d_ARG1 = global <2 x i64> <i64 0, i64 1>, align 16
337 @llvm_mips_min_a_d_ARG2 = global <2 x i64> <i64 2, i64 3>, align 16
338 @llvm_mips_min_a_d_RES = global <2 x i64> <i64 0, i64 0>, align 16
340 define void @llvm_mips_min_a_d_test() nounwind {
342 %0 = load <2 x i64>* @llvm_mips_min_a_d_ARG1
343 %1 = load <2 x i64>* @llvm_mips_min_a_d_ARG2
344 %2 = tail call <2 x i64> @llvm.mips.min.a.d(<2 x i64> %0, <2 x i64> %1)
345 store <2 x i64> %2, <2 x i64>* @llvm_mips_min_a_d_RES
349 declare <2 x i64> @llvm.mips.min.a.d(<2 x i64>, <2 x i64>) nounwind
351 ; CHECK: llvm_mips_min_a_d_test:
356 ; CHECK: .size llvm_mips_min_a_d_test
358 @llvm_mips_min_s_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
359 @llvm_mips_min_s_b_ARG2 = global <16 x i8> <i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23, i8 24, i8 25, i8 26, i8 27, i8 28, i8 29, i8 30, i8 31>, align 16
360 @llvm_mips_min_s_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16
362 define void @llvm_mips_min_s_b_test() nounwind {
364 %0 = load <16 x i8>* @llvm_mips_min_s_b_ARG1
365 %1 = load <16 x i8>* @llvm_mips_min_s_b_ARG2
366 %2 = tail call <16 x i8> @llvm.mips.min.s.b(<16 x i8> %0, <16 x i8> %1)
367 store <16 x i8> %2, <16 x i8>* @llvm_mips_min_s_b_RES
371 declare <16 x i8> @llvm.mips.min.s.b(<16 x i8>, <16 x i8>) nounwind
373 ; CHECK: llvm_mips_min_s_b_test:
378 ; CHECK: .size llvm_mips_min_s_b_test
380 @llvm_mips_min_s_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16
381 @llvm_mips_min_s_h_ARG2 = global <8 x i16> <i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15>, align 16
382 @llvm_mips_min_s_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16
384 define void @llvm_mips_min_s_h_test() nounwind {
386 %0 = load <8 x i16>* @llvm_mips_min_s_h_ARG1
387 %1 = load <8 x i16>* @llvm_mips_min_s_h_ARG2
388 %2 = tail call <8 x i16> @llvm.mips.min.s.h(<8 x i16> %0, <8 x i16> %1)
389 store <8 x i16> %2, <8 x i16>* @llvm_mips_min_s_h_RES
393 declare <8 x i16> @llvm.mips.min.s.h(<8 x i16>, <8 x i16>) nounwind
395 ; CHECK: llvm_mips_min_s_h_test:
400 ; CHECK: .size llvm_mips_min_s_h_test
402 @llvm_mips_min_s_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16
403 @llvm_mips_min_s_w_ARG2 = global <4 x i32> <i32 4, i32 5, i32 6, i32 7>, align 16
404 @llvm_mips_min_s_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16
406 define void @llvm_mips_min_s_w_test() nounwind {
408 %0 = load <4 x i32>* @llvm_mips_min_s_w_ARG1
409 %1 = load <4 x i32>* @llvm_mips_min_s_w_ARG2
410 %2 = tail call <4 x i32> @llvm.mips.min.s.w(<4 x i32> %0, <4 x i32> %1)
411 store <4 x i32> %2, <4 x i32>* @llvm_mips_min_s_w_RES
415 declare <4 x i32> @llvm.mips.min.s.w(<4 x i32>, <4 x i32>) nounwind
417 ; CHECK: llvm_mips_min_s_w_test:
422 ; CHECK: .size llvm_mips_min_s_w_test
424 @llvm_mips_min_s_d_ARG1 = global <2 x i64> <i64 0, i64 1>, align 16
425 @llvm_mips_min_s_d_ARG2 = global <2 x i64> <i64 2, i64 3>, align 16
426 @llvm_mips_min_s_d_RES = global <2 x i64> <i64 0, i64 0>, align 16
428 define void @llvm_mips_min_s_d_test() nounwind {
430 %0 = load <2 x i64>* @llvm_mips_min_s_d_ARG1
431 %1 = load <2 x i64>* @llvm_mips_min_s_d_ARG2
432 %2 = tail call <2 x i64> @llvm.mips.min.s.d(<2 x i64> %0, <2 x i64> %1)
433 store <2 x i64> %2, <2 x i64>* @llvm_mips_min_s_d_RES
437 declare <2 x i64> @llvm.mips.min.s.d(<2 x i64>, <2 x i64>) nounwind
439 ; CHECK: llvm_mips_min_s_d_test:
444 ; CHECK: .size llvm_mips_min_s_d_test
446 @llvm_mips_min_u_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
447 @llvm_mips_min_u_b_ARG2 = global <16 x i8> <i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23, i8 24, i8 25, i8 26, i8 27, i8 28, i8 29, i8 30, i8 31>, align 16
448 @llvm_mips_min_u_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16
450 define void @llvm_mips_min_u_b_test() nounwind {
452 %0 = load <16 x i8>* @llvm_mips_min_u_b_ARG1
453 %1 = load <16 x i8>* @llvm_mips_min_u_b_ARG2
454 %2 = tail call <16 x i8> @llvm.mips.min.u.b(<16 x i8> %0, <16 x i8> %1)
455 store <16 x i8> %2, <16 x i8>* @llvm_mips_min_u_b_RES
459 declare <16 x i8> @llvm.mips.min.u.b(<16 x i8>, <16 x i8>) nounwind
461 ; CHECK: llvm_mips_min_u_b_test:
466 ; CHECK: .size llvm_mips_min_u_b_test
468 @llvm_mips_min_u_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16
469 @llvm_mips_min_u_h_ARG2 = global <8 x i16> <i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15>, align 16
470 @llvm_mips_min_u_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16
472 define void @llvm_mips_min_u_h_test() nounwind {
474 %0 = load <8 x i16>* @llvm_mips_min_u_h_ARG1
475 %1 = load <8 x i16>* @llvm_mips_min_u_h_ARG2
476 %2 = tail call <8 x i16> @llvm.mips.min.u.h(<8 x i16> %0, <8 x i16> %1)
477 store <8 x i16> %2, <8 x i16>* @llvm_mips_min_u_h_RES
481 declare <8 x i16> @llvm.mips.min.u.h(<8 x i16>, <8 x i16>) nounwind
483 ; CHECK: llvm_mips_min_u_h_test:
488 ; CHECK: .size llvm_mips_min_u_h_test
490 @llvm_mips_min_u_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16
491 @llvm_mips_min_u_w_ARG2 = global <4 x i32> <i32 4, i32 5, i32 6, i32 7>, align 16
492 @llvm_mips_min_u_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16
494 define void @llvm_mips_min_u_w_test() nounwind {
496 %0 = load <4 x i32>* @llvm_mips_min_u_w_ARG1
497 %1 = load <4 x i32>* @llvm_mips_min_u_w_ARG2
498 %2 = tail call <4 x i32> @llvm.mips.min.u.w(<4 x i32> %0, <4 x i32> %1)
499 store <4 x i32> %2, <4 x i32>* @llvm_mips_min_u_w_RES
503 declare <4 x i32> @llvm.mips.min.u.w(<4 x i32>, <4 x i32>) nounwind
505 ; CHECK: llvm_mips_min_u_w_test:
510 ; CHECK: .size llvm_mips_min_u_w_test
512 @llvm_mips_min_u_d_ARG1 = global <2 x i64> <i64 0, i64 1>, align 16
513 @llvm_mips_min_u_d_ARG2 = global <2 x i64> <i64 2, i64 3>, align 16
514 @llvm_mips_min_u_d_RES = global <2 x i64> <i64 0, i64 0>, align 16
516 define void @llvm_mips_min_u_d_test() nounwind {
518 %0 = load <2 x i64>* @llvm_mips_min_u_d_ARG1
519 %1 = load <2 x i64>* @llvm_mips_min_u_d_ARG2
520 %2 = tail call <2 x i64> @llvm.mips.min.u.d(<2 x i64> %0, <2 x i64> %1)
521 store <2 x i64> %2, <2 x i64>* @llvm_mips_min_u_d_RES
525 declare <2 x i64> @llvm.mips.min.u.d(<2 x i64>, <2 x i64>) nounwind
527 ; CHECK: llvm_mips_min_u_d_test:
532 ; CHECK: .size llvm_mips_min_u_d_test
534 @llvm_mips_mod_s_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
535 @llvm_mips_mod_s_b_ARG2 = global <16 x i8> <i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23, i8 24, i8 25, i8 26, i8 27, i8 28, i8 29, i8 30, i8 31>, align 16
536 @llvm_mips_mod_s_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16
538 define void @llvm_mips_mod_s_b_test() nounwind {
540 %0 = load <16 x i8>* @llvm_mips_mod_s_b_ARG1
541 %1 = load <16 x i8>* @llvm_mips_mod_s_b_ARG2
542 %2 = tail call <16 x i8> @llvm.mips.mod.s.b(<16 x i8> %0, <16 x i8> %1)
543 store <16 x i8> %2, <16 x i8>* @llvm_mips_mod_s_b_RES
547 declare <16 x i8> @llvm.mips.mod.s.b(<16 x i8>, <16 x i8>) nounwind
549 ; CHECK: llvm_mips_mod_s_b_test:
554 ; CHECK: .size llvm_mips_mod_s_b_test
556 @llvm_mips_mod_s_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16
557 @llvm_mips_mod_s_h_ARG2 = global <8 x i16> <i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15>, align 16
558 @llvm_mips_mod_s_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16
560 define void @llvm_mips_mod_s_h_test() nounwind {
562 %0 = load <8 x i16>* @llvm_mips_mod_s_h_ARG1
563 %1 = load <8 x i16>* @llvm_mips_mod_s_h_ARG2
564 %2 = tail call <8 x i16> @llvm.mips.mod.s.h(<8 x i16> %0, <8 x i16> %1)
565 store <8 x i16> %2, <8 x i16>* @llvm_mips_mod_s_h_RES
569 declare <8 x i16> @llvm.mips.mod.s.h(<8 x i16>, <8 x i16>) nounwind
571 ; CHECK: llvm_mips_mod_s_h_test:
576 ; CHECK: .size llvm_mips_mod_s_h_test
578 @llvm_mips_mod_s_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16
579 @llvm_mips_mod_s_w_ARG2 = global <4 x i32> <i32 4, i32 5, i32 6, i32 7>, align 16
580 @llvm_mips_mod_s_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16
582 define void @llvm_mips_mod_s_w_test() nounwind {
584 %0 = load <4 x i32>* @llvm_mips_mod_s_w_ARG1
585 %1 = load <4 x i32>* @llvm_mips_mod_s_w_ARG2
586 %2 = tail call <4 x i32> @llvm.mips.mod.s.w(<4 x i32> %0, <4 x i32> %1)
587 store <4 x i32> %2, <4 x i32>* @llvm_mips_mod_s_w_RES
591 declare <4 x i32> @llvm.mips.mod.s.w(<4 x i32>, <4 x i32>) nounwind
593 ; CHECK: llvm_mips_mod_s_w_test:
598 ; CHECK: .size llvm_mips_mod_s_w_test
600 @llvm_mips_mod_s_d_ARG1 = global <2 x i64> <i64 0, i64 1>, align 16
601 @llvm_mips_mod_s_d_ARG2 = global <2 x i64> <i64 2, i64 3>, align 16
602 @llvm_mips_mod_s_d_RES = global <2 x i64> <i64 0, i64 0>, align 16
604 define void @llvm_mips_mod_s_d_test() nounwind {
606 %0 = load <2 x i64>* @llvm_mips_mod_s_d_ARG1
607 %1 = load <2 x i64>* @llvm_mips_mod_s_d_ARG2
608 %2 = tail call <2 x i64> @llvm.mips.mod.s.d(<2 x i64> %0, <2 x i64> %1)
609 store <2 x i64> %2, <2 x i64>* @llvm_mips_mod_s_d_RES
613 declare <2 x i64> @llvm.mips.mod.s.d(<2 x i64>, <2 x i64>) nounwind
615 ; CHECK: llvm_mips_mod_s_d_test:
620 ; CHECK: .size llvm_mips_mod_s_d_test
622 @llvm_mips_mod_u_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
623 @llvm_mips_mod_u_b_ARG2 = global <16 x i8> <i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23, i8 24, i8 25, i8 26, i8 27, i8 28, i8 29, i8 30, i8 31>, align 16
624 @llvm_mips_mod_u_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16
626 define void @llvm_mips_mod_u_b_test() nounwind {
628 %0 = load <16 x i8>* @llvm_mips_mod_u_b_ARG1
629 %1 = load <16 x i8>* @llvm_mips_mod_u_b_ARG2
630 %2 = tail call <16 x i8> @llvm.mips.mod.u.b(<16 x i8> %0, <16 x i8> %1)
631 store <16 x i8> %2, <16 x i8>* @llvm_mips_mod_u_b_RES
635 declare <16 x i8> @llvm.mips.mod.u.b(<16 x i8>, <16 x i8>) nounwind
637 ; CHECK: llvm_mips_mod_u_b_test:
642 ; CHECK: .size llvm_mips_mod_u_b_test
644 @llvm_mips_mod_u_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16
645 @llvm_mips_mod_u_h_ARG2 = global <8 x i16> <i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15>, align 16
646 @llvm_mips_mod_u_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16
648 define void @llvm_mips_mod_u_h_test() nounwind {
650 %0 = load <8 x i16>* @llvm_mips_mod_u_h_ARG1
651 %1 = load <8 x i16>* @llvm_mips_mod_u_h_ARG2
652 %2 = tail call <8 x i16> @llvm.mips.mod.u.h(<8 x i16> %0, <8 x i16> %1)
653 store <8 x i16> %2, <8 x i16>* @llvm_mips_mod_u_h_RES
657 declare <8 x i16> @llvm.mips.mod.u.h(<8 x i16>, <8 x i16>) nounwind
659 ; CHECK: llvm_mips_mod_u_h_test:
664 ; CHECK: .size llvm_mips_mod_u_h_test
666 @llvm_mips_mod_u_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16
667 @llvm_mips_mod_u_w_ARG2 = global <4 x i32> <i32 4, i32 5, i32 6, i32 7>, align 16
668 @llvm_mips_mod_u_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16
670 define void @llvm_mips_mod_u_w_test() nounwind {
672 %0 = load <4 x i32>* @llvm_mips_mod_u_w_ARG1
673 %1 = load <4 x i32>* @llvm_mips_mod_u_w_ARG2
674 %2 = tail call <4 x i32> @llvm.mips.mod.u.w(<4 x i32> %0, <4 x i32> %1)
675 store <4 x i32> %2, <4 x i32>* @llvm_mips_mod_u_w_RES
679 declare <4 x i32> @llvm.mips.mod.u.w(<4 x i32>, <4 x i32>) nounwind
681 ; CHECK: llvm_mips_mod_u_w_test:
686 ; CHECK: .size llvm_mips_mod_u_w_test
688 @llvm_mips_mod_u_d_ARG1 = global <2 x i64> <i64 0, i64 1>, align 16
689 @llvm_mips_mod_u_d_ARG2 = global <2 x i64> <i64 2, i64 3>, align 16
690 @llvm_mips_mod_u_d_RES = global <2 x i64> <i64 0, i64 0>, align 16
692 define void @llvm_mips_mod_u_d_test() nounwind {
694 %0 = load <2 x i64>* @llvm_mips_mod_u_d_ARG1
695 %1 = load <2 x i64>* @llvm_mips_mod_u_d_ARG2
696 %2 = tail call <2 x i64> @llvm.mips.mod.u.d(<2 x i64> %0, <2 x i64> %1)
697 store <2 x i64> %2, <2 x i64>* @llvm_mips_mod_u_d_RES
701 declare <2 x i64> @llvm.mips.mod.u.d(<2 x i64>, <2 x i64>) nounwind
703 ; CHECK: llvm_mips_mod_u_d_test:
708 ; CHECK: .size llvm_mips_mod_u_d_test
710 @llvm_mips_mulv_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
711 @llvm_mips_mulv_b_ARG2 = global <16 x i8> <i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23, i8 24, i8 25, i8 26, i8 27, i8 28, i8 29, i8 30, i8 31>, align 16
712 @llvm_mips_mulv_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16
714 define void @llvm_mips_mulv_b_test() nounwind {
716 %0 = load <16 x i8>* @llvm_mips_mulv_b_ARG1
717 %1 = load <16 x i8>* @llvm_mips_mulv_b_ARG2
718 %2 = tail call <16 x i8> @llvm.mips.mulv.b(<16 x i8> %0, <16 x i8> %1)
719 store <16 x i8> %2, <16 x i8>* @llvm_mips_mulv_b_RES
723 declare <16 x i8> @llvm.mips.mulv.b(<16 x i8>, <16 x i8>) nounwind
725 ; CHECK: llvm_mips_mulv_b_test:
730 ; CHECK: .size llvm_mips_mulv_b_test
732 @llvm_mips_mulv_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16
733 @llvm_mips_mulv_h_ARG2 = global <8 x i16> <i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15>, align 16
734 @llvm_mips_mulv_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16
736 define void @llvm_mips_mulv_h_test() nounwind {
738 %0 = load <8 x i16>* @llvm_mips_mulv_h_ARG1
739 %1 = load <8 x i16>* @llvm_mips_mulv_h_ARG2
740 %2 = tail call <8 x i16> @llvm.mips.mulv.h(<8 x i16> %0, <8 x i16> %1)
741 store <8 x i16> %2, <8 x i16>* @llvm_mips_mulv_h_RES
745 declare <8 x i16> @llvm.mips.mulv.h(<8 x i16>, <8 x i16>) nounwind
747 ; CHECK: llvm_mips_mulv_h_test:
752 ; CHECK: .size llvm_mips_mulv_h_test
754 @llvm_mips_mulv_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16
755 @llvm_mips_mulv_w_ARG2 = global <4 x i32> <i32 4, i32 5, i32 6, i32 7>, align 16
756 @llvm_mips_mulv_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16
758 define void @llvm_mips_mulv_w_test() nounwind {
760 %0 = load <4 x i32>* @llvm_mips_mulv_w_ARG1
761 %1 = load <4 x i32>* @llvm_mips_mulv_w_ARG2
762 %2 = tail call <4 x i32> @llvm.mips.mulv.w(<4 x i32> %0, <4 x i32> %1)
763 store <4 x i32> %2, <4 x i32>* @llvm_mips_mulv_w_RES
767 declare <4 x i32> @llvm.mips.mulv.w(<4 x i32>, <4 x i32>) nounwind
769 ; CHECK: llvm_mips_mulv_w_test:
774 ; CHECK: .size llvm_mips_mulv_w_test
776 @llvm_mips_mulv_d_ARG1 = global <2 x i64> <i64 0, i64 1>, align 16
777 @llvm_mips_mulv_d_ARG2 = global <2 x i64> <i64 2, i64 3>, align 16
778 @llvm_mips_mulv_d_RES = global <2 x i64> <i64 0, i64 0>, align 16
780 define void @llvm_mips_mulv_d_test() nounwind {
782 %0 = load <2 x i64>* @llvm_mips_mulv_d_ARG1
783 %1 = load <2 x i64>* @llvm_mips_mulv_d_ARG2
784 %2 = tail call <2 x i64> @llvm.mips.mulv.d(<2 x i64> %0, <2 x i64> %1)
785 store <2 x i64> %2, <2 x i64>* @llvm_mips_mulv_d_RES
789 declare <2 x i64> @llvm.mips.mulv.d(<2 x i64>, <2 x i64>) nounwind
791 ; CHECK: llvm_mips_mulv_d_test:
796 ; CHECK: .size llvm_mips_mulv_d_test
798 define void @mulv_b_test() nounwind {
800 %0 = load <16 x i8>* @llvm_mips_mulv_b_ARG1
801 %1 = load <16 x i8>* @llvm_mips_mulv_b_ARG2
802 %2 = mul <16 x i8> %0, %1
803 store <16 x i8> %2, <16 x i8>* @llvm_mips_mulv_b_RES
807 ; CHECK: mulv_b_test:
812 ; CHECK: .size mulv_b_test
814 define void @mulv_h_test() nounwind {
816 %0 = load <8 x i16>* @llvm_mips_mulv_h_ARG1
817 %1 = load <8 x i16>* @llvm_mips_mulv_h_ARG2
818 %2 = mul <8 x i16> %0, %1
819 store <8 x i16> %2, <8 x i16>* @llvm_mips_mulv_h_RES
823 ; CHECK: mulv_h_test:
828 ; CHECK: .size mulv_h_test
830 define void @mulv_w_test() nounwind {
832 %0 = load <4 x i32>* @llvm_mips_mulv_w_ARG1
833 %1 = load <4 x i32>* @llvm_mips_mulv_w_ARG2
834 %2 = mul <4 x i32> %0, %1
835 store <4 x i32> %2, <4 x i32>* @llvm_mips_mulv_w_RES
839 ; CHECK: mulv_w_test:
844 ; CHECK: .size mulv_w_test
846 define void @mulv_d_test() nounwind {
848 %0 = load <2 x i64>* @llvm_mips_mulv_d_ARG1
849 %1 = load <2 x i64>* @llvm_mips_mulv_d_ARG2
850 %2 = mul <2 x i64> %0, %1
851 store <2 x i64> %2, <2 x i64>* @llvm_mips_mulv_d_RES
855 ; CHECK: mulv_d_test:
860 ; CHECK: .size mulv_d_test