1 ; Test the MSA intrinsics that are encoded with the 3R instruction format.
2 ; There are lots of these so this covers those beginning with 's'
4 ; RUN: llc -march=mips -mattr=+msa < %s | FileCheck %s
6 @llvm_mips_sld_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
7 @llvm_mips_sld_b_ARG2 = global <16 x i8> <i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23, i8 24, i8 25, i8 26, i8 27, i8 28, i8 29, i8 30, i8 31>, align 16
8 @llvm_mips_sld_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16
10 define void @llvm_mips_sld_b_test() nounwind {
12 %0 = load <16 x i8>* @llvm_mips_sld_b_ARG1
13 %1 = load <16 x i8>* @llvm_mips_sld_b_ARG2
14 %2 = tail call <16 x i8> @llvm.mips.sld.b(<16 x i8> %0, <16 x i8> %1)
15 store <16 x i8> %2, <16 x i8>* @llvm_mips_sld_b_RES
19 declare <16 x i8> @llvm.mips.sld.b(<16 x i8>, <16 x i8>) nounwind
21 ; CHECK: llvm_mips_sld_b_test:
26 ; CHECK: .size llvm_mips_sld_b_test
28 @llvm_mips_sld_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16
29 @llvm_mips_sld_h_ARG2 = global <8 x i16> <i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15>, align 16
30 @llvm_mips_sld_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16
32 define void @llvm_mips_sld_h_test() nounwind {
34 %0 = load <8 x i16>* @llvm_mips_sld_h_ARG1
35 %1 = load <8 x i16>* @llvm_mips_sld_h_ARG2
36 %2 = tail call <8 x i16> @llvm.mips.sld.h(<8 x i16> %0, <8 x i16> %1)
37 store <8 x i16> %2, <8 x i16>* @llvm_mips_sld_h_RES
41 declare <8 x i16> @llvm.mips.sld.h(<8 x i16>, <8 x i16>) nounwind
43 ; CHECK: llvm_mips_sld_h_test:
48 ; CHECK: .size llvm_mips_sld_h_test
50 @llvm_mips_sld_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16
51 @llvm_mips_sld_w_ARG2 = global <4 x i32> <i32 4, i32 5, i32 6, i32 7>, align 16
52 @llvm_mips_sld_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16
54 define void @llvm_mips_sld_w_test() nounwind {
56 %0 = load <4 x i32>* @llvm_mips_sld_w_ARG1
57 %1 = load <4 x i32>* @llvm_mips_sld_w_ARG2
58 %2 = tail call <4 x i32> @llvm.mips.sld.w(<4 x i32> %0, <4 x i32> %1)
59 store <4 x i32> %2, <4 x i32>* @llvm_mips_sld_w_RES
63 declare <4 x i32> @llvm.mips.sld.w(<4 x i32>, <4 x i32>) nounwind
65 ; CHECK: llvm_mips_sld_w_test:
70 ; CHECK: .size llvm_mips_sld_w_test
72 @llvm_mips_sld_d_ARG1 = global <2 x i64> <i64 0, i64 1>, align 16
73 @llvm_mips_sld_d_ARG2 = global <2 x i64> <i64 2, i64 3>, align 16
74 @llvm_mips_sld_d_RES = global <2 x i64> <i64 0, i64 0>, align 16
76 define void @llvm_mips_sld_d_test() nounwind {
78 %0 = load <2 x i64>* @llvm_mips_sld_d_ARG1
79 %1 = load <2 x i64>* @llvm_mips_sld_d_ARG2
80 %2 = tail call <2 x i64> @llvm.mips.sld.d(<2 x i64> %0, <2 x i64> %1)
81 store <2 x i64> %2, <2 x i64>* @llvm_mips_sld_d_RES
85 declare <2 x i64> @llvm.mips.sld.d(<2 x i64>, <2 x i64>) nounwind
87 ; CHECK: llvm_mips_sld_d_test:
92 ; CHECK: .size llvm_mips_sld_d_test
94 @llvm_mips_sll_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
95 @llvm_mips_sll_b_ARG2 = global <16 x i8> <i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23, i8 24, i8 25, i8 26, i8 27, i8 28, i8 29, i8 30, i8 31>, align 16
96 @llvm_mips_sll_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16
98 define void @llvm_mips_sll_b_test() nounwind {
100 %0 = load <16 x i8>* @llvm_mips_sll_b_ARG1
101 %1 = load <16 x i8>* @llvm_mips_sll_b_ARG2
102 %2 = tail call <16 x i8> @llvm.mips.sll.b(<16 x i8> %0, <16 x i8> %1)
103 store <16 x i8> %2, <16 x i8>* @llvm_mips_sll_b_RES
107 declare <16 x i8> @llvm.mips.sll.b(<16 x i8>, <16 x i8>) nounwind
109 ; CHECK: llvm_mips_sll_b_test:
114 ; CHECK: .size llvm_mips_sll_b_test
116 @llvm_mips_sll_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16
117 @llvm_mips_sll_h_ARG2 = global <8 x i16> <i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15>, align 16
118 @llvm_mips_sll_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16
120 define void @llvm_mips_sll_h_test() nounwind {
122 %0 = load <8 x i16>* @llvm_mips_sll_h_ARG1
123 %1 = load <8 x i16>* @llvm_mips_sll_h_ARG2
124 %2 = tail call <8 x i16> @llvm.mips.sll.h(<8 x i16> %0, <8 x i16> %1)
125 store <8 x i16> %2, <8 x i16>* @llvm_mips_sll_h_RES
129 declare <8 x i16> @llvm.mips.sll.h(<8 x i16>, <8 x i16>) nounwind
131 ; CHECK: llvm_mips_sll_h_test:
136 ; CHECK: .size llvm_mips_sll_h_test
138 @llvm_mips_sll_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16
139 @llvm_mips_sll_w_ARG2 = global <4 x i32> <i32 4, i32 5, i32 6, i32 7>, align 16
140 @llvm_mips_sll_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16
142 define void @llvm_mips_sll_w_test() nounwind {
144 %0 = load <4 x i32>* @llvm_mips_sll_w_ARG1
145 %1 = load <4 x i32>* @llvm_mips_sll_w_ARG2
146 %2 = tail call <4 x i32> @llvm.mips.sll.w(<4 x i32> %0, <4 x i32> %1)
147 store <4 x i32> %2, <4 x i32>* @llvm_mips_sll_w_RES
151 declare <4 x i32> @llvm.mips.sll.w(<4 x i32>, <4 x i32>) nounwind
153 ; CHECK: llvm_mips_sll_w_test:
158 ; CHECK: .size llvm_mips_sll_w_test
160 @llvm_mips_sll_d_ARG1 = global <2 x i64> <i64 0, i64 1>, align 16
161 @llvm_mips_sll_d_ARG2 = global <2 x i64> <i64 2, i64 3>, align 16
162 @llvm_mips_sll_d_RES = global <2 x i64> <i64 0, i64 0>, align 16
164 define void @llvm_mips_sll_d_test() nounwind {
166 %0 = load <2 x i64>* @llvm_mips_sll_d_ARG1
167 %1 = load <2 x i64>* @llvm_mips_sll_d_ARG2
168 %2 = tail call <2 x i64> @llvm.mips.sll.d(<2 x i64> %0, <2 x i64> %1)
169 store <2 x i64> %2, <2 x i64>* @llvm_mips_sll_d_RES
173 declare <2 x i64> @llvm.mips.sll.d(<2 x i64>, <2 x i64>) nounwind
175 ; CHECK: llvm_mips_sll_d_test:
180 ; CHECK: .size llvm_mips_sll_d_test
182 define void @sll_b_test() nounwind {
184 %0 = load <16 x i8>* @llvm_mips_sll_b_ARG1
185 %1 = load <16 x i8>* @llvm_mips_sll_b_ARG2
186 %2 = shl <16 x i8> %0, %1
187 store <16 x i8> %2, <16 x i8>* @llvm_mips_sll_b_RES
196 ; CHECK: .size sll_b_test
198 define void @sll_h_test() nounwind {
200 %0 = load <8 x i16>* @llvm_mips_sll_h_ARG1
201 %1 = load <8 x i16>* @llvm_mips_sll_h_ARG2
202 %2 = shl <8 x i16> %0, %1
203 store <8 x i16> %2, <8 x i16>* @llvm_mips_sll_h_RES
212 ; CHECK: .size sll_h_test
214 define void @sll_w_test() nounwind {
216 %0 = load <4 x i32>* @llvm_mips_sll_w_ARG1
217 %1 = load <4 x i32>* @llvm_mips_sll_w_ARG2
218 %2 = shl <4 x i32> %0, %1
219 store <4 x i32> %2, <4 x i32>* @llvm_mips_sll_w_RES
228 ; CHECK: .size sll_w_test
230 define void @sll_d_test() nounwind {
232 %0 = load <2 x i64>* @llvm_mips_sll_d_ARG1
233 %1 = load <2 x i64>* @llvm_mips_sll_d_ARG2
234 %2 = shl <2 x i64> %0, %1
235 store <2 x i64> %2, <2 x i64>* @llvm_mips_sll_d_RES
244 ; CHECK: .size sll_d_test
246 @llvm_mips_sra_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
247 @llvm_mips_sra_b_ARG2 = global <16 x i8> <i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23, i8 24, i8 25, i8 26, i8 27, i8 28, i8 29, i8 30, i8 31>, align 16
248 @llvm_mips_sra_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16
250 define void @llvm_mips_sra_b_test() nounwind {
252 %0 = load <16 x i8>* @llvm_mips_sra_b_ARG1
253 %1 = load <16 x i8>* @llvm_mips_sra_b_ARG2
254 %2 = tail call <16 x i8> @llvm.mips.sra.b(<16 x i8> %0, <16 x i8> %1)
255 store <16 x i8> %2, <16 x i8>* @llvm_mips_sra_b_RES
259 declare <16 x i8> @llvm.mips.sra.b(<16 x i8>, <16 x i8>) nounwind
261 ; CHECK: llvm_mips_sra_b_test:
266 ; CHECK: .size llvm_mips_sra_b_test
268 @llvm_mips_sra_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16
269 @llvm_mips_sra_h_ARG2 = global <8 x i16> <i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15>, align 16
270 @llvm_mips_sra_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16
272 define void @llvm_mips_sra_h_test() nounwind {
274 %0 = load <8 x i16>* @llvm_mips_sra_h_ARG1
275 %1 = load <8 x i16>* @llvm_mips_sra_h_ARG2
276 %2 = tail call <8 x i16> @llvm.mips.sra.h(<8 x i16> %0, <8 x i16> %1)
277 store <8 x i16> %2, <8 x i16>* @llvm_mips_sra_h_RES
281 declare <8 x i16> @llvm.mips.sra.h(<8 x i16>, <8 x i16>) nounwind
283 ; CHECK: llvm_mips_sra_h_test:
288 ; CHECK: .size llvm_mips_sra_h_test
290 @llvm_mips_sra_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16
291 @llvm_mips_sra_w_ARG2 = global <4 x i32> <i32 4, i32 5, i32 6, i32 7>, align 16
292 @llvm_mips_sra_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16
294 define void @llvm_mips_sra_w_test() nounwind {
296 %0 = load <4 x i32>* @llvm_mips_sra_w_ARG1
297 %1 = load <4 x i32>* @llvm_mips_sra_w_ARG2
298 %2 = tail call <4 x i32> @llvm.mips.sra.w(<4 x i32> %0, <4 x i32> %1)
299 store <4 x i32> %2, <4 x i32>* @llvm_mips_sra_w_RES
303 declare <4 x i32> @llvm.mips.sra.w(<4 x i32>, <4 x i32>) nounwind
305 ; CHECK: llvm_mips_sra_w_test:
310 ; CHECK: .size llvm_mips_sra_w_test
312 @llvm_mips_sra_d_ARG1 = global <2 x i64> <i64 0, i64 1>, align 16
313 @llvm_mips_sra_d_ARG2 = global <2 x i64> <i64 2, i64 3>, align 16
314 @llvm_mips_sra_d_RES = global <2 x i64> <i64 0, i64 0>, align 16
316 define void @llvm_mips_sra_d_test() nounwind {
318 %0 = load <2 x i64>* @llvm_mips_sra_d_ARG1
319 %1 = load <2 x i64>* @llvm_mips_sra_d_ARG2
320 %2 = tail call <2 x i64> @llvm.mips.sra.d(<2 x i64> %0, <2 x i64> %1)
321 store <2 x i64> %2, <2 x i64>* @llvm_mips_sra_d_RES
325 declare <2 x i64> @llvm.mips.sra.d(<2 x i64>, <2 x i64>) nounwind
327 ; CHECK: llvm_mips_sra_d_test:
332 ; CHECK: .size llvm_mips_sra_d_test
335 define void @sra_b_test() nounwind {
337 %0 = load <16 x i8>* @llvm_mips_sra_b_ARG1
338 %1 = load <16 x i8>* @llvm_mips_sra_b_ARG2
339 %2 = ashr <16 x i8> %0, %1
340 store <16 x i8> %2, <16 x i8>* @llvm_mips_sra_b_RES
349 ; CHECK: .size sra_b_test
351 define void @sra_h_test() nounwind {
353 %0 = load <8 x i16>* @llvm_mips_sra_h_ARG1
354 %1 = load <8 x i16>* @llvm_mips_sra_h_ARG2
355 %2 = ashr <8 x i16> %0, %1
356 store <8 x i16> %2, <8 x i16>* @llvm_mips_sra_h_RES
365 ; CHECK: .size sra_h_test
367 define void @sra_w_test() nounwind {
369 %0 = load <4 x i32>* @llvm_mips_sra_w_ARG1
370 %1 = load <4 x i32>* @llvm_mips_sra_w_ARG2
371 %2 = ashr <4 x i32> %0, %1
372 store <4 x i32> %2, <4 x i32>* @llvm_mips_sra_w_RES
381 ; CHECK: .size sra_w_test
383 define void @sra_d_test() nounwind {
385 %0 = load <2 x i64>* @llvm_mips_sra_d_ARG1
386 %1 = load <2 x i64>* @llvm_mips_sra_d_ARG2
387 %2 = ashr <2 x i64> %0, %1
388 store <2 x i64> %2, <2 x i64>* @llvm_mips_sra_d_RES
397 ; CHECK: .size sra_d_test
399 @llvm_mips_srar_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
400 @llvm_mips_srar_b_ARG2 = global <16 x i8> <i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23, i8 24, i8 25, i8 26, i8 27, i8 28, i8 29, i8 30, i8 31>, align 16
401 @llvm_mips_srar_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16
403 define void @llvm_mips_srar_b_test() nounwind {
405 %0 = load <16 x i8>* @llvm_mips_srar_b_ARG1
406 %1 = load <16 x i8>* @llvm_mips_srar_b_ARG2
407 %2 = tail call <16 x i8> @llvm.mips.srar.b(<16 x i8> %0, <16 x i8> %1)
408 store <16 x i8> %2, <16 x i8>* @llvm_mips_srar_b_RES
412 declare <16 x i8> @llvm.mips.srar.b(<16 x i8>, <16 x i8>) nounwind
414 ; CHECK: llvm_mips_srar_b_test:
419 ; CHECK: .size llvm_mips_srar_b_test
421 @llvm_mips_srar_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16
422 @llvm_mips_srar_h_ARG2 = global <8 x i16> <i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15>, align 16
423 @llvm_mips_srar_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16
425 define void @llvm_mips_srar_h_test() nounwind {
427 %0 = load <8 x i16>* @llvm_mips_srar_h_ARG1
428 %1 = load <8 x i16>* @llvm_mips_srar_h_ARG2
429 %2 = tail call <8 x i16> @llvm.mips.srar.h(<8 x i16> %0, <8 x i16> %1)
430 store <8 x i16> %2, <8 x i16>* @llvm_mips_srar_h_RES
434 declare <8 x i16> @llvm.mips.srar.h(<8 x i16>, <8 x i16>) nounwind
436 ; CHECK: llvm_mips_srar_h_test:
441 ; CHECK: .size llvm_mips_srar_h_test
443 @llvm_mips_srar_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16
444 @llvm_mips_srar_w_ARG2 = global <4 x i32> <i32 4, i32 5, i32 6, i32 7>, align 16
445 @llvm_mips_srar_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16
447 define void @llvm_mips_srar_w_test() nounwind {
449 %0 = load <4 x i32>* @llvm_mips_srar_w_ARG1
450 %1 = load <4 x i32>* @llvm_mips_srar_w_ARG2
451 %2 = tail call <4 x i32> @llvm.mips.srar.w(<4 x i32> %0, <4 x i32> %1)
452 store <4 x i32> %2, <4 x i32>* @llvm_mips_srar_w_RES
456 declare <4 x i32> @llvm.mips.srar.w(<4 x i32>, <4 x i32>) nounwind
458 ; CHECK: llvm_mips_srar_w_test:
463 ; CHECK: .size llvm_mips_srar_w_test
465 @llvm_mips_srar_d_ARG1 = global <2 x i64> <i64 0, i64 1>, align 16
466 @llvm_mips_srar_d_ARG2 = global <2 x i64> <i64 2, i64 3>, align 16
467 @llvm_mips_srar_d_RES = global <2 x i64> <i64 0, i64 0>, align 16
469 define void @llvm_mips_srar_d_test() nounwind {
471 %0 = load <2 x i64>* @llvm_mips_srar_d_ARG1
472 %1 = load <2 x i64>* @llvm_mips_srar_d_ARG2
473 %2 = tail call <2 x i64> @llvm.mips.srar.d(<2 x i64> %0, <2 x i64> %1)
474 store <2 x i64> %2, <2 x i64>* @llvm_mips_srar_d_RES
478 declare <2 x i64> @llvm.mips.srar.d(<2 x i64>, <2 x i64>) nounwind
480 ; CHECK: llvm_mips_srar_d_test:
485 ; CHECK: .size llvm_mips_srar_d_test
487 @llvm_mips_srl_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
488 @llvm_mips_srl_b_ARG2 = global <16 x i8> <i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23, i8 24, i8 25, i8 26, i8 27, i8 28, i8 29, i8 30, i8 31>, align 16
489 @llvm_mips_srl_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16
491 define void @llvm_mips_srl_b_test() nounwind {
493 %0 = load <16 x i8>* @llvm_mips_srl_b_ARG1
494 %1 = load <16 x i8>* @llvm_mips_srl_b_ARG2
495 %2 = tail call <16 x i8> @llvm.mips.srl.b(<16 x i8> %0, <16 x i8> %1)
496 store <16 x i8> %2, <16 x i8>* @llvm_mips_srl_b_RES
500 declare <16 x i8> @llvm.mips.srl.b(<16 x i8>, <16 x i8>) nounwind
502 ; CHECK: llvm_mips_srl_b_test:
507 ; CHECK: .size llvm_mips_srl_b_test
509 @llvm_mips_srl_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16
510 @llvm_mips_srl_h_ARG2 = global <8 x i16> <i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15>, align 16
511 @llvm_mips_srl_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16
513 define void @llvm_mips_srl_h_test() nounwind {
515 %0 = load <8 x i16>* @llvm_mips_srl_h_ARG1
516 %1 = load <8 x i16>* @llvm_mips_srl_h_ARG2
517 %2 = tail call <8 x i16> @llvm.mips.srl.h(<8 x i16> %0, <8 x i16> %1)
518 store <8 x i16> %2, <8 x i16>* @llvm_mips_srl_h_RES
522 declare <8 x i16> @llvm.mips.srl.h(<8 x i16>, <8 x i16>) nounwind
524 ; CHECK: llvm_mips_srl_h_test:
529 ; CHECK: .size llvm_mips_srl_h_test
531 @llvm_mips_srl_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16
532 @llvm_mips_srl_w_ARG2 = global <4 x i32> <i32 4, i32 5, i32 6, i32 7>, align 16
533 @llvm_mips_srl_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16
535 define void @llvm_mips_srl_w_test() nounwind {
537 %0 = load <4 x i32>* @llvm_mips_srl_w_ARG1
538 %1 = load <4 x i32>* @llvm_mips_srl_w_ARG2
539 %2 = tail call <4 x i32> @llvm.mips.srl.w(<4 x i32> %0, <4 x i32> %1)
540 store <4 x i32> %2, <4 x i32>* @llvm_mips_srl_w_RES
544 declare <4 x i32> @llvm.mips.srl.w(<4 x i32>, <4 x i32>) nounwind
546 ; CHECK: llvm_mips_srl_w_test:
551 ; CHECK: .size llvm_mips_srl_w_test
553 @llvm_mips_srl_d_ARG1 = global <2 x i64> <i64 0, i64 1>, align 16
554 @llvm_mips_srl_d_ARG2 = global <2 x i64> <i64 2, i64 3>, align 16
555 @llvm_mips_srl_d_RES = global <2 x i64> <i64 0, i64 0>, align 16
557 define void @llvm_mips_srl_d_test() nounwind {
559 %0 = load <2 x i64>* @llvm_mips_srl_d_ARG1
560 %1 = load <2 x i64>* @llvm_mips_srl_d_ARG2
561 %2 = tail call <2 x i64> @llvm.mips.srl.d(<2 x i64> %0, <2 x i64> %1)
562 store <2 x i64> %2, <2 x i64>* @llvm_mips_srl_d_RES
566 declare <2 x i64> @llvm.mips.srl.d(<2 x i64>, <2 x i64>) nounwind
568 ; CHECK: llvm_mips_srl_d_test:
573 ; CHECK: .size llvm_mips_srl_d_test
575 @llvm_mips_srlr_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
576 @llvm_mips_srlr_b_ARG2 = global <16 x i8> <i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23, i8 24, i8 25, i8 26, i8 27, i8 28, i8 29, i8 30, i8 31>, align 16
577 @llvm_mips_srlr_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16
579 define void @llvm_mips_srlr_b_test() nounwind {
581 %0 = load <16 x i8>* @llvm_mips_srlr_b_ARG1
582 %1 = load <16 x i8>* @llvm_mips_srlr_b_ARG2
583 %2 = tail call <16 x i8> @llvm.mips.srlr.b(<16 x i8> %0, <16 x i8> %1)
584 store <16 x i8> %2, <16 x i8>* @llvm_mips_srlr_b_RES
588 declare <16 x i8> @llvm.mips.srlr.b(<16 x i8>, <16 x i8>) nounwind
590 ; CHECK: llvm_mips_srlr_b_test:
595 ; CHECK: .size llvm_mips_srlr_b_test
597 @llvm_mips_srlr_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16
598 @llvm_mips_srlr_h_ARG2 = global <8 x i16> <i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15>, align 16
599 @llvm_mips_srlr_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16
601 define void @llvm_mips_srlr_h_test() nounwind {
603 %0 = load <8 x i16>* @llvm_mips_srlr_h_ARG1
604 %1 = load <8 x i16>* @llvm_mips_srlr_h_ARG2
605 %2 = tail call <8 x i16> @llvm.mips.srlr.h(<8 x i16> %0, <8 x i16> %1)
606 store <8 x i16> %2, <8 x i16>* @llvm_mips_srlr_h_RES
610 declare <8 x i16> @llvm.mips.srlr.h(<8 x i16>, <8 x i16>) nounwind
612 ; CHECK: llvm_mips_srlr_h_test:
617 ; CHECK: .size llvm_mips_srlr_h_test
619 @llvm_mips_srlr_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16
620 @llvm_mips_srlr_w_ARG2 = global <4 x i32> <i32 4, i32 5, i32 6, i32 7>, align 16
621 @llvm_mips_srlr_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16
623 define void @llvm_mips_srlr_w_test() nounwind {
625 %0 = load <4 x i32>* @llvm_mips_srlr_w_ARG1
626 %1 = load <4 x i32>* @llvm_mips_srlr_w_ARG2
627 %2 = tail call <4 x i32> @llvm.mips.srlr.w(<4 x i32> %0, <4 x i32> %1)
628 store <4 x i32> %2, <4 x i32>* @llvm_mips_srlr_w_RES
632 declare <4 x i32> @llvm.mips.srlr.w(<4 x i32>, <4 x i32>) nounwind
634 ; CHECK: llvm_mips_srlr_w_test:
639 ; CHECK: .size llvm_mips_srlr_w_test
641 @llvm_mips_srlr_d_ARG1 = global <2 x i64> <i64 0, i64 1>, align 16
642 @llvm_mips_srlr_d_ARG2 = global <2 x i64> <i64 2, i64 3>, align 16
643 @llvm_mips_srlr_d_RES = global <2 x i64> <i64 0, i64 0>, align 16
645 define void @llvm_mips_srlr_d_test() nounwind {
647 %0 = load <2 x i64>* @llvm_mips_srlr_d_ARG1
648 %1 = load <2 x i64>* @llvm_mips_srlr_d_ARG2
649 %2 = tail call <2 x i64> @llvm.mips.srlr.d(<2 x i64> %0, <2 x i64> %1)
650 store <2 x i64> %2, <2 x i64>* @llvm_mips_srlr_d_RES
654 declare <2 x i64> @llvm.mips.srlr.d(<2 x i64>, <2 x i64>) nounwind
656 ; CHECK: llvm_mips_srlr_d_test:
661 ; CHECK: .size llvm_mips_srlr_d_test
664 define void @srl_b_test() nounwind {
666 %0 = load <16 x i8>* @llvm_mips_srl_b_ARG1
667 %1 = load <16 x i8>* @llvm_mips_srl_b_ARG2
668 %2 = lshr <16 x i8> %0, %1
669 store <16 x i8> %2, <16 x i8>* @llvm_mips_srl_b_RES
678 ; CHECK: .size srl_b_test
680 define void @srl_h_test() nounwind {
682 %0 = load <8 x i16>* @llvm_mips_srl_h_ARG1
683 %1 = load <8 x i16>* @llvm_mips_srl_h_ARG2
684 %2 = lshr <8 x i16> %0, %1
685 store <8 x i16> %2, <8 x i16>* @llvm_mips_srl_h_RES
694 ; CHECK: .size srl_h_test
696 define void @srl_w_test() nounwind {
698 %0 = load <4 x i32>* @llvm_mips_srl_w_ARG1
699 %1 = load <4 x i32>* @llvm_mips_srl_w_ARG2
700 %2 = lshr <4 x i32> %0, %1
701 store <4 x i32> %2, <4 x i32>* @llvm_mips_srl_w_RES
710 ; CHECK: .size srl_w_test
712 define void @srl_d_test() nounwind {
714 %0 = load <2 x i64>* @llvm_mips_srl_d_ARG1
715 %1 = load <2 x i64>* @llvm_mips_srl_d_ARG2
716 %2 = lshr <2 x i64> %0, %1
717 store <2 x i64> %2, <2 x i64>* @llvm_mips_srl_d_RES
726 ; CHECK: .size srl_d_test
728 @llvm_mips_subs_s_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
729 @llvm_mips_subs_s_b_ARG2 = global <16 x i8> <i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23, i8 24, i8 25, i8 26, i8 27, i8 28, i8 29, i8 30, i8 31>, align 16
730 @llvm_mips_subs_s_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16
732 define void @llvm_mips_subs_s_b_test() nounwind {
734 %0 = load <16 x i8>* @llvm_mips_subs_s_b_ARG1
735 %1 = load <16 x i8>* @llvm_mips_subs_s_b_ARG2
736 %2 = tail call <16 x i8> @llvm.mips.subs.s.b(<16 x i8> %0, <16 x i8> %1)
737 store <16 x i8> %2, <16 x i8>* @llvm_mips_subs_s_b_RES
741 declare <16 x i8> @llvm.mips.subs.s.b(<16 x i8>, <16 x i8>) nounwind
743 ; CHECK: llvm_mips_subs_s_b_test:
748 ; CHECK: .size llvm_mips_subs_s_b_test
750 @llvm_mips_subs_s_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16
751 @llvm_mips_subs_s_h_ARG2 = global <8 x i16> <i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15>, align 16
752 @llvm_mips_subs_s_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16
754 define void @llvm_mips_subs_s_h_test() nounwind {
756 %0 = load <8 x i16>* @llvm_mips_subs_s_h_ARG1
757 %1 = load <8 x i16>* @llvm_mips_subs_s_h_ARG2
758 %2 = tail call <8 x i16> @llvm.mips.subs.s.h(<8 x i16> %0, <8 x i16> %1)
759 store <8 x i16> %2, <8 x i16>* @llvm_mips_subs_s_h_RES
763 declare <8 x i16> @llvm.mips.subs.s.h(<8 x i16>, <8 x i16>) nounwind
765 ; CHECK: llvm_mips_subs_s_h_test:
770 ; CHECK: .size llvm_mips_subs_s_h_test
772 @llvm_mips_subs_s_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16
773 @llvm_mips_subs_s_w_ARG2 = global <4 x i32> <i32 4, i32 5, i32 6, i32 7>, align 16
774 @llvm_mips_subs_s_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16
776 define void @llvm_mips_subs_s_w_test() nounwind {
778 %0 = load <4 x i32>* @llvm_mips_subs_s_w_ARG1
779 %1 = load <4 x i32>* @llvm_mips_subs_s_w_ARG2
780 %2 = tail call <4 x i32> @llvm.mips.subs.s.w(<4 x i32> %0, <4 x i32> %1)
781 store <4 x i32> %2, <4 x i32>* @llvm_mips_subs_s_w_RES
785 declare <4 x i32> @llvm.mips.subs.s.w(<4 x i32>, <4 x i32>) nounwind
787 ; CHECK: llvm_mips_subs_s_w_test:
792 ; CHECK: .size llvm_mips_subs_s_w_test
794 @llvm_mips_subs_s_d_ARG1 = global <2 x i64> <i64 0, i64 1>, align 16
795 @llvm_mips_subs_s_d_ARG2 = global <2 x i64> <i64 2, i64 3>, align 16
796 @llvm_mips_subs_s_d_RES = global <2 x i64> <i64 0, i64 0>, align 16
798 define void @llvm_mips_subs_s_d_test() nounwind {
800 %0 = load <2 x i64>* @llvm_mips_subs_s_d_ARG1
801 %1 = load <2 x i64>* @llvm_mips_subs_s_d_ARG2
802 %2 = tail call <2 x i64> @llvm.mips.subs.s.d(<2 x i64> %0, <2 x i64> %1)
803 store <2 x i64> %2, <2 x i64>* @llvm_mips_subs_s_d_RES
807 declare <2 x i64> @llvm.mips.subs.s.d(<2 x i64>, <2 x i64>) nounwind
809 ; CHECK: llvm_mips_subs_s_d_test:
814 ; CHECK: .size llvm_mips_subs_s_d_test
816 @llvm_mips_subs_u_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
817 @llvm_mips_subs_u_b_ARG2 = global <16 x i8> <i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23, i8 24, i8 25, i8 26, i8 27, i8 28, i8 29, i8 30, i8 31>, align 16
818 @llvm_mips_subs_u_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16
820 define void @llvm_mips_subs_u_b_test() nounwind {
822 %0 = load <16 x i8>* @llvm_mips_subs_u_b_ARG1
823 %1 = load <16 x i8>* @llvm_mips_subs_u_b_ARG2
824 %2 = tail call <16 x i8> @llvm.mips.subs.u.b(<16 x i8> %0, <16 x i8> %1)
825 store <16 x i8> %2, <16 x i8>* @llvm_mips_subs_u_b_RES
829 declare <16 x i8> @llvm.mips.subs.u.b(<16 x i8>, <16 x i8>) nounwind
831 ; CHECK: llvm_mips_subs_u_b_test:
836 ; CHECK: .size llvm_mips_subs_u_b_test
838 @llvm_mips_subs_u_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16
839 @llvm_mips_subs_u_h_ARG2 = global <8 x i16> <i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15>, align 16
840 @llvm_mips_subs_u_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16
842 define void @llvm_mips_subs_u_h_test() nounwind {
844 %0 = load <8 x i16>* @llvm_mips_subs_u_h_ARG1
845 %1 = load <8 x i16>* @llvm_mips_subs_u_h_ARG2
846 %2 = tail call <8 x i16> @llvm.mips.subs.u.h(<8 x i16> %0, <8 x i16> %1)
847 store <8 x i16> %2, <8 x i16>* @llvm_mips_subs_u_h_RES
851 declare <8 x i16> @llvm.mips.subs.u.h(<8 x i16>, <8 x i16>) nounwind
853 ; CHECK: llvm_mips_subs_u_h_test:
858 ; CHECK: .size llvm_mips_subs_u_h_test
860 @llvm_mips_subs_u_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16
861 @llvm_mips_subs_u_w_ARG2 = global <4 x i32> <i32 4, i32 5, i32 6, i32 7>, align 16
862 @llvm_mips_subs_u_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16
864 define void @llvm_mips_subs_u_w_test() nounwind {
866 %0 = load <4 x i32>* @llvm_mips_subs_u_w_ARG1
867 %1 = load <4 x i32>* @llvm_mips_subs_u_w_ARG2
868 %2 = tail call <4 x i32> @llvm.mips.subs.u.w(<4 x i32> %0, <4 x i32> %1)
869 store <4 x i32> %2, <4 x i32>* @llvm_mips_subs_u_w_RES
873 declare <4 x i32> @llvm.mips.subs.u.w(<4 x i32>, <4 x i32>) nounwind
875 ; CHECK: llvm_mips_subs_u_w_test:
880 ; CHECK: .size llvm_mips_subs_u_w_test
882 @llvm_mips_subs_u_d_ARG1 = global <2 x i64> <i64 0, i64 1>, align 16
883 @llvm_mips_subs_u_d_ARG2 = global <2 x i64> <i64 2, i64 3>, align 16
884 @llvm_mips_subs_u_d_RES = global <2 x i64> <i64 0, i64 0>, align 16
886 define void @llvm_mips_subs_u_d_test() nounwind {
888 %0 = load <2 x i64>* @llvm_mips_subs_u_d_ARG1
889 %1 = load <2 x i64>* @llvm_mips_subs_u_d_ARG2
890 %2 = tail call <2 x i64> @llvm.mips.subs.u.d(<2 x i64> %0, <2 x i64> %1)
891 store <2 x i64> %2, <2 x i64>* @llvm_mips_subs_u_d_RES
895 declare <2 x i64> @llvm.mips.subs.u.d(<2 x i64>, <2 x i64>) nounwind
897 ; CHECK: llvm_mips_subs_u_d_test:
902 ; CHECK: .size llvm_mips_subs_u_d_test
904 @llvm_mips_subsus_u_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
905 @llvm_mips_subsus_u_b_ARG2 = global <16 x i8> <i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23, i8 24, i8 25, i8 26, i8 27, i8 28, i8 29, i8 30, i8 31>, align 16
906 @llvm_mips_subsus_u_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16
908 define void @llvm_mips_subsus_u_b_test() nounwind {
910 %0 = load <16 x i8>* @llvm_mips_subsus_u_b_ARG1
911 %1 = load <16 x i8>* @llvm_mips_subsus_u_b_ARG2
912 %2 = tail call <16 x i8> @llvm.mips.subsus.u.b(<16 x i8> %0, <16 x i8> %1)
913 store <16 x i8> %2, <16 x i8>* @llvm_mips_subsus_u_b_RES
917 declare <16 x i8> @llvm.mips.subsus.u.b(<16 x i8>, <16 x i8>) nounwind
919 ; CHECK: llvm_mips_subsus_u_b_test:
924 ; CHECK: .size llvm_mips_subsus_u_b_test
926 @llvm_mips_subsus_u_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16
927 @llvm_mips_subsus_u_h_ARG2 = global <8 x i16> <i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15>, align 16
928 @llvm_mips_subsus_u_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16
930 define void @llvm_mips_subsus_u_h_test() nounwind {
932 %0 = load <8 x i16>* @llvm_mips_subsus_u_h_ARG1
933 %1 = load <8 x i16>* @llvm_mips_subsus_u_h_ARG2
934 %2 = tail call <8 x i16> @llvm.mips.subsus.u.h(<8 x i16> %0, <8 x i16> %1)
935 store <8 x i16> %2, <8 x i16>* @llvm_mips_subsus_u_h_RES
939 declare <8 x i16> @llvm.mips.subsus.u.h(<8 x i16>, <8 x i16>) nounwind
941 ; CHECK: llvm_mips_subsus_u_h_test:
946 ; CHECK: .size llvm_mips_subsus_u_h_test
948 @llvm_mips_subsus_u_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16
949 @llvm_mips_subsus_u_w_ARG2 = global <4 x i32> <i32 4, i32 5, i32 6, i32 7>, align 16
950 @llvm_mips_subsus_u_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16
952 define void @llvm_mips_subsus_u_w_test() nounwind {
954 %0 = load <4 x i32>* @llvm_mips_subsus_u_w_ARG1
955 %1 = load <4 x i32>* @llvm_mips_subsus_u_w_ARG2
956 %2 = tail call <4 x i32> @llvm.mips.subsus.u.w(<4 x i32> %0, <4 x i32> %1)
957 store <4 x i32> %2, <4 x i32>* @llvm_mips_subsus_u_w_RES
961 declare <4 x i32> @llvm.mips.subsus.u.w(<4 x i32>, <4 x i32>) nounwind
963 ; CHECK: llvm_mips_subsus_u_w_test:
968 ; CHECK: .size llvm_mips_subsus_u_w_test
970 @llvm_mips_subsus_u_d_ARG1 = global <2 x i64> <i64 0, i64 1>, align 16
971 @llvm_mips_subsus_u_d_ARG2 = global <2 x i64> <i64 2, i64 3>, align 16
972 @llvm_mips_subsus_u_d_RES = global <2 x i64> <i64 0, i64 0>, align 16
974 define void @llvm_mips_subsus_u_d_test() nounwind {
976 %0 = load <2 x i64>* @llvm_mips_subsus_u_d_ARG1
977 %1 = load <2 x i64>* @llvm_mips_subsus_u_d_ARG2
978 %2 = tail call <2 x i64> @llvm.mips.subsus.u.d(<2 x i64> %0, <2 x i64> %1)
979 store <2 x i64> %2, <2 x i64>* @llvm_mips_subsus_u_d_RES
983 declare <2 x i64> @llvm.mips.subsus.u.d(<2 x i64>, <2 x i64>) nounwind
985 ; CHECK: llvm_mips_subsus_u_d_test:
990 ; CHECK: .size llvm_mips_subsus_u_d_test
992 @llvm_mips_subsuu_s_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
993 @llvm_mips_subsuu_s_b_ARG2 = global <16 x i8> <i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23, i8 24, i8 25, i8 26, i8 27, i8 28, i8 29, i8 30, i8 31>, align 16
994 @llvm_mips_subsuu_s_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16
996 define void @llvm_mips_subsuu_s_b_test() nounwind {
998 %0 = load <16 x i8>* @llvm_mips_subsuu_s_b_ARG1
999 %1 = load <16 x i8>* @llvm_mips_subsuu_s_b_ARG2
1000 %2 = tail call <16 x i8> @llvm.mips.subsuu.s.b(<16 x i8> %0, <16 x i8> %1)
1001 store <16 x i8> %2, <16 x i8>* @llvm_mips_subsuu_s_b_RES
1005 declare <16 x i8> @llvm.mips.subsuu.s.b(<16 x i8>, <16 x i8>) nounwind
1007 ; CHECK: llvm_mips_subsuu_s_b_test:
1012 ; CHECK: .size llvm_mips_subsuu_s_b_test
1014 @llvm_mips_subsuu_s_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16
1015 @llvm_mips_subsuu_s_h_ARG2 = global <8 x i16> <i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15>, align 16
1016 @llvm_mips_subsuu_s_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16
1018 define void @llvm_mips_subsuu_s_h_test() nounwind {
1020 %0 = load <8 x i16>* @llvm_mips_subsuu_s_h_ARG1
1021 %1 = load <8 x i16>* @llvm_mips_subsuu_s_h_ARG2
1022 %2 = tail call <8 x i16> @llvm.mips.subsuu.s.h(<8 x i16> %0, <8 x i16> %1)
1023 store <8 x i16> %2, <8 x i16>* @llvm_mips_subsuu_s_h_RES
1027 declare <8 x i16> @llvm.mips.subsuu.s.h(<8 x i16>, <8 x i16>) nounwind
1029 ; CHECK: llvm_mips_subsuu_s_h_test:
1034 ; CHECK: .size llvm_mips_subsuu_s_h_test
1036 @llvm_mips_subsuu_s_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16
1037 @llvm_mips_subsuu_s_w_ARG2 = global <4 x i32> <i32 4, i32 5, i32 6, i32 7>, align 16
1038 @llvm_mips_subsuu_s_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16
1040 define void @llvm_mips_subsuu_s_w_test() nounwind {
1042 %0 = load <4 x i32>* @llvm_mips_subsuu_s_w_ARG1
1043 %1 = load <4 x i32>* @llvm_mips_subsuu_s_w_ARG2
1044 %2 = tail call <4 x i32> @llvm.mips.subsuu.s.w(<4 x i32> %0, <4 x i32> %1)
1045 store <4 x i32> %2, <4 x i32>* @llvm_mips_subsuu_s_w_RES
1049 declare <4 x i32> @llvm.mips.subsuu.s.w(<4 x i32>, <4 x i32>) nounwind
1051 ; CHECK: llvm_mips_subsuu_s_w_test:
1056 ; CHECK: .size llvm_mips_subsuu_s_w_test
1058 @llvm_mips_subsuu_s_d_ARG1 = global <2 x i64> <i64 0, i64 1>, align 16
1059 @llvm_mips_subsuu_s_d_ARG2 = global <2 x i64> <i64 2, i64 3>, align 16
1060 @llvm_mips_subsuu_s_d_RES = global <2 x i64> <i64 0, i64 0>, align 16
1062 define void @llvm_mips_subsuu_s_d_test() nounwind {
1064 %0 = load <2 x i64>* @llvm_mips_subsuu_s_d_ARG1
1065 %1 = load <2 x i64>* @llvm_mips_subsuu_s_d_ARG2
1066 %2 = tail call <2 x i64> @llvm.mips.subsuu.s.d(<2 x i64> %0, <2 x i64> %1)
1067 store <2 x i64> %2, <2 x i64>* @llvm_mips_subsuu_s_d_RES
1071 declare <2 x i64> @llvm.mips.subsuu.s.d(<2 x i64>, <2 x i64>) nounwind
1073 ; CHECK: llvm_mips_subsuu_s_d_test:
1078 ; CHECK: .size llvm_mips_subsuu_s_d_test
1080 @llvm_mips_subv_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
1081 @llvm_mips_subv_b_ARG2 = global <16 x i8> <i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23, i8 24, i8 25, i8 26, i8 27, i8 28, i8 29, i8 30, i8 31>, align 16
1082 @llvm_mips_subv_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16
1084 define void @llvm_mips_subv_b_test() nounwind {
1086 %0 = load <16 x i8>* @llvm_mips_subv_b_ARG1
1087 %1 = load <16 x i8>* @llvm_mips_subv_b_ARG2
1088 %2 = tail call <16 x i8> @llvm.mips.subv.b(<16 x i8> %0, <16 x i8> %1)
1089 store <16 x i8> %2, <16 x i8>* @llvm_mips_subv_b_RES
1093 declare <16 x i8> @llvm.mips.subv.b(<16 x i8>, <16 x i8>) nounwind
1095 ; CHECK: llvm_mips_subv_b_test:
1100 ; CHECK: .size llvm_mips_subv_b_test
1102 @llvm_mips_subv_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16
1103 @llvm_mips_subv_h_ARG2 = global <8 x i16> <i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15>, align 16
1104 @llvm_mips_subv_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16
1106 define void @llvm_mips_subv_h_test() nounwind {
1108 %0 = load <8 x i16>* @llvm_mips_subv_h_ARG1
1109 %1 = load <8 x i16>* @llvm_mips_subv_h_ARG2
1110 %2 = tail call <8 x i16> @llvm.mips.subv.h(<8 x i16> %0, <8 x i16> %1)
1111 store <8 x i16> %2, <8 x i16>* @llvm_mips_subv_h_RES
1115 declare <8 x i16> @llvm.mips.subv.h(<8 x i16>, <8 x i16>) nounwind
1117 ; CHECK: llvm_mips_subv_h_test:
1122 ; CHECK: .size llvm_mips_subv_h_test
1124 @llvm_mips_subv_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16
1125 @llvm_mips_subv_w_ARG2 = global <4 x i32> <i32 4, i32 5, i32 6, i32 7>, align 16
1126 @llvm_mips_subv_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16
1128 define void @llvm_mips_subv_w_test() nounwind {
1130 %0 = load <4 x i32>* @llvm_mips_subv_w_ARG1
1131 %1 = load <4 x i32>* @llvm_mips_subv_w_ARG2
1132 %2 = tail call <4 x i32> @llvm.mips.subv.w(<4 x i32> %0, <4 x i32> %1)
1133 store <4 x i32> %2, <4 x i32>* @llvm_mips_subv_w_RES
1137 declare <4 x i32> @llvm.mips.subv.w(<4 x i32>, <4 x i32>) nounwind
1139 ; CHECK: llvm_mips_subv_w_test:
1144 ; CHECK: .size llvm_mips_subv_w_test
1146 @llvm_mips_subv_d_ARG1 = global <2 x i64> <i64 0, i64 1>, align 16
1147 @llvm_mips_subv_d_ARG2 = global <2 x i64> <i64 2, i64 3>, align 16
1148 @llvm_mips_subv_d_RES = global <2 x i64> <i64 0, i64 0>, align 16
1150 define void @llvm_mips_subv_d_test() nounwind {
1152 %0 = load <2 x i64>* @llvm_mips_subv_d_ARG1
1153 %1 = load <2 x i64>* @llvm_mips_subv_d_ARG2
1154 %2 = tail call <2 x i64> @llvm.mips.subv.d(<2 x i64> %0, <2 x i64> %1)
1155 store <2 x i64> %2, <2 x i64>* @llvm_mips_subv_d_RES
1159 declare <2 x i64> @llvm.mips.subv.d(<2 x i64>, <2 x i64>) nounwind
1161 ; CHECK: llvm_mips_subv_d_test:
1166 ; CHECK: .size llvm_mips_subv_d_test
1169 define void @subv_b_test() nounwind {
1171 %0 = load <16 x i8>* @llvm_mips_subv_b_ARG1
1172 %1 = load <16 x i8>* @llvm_mips_subv_b_ARG2
1173 %2 = sub <16 x i8> %0, %1
1174 store <16 x i8> %2, <16 x i8>* @llvm_mips_subv_b_RES
1178 ; CHECK: subv_b_test:
1183 ; CHECK: .size subv_b_test
1185 define void @subv_h_test() nounwind {
1187 %0 = load <8 x i16>* @llvm_mips_subv_h_ARG1
1188 %1 = load <8 x i16>* @llvm_mips_subv_h_ARG2
1189 %2 = sub <8 x i16> %0, %1
1190 store <8 x i16> %2, <8 x i16>* @llvm_mips_subv_h_RES
1194 ; CHECK: subv_h_test:
1199 ; CHECK: .size subv_h_test
1201 define void @subv_w_test() nounwind {
1203 %0 = load <4 x i32>* @llvm_mips_subv_w_ARG1
1204 %1 = load <4 x i32>* @llvm_mips_subv_w_ARG2
1205 %2 = sub <4 x i32> %0, %1
1206 store <4 x i32> %2, <4 x i32>* @llvm_mips_subv_w_RES
1210 ; CHECK: subv_w_test:
1215 ; CHECK: .size subv_w_test
1217 define void @subv_d_test() nounwind {
1219 %0 = load <2 x i64>* @llvm_mips_subv_d_ARG1
1220 %1 = load <2 x i64>* @llvm_mips_subv_d_ARG2
1221 %2 = sub <2 x i64> %0, %1
1222 store <2 x i64> %2, <2 x i64>* @llvm_mips_subv_d_RES
1226 ; CHECK: subv_d_test:
1231 ; CHECK: .size subv_d_test