1 ; Test the MSA intrinsics that are encoded with the 3R instruction format and
2 ; use the result as a third operand and results in wider elements than the
5 ; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s
7 @llvm_mips_dpadd_s_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16
8 @llvm_mips_dpadd_s_h_ARG2 = global <16 x i8> <i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15, i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23>, align 16
9 @llvm_mips_dpadd_s_h_ARG3 = global <16 x i8> <i8 24, i8 25, i8 26, i8 27, i8 28, i8 29, i8 30, i8 31, i8 32, i8 33, i8 34, i8 35, i8 36, i8 37, i8 38, i8 39>, align 16
10 @llvm_mips_dpadd_s_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16
12 define void @llvm_mips_dpadd_s_h_test() nounwind {
14 %0 = load <8 x i16>* @llvm_mips_dpadd_s_h_ARG1
15 %1 = load <16 x i8>* @llvm_mips_dpadd_s_h_ARG2
16 %2 = load <16 x i8>* @llvm_mips_dpadd_s_h_ARG3
17 %3 = tail call <8 x i16> @llvm.mips.dpadd.s.h(<8 x i16> %0, <16 x i8> %1, <16 x i8> %2)
18 store <8 x i16> %3, <8 x i16>* @llvm_mips_dpadd_s_h_RES
22 declare <8 x i16> @llvm.mips.dpadd.s.h(<8 x i16>, <16 x i8>, <16 x i8>) nounwind
24 ; CHECK: llvm_mips_dpadd_s_h_test:
30 ; CHECK: .size llvm_mips_dpadd_s_h_test
32 @llvm_mips_dpadd_s_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16
33 @llvm_mips_dpadd_s_w_ARG2 = global <8 x i16> <i16 4, i16 5, i16 6, i16 7, i16 8, i16 9, i16 10, i16 11>, align 16
34 @llvm_mips_dpadd_s_w_ARG3 = global <8 x i16> <i16 12, i16 13, i16 14, i16 15, i16 16, i16 17, i16 18, i16 19>, align 16
35 @llvm_mips_dpadd_s_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16
37 define void @llvm_mips_dpadd_s_w_test() nounwind {
39 %0 = load <4 x i32>* @llvm_mips_dpadd_s_w_ARG1
40 %1 = load <8 x i16>* @llvm_mips_dpadd_s_w_ARG2
41 %2 = load <8 x i16>* @llvm_mips_dpadd_s_w_ARG3
42 %3 = tail call <4 x i32> @llvm.mips.dpadd.s.w(<4 x i32> %0, <8 x i16> %1, <8 x i16> %2)
43 store <4 x i32> %3, <4 x i32>* @llvm_mips_dpadd_s_w_RES
47 declare <4 x i32> @llvm.mips.dpadd.s.w(<4 x i32>, <8 x i16>, <8 x i16>) nounwind
49 ; CHECK: llvm_mips_dpadd_s_w_test:
55 ; CHECK: .size llvm_mips_dpadd_s_w_test
57 @llvm_mips_dpadd_s_d_ARG1 = global <2 x i64> <i64 0, i64 1>, align 16
58 @llvm_mips_dpadd_s_d_ARG2 = global <4 x i32> <i32 2, i32 3, i32 4, i32 5>, align 16
59 @llvm_mips_dpadd_s_d_ARG3 = global <4 x i32> <i32 6, i32 7, i32 8, i32 9>, align 16
60 @llvm_mips_dpadd_s_d_RES = global <2 x i64> <i64 0, i64 0>, align 16
62 define void @llvm_mips_dpadd_s_d_test() nounwind {
64 %0 = load <2 x i64>* @llvm_mips_dpadd_s_d_ARG1
65 %1 = load <4 x i32>* @llvm_mips_dpadd_s_d_ARG2
66 %2 = load <4 x i32>* @llvm_mips_dpadd_s_d_ARG3
67 %3 = tail call <2 x i64> @llvm.mips.dpadd.s.d(<2 x i64> %0, <4 x i32> %1, <4 x i32> %2)
68 store <2 x i64> %3, <2 x i64>* @llvm_mips_dpadd_s_d_RES
72 declare <2 x i64> @llvm.mips.dpadd.s.d(<2 x i64>, <4 x i32>, <4 x i32>) nounwind
74 ; CHECK: llvm_mips_dpadd_s_d_test:
80 ; CHECK: .size llvm_mips_dpadd_s_d_test
82 @llvm_mips_dpadd_u_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16
83 @llvm_mips_dpadd_u_h_ARG2 = global <16 x i8> <i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15, i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23>, align 16
84 @llvm_mips_dpadd_u_h_ARG3 = global <16 x i8> <i8 24, i8 25, i8 26, i8 27, i8 28, i8 29, i8 30, i8 31, i8 32, i8 33, i8 34, i8 35, i8 36, i8 37, i8 38, i8 39>, align 16
85 @llvm_mips_dpadd_u_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16
87 define void @llvm_mips_dpadd_u_h_test() nounwind {
89 %0 = load <8 x i16>* @llvm_mips_dpadd_u_h_ARG1
90 %1 = load <16 x i8>* @llvm_mips_dpadd_u_h_ARG2
91 %2 = load <16 x i8>* @llvm_mips_dpadd_u_h_ARG3
92 %3 = tail call <8 x i16> @llvm.mips.dpadd.u.h(<8 x i16> %0, <16 x i8> %1, <16 x i8> %2)
93 store <8 x i16> %3, <8 x i16>* @llvm_mips_dpadd_u_h_RES
97 declare <8 x i16> @llvm.mips.dpadd.u.h(<8 x i16>, <16 x i8>, <16 x i8>) nounwind
99 ; CHECK: llvm_mips_dpadd_u_h_test:
105 ; CHECK: .size llvm_mips_dpadd_u_h_test
107 @llvm_mips_dpadd_u_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16
108 @llvm_mips_dpadd_u_w_ARG2 = global <8 x i16> <i16 4, i16 5, i16 6, i16 7, i16 8, i16 9, i16 10, i16 11>, align 16
109 @llvm_mips_dpadd_u_w_ARG3 = global <8 x i16> <i16 12, i16 13, i16 14, i16 15, i16 16, i16 17, i16 18, i16 19>, align 16
110 @llvm_mips_dpadd_u_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16
112 define void @llvm_mips_dpadd_u_w_test() nounwind {
114 %0 = load <4 x i32>* @llvm_mips_dpadd_u_w_ARG1
115 %1 = load <8 x i16>* @llvm_mips_dpadd_u_w_ARG2
116 %2 = load <8 x i16>* @llvm_mips_dpadd_u_w_ARG3
117 %3 = tail call <4 x i32> @llvm.mips.dpadd.u.w(<4 x i32> %0, <8 x i16> %1, <8 x i16> %2)
118 store <4 x i32> %3, <4 x i32>* @llvm_mips_dpadd_u_w_RES
122 declare <4 x i32> @llvm.mips.dpadd.u.w(<4 x i32>, <8 x i16>, <8 x i16>) nounwind
124 ; CHECK: llvm_mips_dpadd_u_w_test:
130 ; CHECK: .size llvm_mips_dpadd_u_w_test
132 @llvm_mips_dpadd_u_d_ARG1 = global <2 x i64> <i64 0, i64 1>, align 16
133 @llvm_mips_dpadd_u_d_ARG2 = global <4 x i32> <i32 2, i32 3, i32 4, i32 5>, align 16
134 @llvm_mips_dpadd_u_d_ARG3 = global <4 x i32> <i32 6, i32 7, i32 8, i32 9>, align 16
135 @llvm_mips_dpadd_u_d_RES = global <2 x i64> <i64 0, i64 0>, align 16
137 define void @llvm_mips_dpadd_u_d_test() nounwind {
139 %0 = load <2 x i64>* @llvm_mips_dpadd_u_d_ARG1
140 %1 = load <4 x i32>* @llvm_mips_dpadd_u_d_ARG2
141 %2 = load <4 x i32>* @llvm_mips_dpadd_u_d_ARG3
142 %3 = tail call <2 x i64> @llvm.mips.dpadd.u.d(<2 x i64> %0, <4 x i32> %1, <4 x i32> %2)
143 store <2 x i64> %3, <2 x i64>* @llvm_mips_dpadd_u_d_RES
147 declare <2 x i64> @llvm.mips.dpadd.u.d(<2 x i64>, <4 x i32>, <4 x i32>) nounwind
149 ; CHECK: llvm_mips_dpadd_u_d_test:
155 ; CHECK: .size llvm_mips_dpadd_u_d_test
157 @llvm_mips_dpsub_s_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16
158 @llvm_mips_dpsub_s_h_ARG2 = global <16 x i8> <i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15, i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23>, align 16
159 @llvm_mips_dpsub_s_h_ARG3 = global <16 x i8> <i8 24, i8 25, i8 26, i8 27, i8 28, i8 29, i8 30, i8 31, i8 32, i8 33, i8 34, i8 35, i8 36, i8 37, i8 38, i8 39>, align 16
160 @llvm_mips_dpsub_s_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16
162 define void @llvm_mips_dpsub_s_h_test() nounwind {
164 %0 = load <8 x i16>* @llvm_mips_dpsub_s_h_ARG1
165 %1 = load <16 x i8>* @llvm_mips_dpsub_s_h_ARG2
166 %2 = load <16 x i8>* @llvm_mips_dpsub_s_h_ARG3
167 %3 = tail call <8 x i16> @llvm.mips.dpsub.s.h(<8 x i16> %0, <16 x i8> %1, <16 x i8> %2)
168 store <8 x i16> %3, <8 x i16>* @llvm_mips_dpsub_s_h_RES
172 declare <8 x i16> @llvm.mips.dpsub.s.h(<8 x i16>, <16 x i8>, <16 x i8>) nounwind
174 ; CHECK: llvm_mips_dpsub_s_h_test:
180 ; CHECK: .size llvm_mips_dpsub_s_h_test
182 @llvm_mips_dpsub_s_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16
183 @llvm_mips_dpsub_s_w_ARG2 = global <8 x i16> <i16 4, i16 5, i16 6, i16 7, i16 8, i16 9, i16 10, i16 11>, align 16
184 @llvm_mips_dpsub_s_w_ARG3 = global <8 x i16> <i16 12, i16 13, i16 14, i16 15, i16 16, i16 17, i16 18, i16 19>, align 16
185 @llvm_mips_dpsub_s_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16
187 define void @llvm_mips_dpsub_s_w_test() nounwind {
189 %0 = load <4 x i32>* @llvm_mips_dpsub_s_w_ARG1
190 %1 = load <8 x i16>* @llvm_mips_dpsub_s_w_ARG2
191 %2 = load <8 x i16>* @llvm_mips_dpsub_s_w_ARG3
192 %3 = tail call <4 x i32> @llvm.mips.dpsub.s.w(<4 x i32> %0, <8 x i16> %1, <8 x i16> %2)
193 store <4 x i32> %3, <4 x i32>* @llvm_mips_dpsub_s_w_RES
197 declare <4 x i32> @llvm.mips.dpsub.s.w(<4 x i32>, <8 x i16>, <8 x i16>) nounwind
199 ; CHECK: llvm_mips_dpsub_s_w_test:
205 ; CHECK: .size llvm_mips_dpsub_s_w_test
207 @llvm_mips_dpsub_s_d_ARG1 = global <2 x i64> <i64 0, i64 1>, align 16
208 @llvm_mips_dpsub_s_d_ARG2 = global <4 x i32> <i32 2, i32 3, i32 4, i32 5>, align 16
209 @llvm_mips_dpsub_s_d_ARG3 = global <4 x i32> <i32 6, i32 7, i32 8, i32 9>, align 16
210 @llvm_mips_dpsub_s_d_RES = global <2 x i64> <i64 0, i64 0>, align 16
212 define void @llvm_mips_dpsub_s_d_test() nounwind {
214 %0 = load <2 x i64>* @llvm_mips_dpsub_s_d_ARG1
215 %1 = load <4 x i32>* @llvm_mips_dpsub_s_d_ARG2
216 %2 = load <4 x i32>* @llvm_mips_dpsub_s_d_ARG3
217 %3 = tail call <2 x i64> @llvm.mips.dpsub.s.d(<2 x i64> %0, <4 x i32> %1, <4 x i32> %2)
218 store <2 x i64> %3, <2 x i64>* @llvm_mips_dpsub_s_d_RES
222 declare <2 x i64> @llvm.mips.dpsub.s.d(<2 x i64>, <4 x i32>, <4 x i32>) nounwind
224 ; CHECK: llvm_mips_dpsub_s_d_test:
230 ; CHECK: .size llvm_mips_dpsub_s_d_test
232 @llvm_mips_dpsub_u_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16
233 @llvm_mips_dpsub_u_h_ARG2 = global <16 x i8> <i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15, i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23>, align 16
234 @llvm_mips_dpsub_u_h_ARG3 = global <16 x i8> <i8 24, i8 25, i8 26, i8 27, i8 28, i8 29, i8 30, i8 31, i8 32, i8 33, i8 34, i8 35, i8 36, i8 37, i8 38, i8 39>, align 16
235 @llvm_mips_dpsub_u_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16
237 define void @llvm_mips_dpsub_u_h_test() nounwind {
239 %0 = load <8 x i16>* @llvm_mips_dpsub_u_h_ARG1
240 %1 = load <16 x i8>* @llvm_mips_dpsub_u_h_ARG2
241 %2 = load <16 x i8>* @llvm_mips_dpsub_u_h_ARG3
242 %3 = tail call <8 x i16> @llvm.mips.dpsub.u.h(<8 x i16> %0, <16 x i8> %1, <16 x i8> %2)
243 store <8 x i16> %3, <8 x i16>* @llvm_mips_dpsub_u_h_RES
247 declare <8 x i16> @llvm.mips.dpsub.u.h(<8 x i16>, <16 x i8>, <16 x i8>) nounwind
249 ; CHECK: llvm_mips_dpsub_u_h_test:
255 ; CHECK: .size llvm_mips_dpsub_u_h_test
257 @llvm_mips_dpsub_u_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16
258 @llvm_mips_dpsub_u_w_ARG2 = global <8 x i16> <i16 4, i16 5, i16 6, i16 7, i16 8, i16 9, i16 10, i16 11>, align 16
259 @llvm_mips_dpsub_u_w_ARG3 = global <8 x i16> <i16 12, i16 13, i16 14, i16 15, i16 16, i16 17, i16 18, i16 19>, align 16
260 @llvm_mips_dpsub_u_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16
262 define void @llvm_mips_dpsub_u_w_test() nounwind {
264 %0 = load <4 x i32>* @llvm_mips_dpsub_u_w_ARG1
265 %1 = load <8 x i16>* @llvm_mips_dpsub_u_w_ARG2
266 %2 = load <8 x i16>* @llvm_mips_dpsub_u_w_ARG3
267 %3 = tail call <4 x i32> @llvm.mips.dpsub.u.w(<4 x i32> %0, <8 x i16> %1, <8 x i16> %2)
268 store <4 x i32> %3, <4 x i32>* @llvm_mips_dpsub_u_w_RES
272 declare <4 x i32> @llvm.mips.dpsub.u.w(<4 x i32>, <8 x i16>, <8 x i16>) nounwind
274 ; CHECK: llvm_mips_dpsub_u_w_test:
280 ; CHECK: .size llvm_mips_dpsub_u_w_test
282 @llvm_mips_dpsub_u_d_ARG1 = global <2 x i64> <i64 0, i64 1>, align 16
283 @llvm_mips_dpsub_u_d_ARG2 = global <4 x i32> <i32 2, i32 3, i32 4, i32 5>, align 16
284 @llvm_mips_dpsub_u_d_ARG3 = global <4 x i32> <i32 6, i32 7, i32 8, i32 9>, align 16
285 @llvm_mips_dpsub_u_d_RES = global <2 x i64> <i64 0, i64 0>, align 16
287 define void @llvm_mips_dpsub_u_d_test() nounwind {
289 %0 = load <2 x i64>* @llvm_mips_dpsub_u_d_ARG1
290 %1 = load <4 x i32>* @llvm_mips_dpsub_u_d_ARG2
291 %2 = load <4 x i32>* @llvm_mips_dpsub_u_d_ARG3
292 %3 = tail call <2 x i64> @llvm.mips.dpsub.u.d(<2 x i64> %0, <4 x i32> %1, <4 x i32> %2)
293 store <2 x i64> %3, <2 x i64>* @llvm_mips_dpsub_u_d_RES
297 declare <2 x i64> @llvm.mips.dpsub.u.d(<2 x i64>, <4 x i32>, <4 x i32>) nounwind
299 ; CHECK: llvm_mips_dpsub_u_d_test:
305 ; CHECK: .size llvm_mips_dpsub_u_d_test