1 ; Test the MSA intrinsics that are encoded with the 3R instruction format and
2 ; use the result as a third operand and results in wider elements than the
5 ; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s
6 ; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | FileCheck %s
8 @llvm_mips_dpadd_s_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16
9 @llvm_mips_dpadd_s_h_ARG2 = global <16 x i8> <i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15, i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23>, align 16
10 @llvm_mips_dpadd_s_h_ARG3 = global <16 x i8> <i8 24, i8 25, i8 26, i8 27, i8 28, i8 29, i8 30, i8 31, i8 32, i8 33, i8 34, i8 35, i8 36, i8 37, i8 38, i8 39>, align 16
11 @llvm_mips_dpadd_s_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16
13 define void @llvm_mips_dpadd_s_h_test() nounwind {
15 %0 = load <8 x i16>* @llvm_mips_dpadd_s_h_ARG1
16 %1 = load <16 x i8>* @llvm_mips_dpadd_s_h_ARG2
17 %2 = load <16 x i8>* @llvm_mips_dpadd_s_h_ARG3
18 %3 = tail call <8 x i16> @llvm.mips.dpadd.s.h(<8 x i16> %0, <16 x i8> %1, <16 x i8> %2)
19 store <8 x i16> %3, <8 x i16>* @llvm_mips_dpadd_s_h_RES
23 declare <8 x i16> @llvm.mips.dpadd.s.h(<8 x i16>, <16 x i8>, <16 x i8>) nounwind
25 ; CHECK: llvm_mips_dpadd_s_h_test:
31 ; CHECK: .size llvm_mips_dpadd_s_h_test
33 @llvm_mips_dpadd_s_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16
34 @llvm_mips_dpadd_s_w_ARG2 = global <8 x i16> <i16 4, i16 5, i16 6, i16 7, i16 8, i16 9, i16 10, i16 11>, align 16
35 @llvm_mips_dpadd_s_w_ARG3 = global <8 x i16> <i16 12, i16 13, i16 14, i16 15, i16 16, i16 17, i16 18, i16 19>, align 16
36 @llvm_mips_dpadd_s_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16
38 define void @llvm_mips_dpadd_s_w_test() nounwind {
40 %0 = load <4 x i32>* @llvm_mips_dpadd_s_w_ARG1
41 %1 = load <8 x i16>* @llvm_mips_dpadd_s_w_ARG2
42 %2 = load <8 x i16>* @llvm_mips_dpadd_s_w_ARG3
43 %3 = tail call <4 x i32> @llvm.mips.dpadd.s.w(<4 x i32> %0, <8 x i16> %1, <8 x i16> %2)
44 store <4 x i32> %3, <4 x i32>* @llvm_mips_dpadd_s_w_RES
48 declare <4 x i32> @llvm.mips.dpadd.s.w(<4 x i32>, <8 x i16>, <8 x i16>) nounwind
50 ; CHECK: llvm_mips_dpadd_s_w_test:
56 ; CHECK: .size llvm_mips_dpadd_s_w_test
58 @llvm_mips_dpadd_s_d_ARG1 = global <2 x i64> <i64 0, i64 1>, align 16
59 @llvm_mips_dpadd_s_d_ARG2 = global <4 x i32> <i32 2, i32 3, i32 4, i32 5>, align 16
60 @llvm_mips_dpadd_s_d_ARG3 = global <4 x i32> <i32 6, i32 7, i32 8, i32 9>, align 16
61 @llvm_mips_dpadd_s_d_RES = global <2 x i64> <i64 0, i64 0>, align 16
63 define void @llvm_mips_dpadd_s_d_test() nounwind {
65 %0 = load <2 x i64>* @llvm_mips_dpadd_s_d_ARG1
66 %1 = load <4 x i32>* @llvm_mips_dpadd_s_d_ARG2
67 %2 = load <4 x i32>* @llvm_mips_dpadd_s_d_ARG3
68 %3 = tail call <2 x i64> @llvm.mips.dpadd.s.d(<2 x i64> %0, <4 x i32> %1, <4 x i32> %2)
69 store <2 x i64> %3, <2 x i64>* @llvm_mips_dpadd_s_d_RES
73 declare <2 x i64> @llvm.mips.dpadd.s.d(<2 x i64>, <4 x i32>, <4 x i32>) nounwind
75 ; CHECK: llvm_mips_dpadd_s_d_test:
81 ; CHECK: .size llvm_mips_dpadd_s_d_test
83 @llvm_mips_dpadd_u_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16
84 @llvm_mips_dpadd_u_h_ARG2 = global <16 x i8> <i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15, i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23>, align 16
85 @llvm_mips_dpadd_u_h_ARG3 = global <16 x i8> <i8 24, i8 25, i8 26, i8 27, i8 28, i8 29, i8 30, i8 31, i8 32, i8 33, i8 34, i8 35, i8 36, i8 37, i8 38, i8 39>, align 16
86 @llvm_mips_dpadd_u_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16
88 define void @llvm_mips_dpadd_u_h_test() nounwind {
90 %0 = load <8 x i16>* @llvm_mips_dpadd_u_h_ARG1
91 %1 = load <16 x i8>* @llvm_mips_dpadd_u_h_ARG2
92 %2 = load <16 x i8>* @llvm_mips_dpadd_u_h_ARG3
93 %3 = tail call <8 x i16> @llvm.mips.dpadd.u.h(<8 x i16> %0, <16 x i8> %1, <16 x i8> %2)
94 store <8 x i16> %3, <8 x i16>* @llvm_mips_dpadd_u_h_RES
98 declare <8 x i16> @llvm.mips.dpadd.u.h(<8 x i16>, <16 x i8>, <16 x i8>) nounwind
100 ; CHECK: llvm_mips_dpadd_u_h_test:
106 ; CHECK: .size llvm_mips_dpadd_u_h_test
108 @llvm_mips_dpadd_u_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16
109 @llvm_mips_dpadd_u_w_ARG2 = global <8 x i16> <i16 4, i16 5, i16 6, i16 7, i16 8, i16 9, i16 10, i16 11>, align 16
110 @llvm_mips_dpadd_u_w_ARG3 = global <8 x i16> <i16 12, i16 13, i16 14, i16 15, i16 16, i16 17, i16 18, i16 19>, align 16
111 @llvm_mips_dpadd_u_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16
113 define void @llvm_mips_dpadd_u_w_test() nounwind {
115 %0 = load <4 x i32>* @llvm_mips_dpadd_u_w_ARG1
116 %1 = load <8 x i16>* @llvm_mips_dpadd_u_w_ARG2
117 %2 = load <8 x i16>* @llvm_mips_dpadd_u_w_ARG3
118 %3 = tail call <4 x i32> @llvm.mips.dpadd.u.w(<4 x i32> %0, <8 x i16> %1, <8 x i16> %2)
119 store <4 x i32> %3, <4 x i32>* @llvm_mips_dpadd_u_w_RES
123 declare <4 x i32> @llvm.mips.dpadd.u.w(<4 x i32>, <8 x i16>, <8 x i16>) nounwind
125 ; CHECK: llvm_mips_dpadd_u_w_test:
131 ; CHECK: .size llvm_mips_dpadd_u_w_test
133 @llvm_mips_dpadd_u_d_ARG1 = global <2 x i64> <i64 0, i64 1>, align 16
134 @llvm_mips_dpadd_u_d_ARG2 = global <4 x i32> <i32 2, i32 3, i32 4, i32 5>, align 16
135 @llvm_mips_dpadd_u_d_ARG3 = global <4 x i32> <i32 6, i32 7, i32 8, i32 9>, align 16
136 @llvm_mips_dpadd_u_d_RES = global <2 x i64> <i64 0, i64 0>, align 16
138 define void @llvm_mips_dpadd_u_d_test() nounwind {
140 %0 = load <2 x i64>* @llvm_mips_dpadd_u_d_ARG1
141 %1 = load <4 x i32>* @llvm_mips_dpadd_u_d_ARG2
142 %2 = load <4 x i32>* @llvm_mips_dpadd_u_d_ARG3
143 %3 = tail call <2 x i64> @llvm.mips.dpadd.u.d(<2 x i64> %0, <4 x i32> %1, <4 x i32> %2)
144 store <2 x i64> %3, <2 x i64>* @llvm_mips_dpadd_u_d_RES
148 declare <2 x i64> @llvm.mips.dpadd.u.d(<2 x i64>, <4 x i32>, <4 x i32>) nounwind
150 ; CHECK: llvm_mips_dpadd_u_d_test:
156 ; CHECK: .size llvm_mips_dpadd_u_d_test
158 @llvm_mips_dpsub_s_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16
159 @llvm_mips_dpsub_s_h_ARG2 = global <16 x i8> <i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15, i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23>, align 16
160 @llvm_mips_dpsub_s_h_ARG3 = global <16 x i8> <i8 24, i8 25, i8 26, i8 27, i8 28, i8 29, i8 30, i8 31, i8 32, i8 33, i8 34, i8 35, i8 36, i8 37, i8 38, i8 39>, align 16
161 @llvm_mips_dpsub_s_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16
163 define void @llvm_mips_dpsub_s_h_test() nounwind {
165 %0 = load <8 x i16>* @llvm_mips_dpsub_s_h_ARG1
166 %1 = load <16 x i8>* @llvm_mips_dpsub_s_h_ARG2
167 %2 = load <16 x i8>* @llvm_mips_dpsub_s_h_ARG3
168 %3 = tail call <8 x i16> @llvm.mips.dpsub.s.h(<8 x i16> %0, <16 x i8> %1, <16 x i8> %2)
169 store <8 x i16> %3, <8 x i16>* @llvm_mips_dpsub_s_h_RES
173 declare <8 x i16> @llvm.mips.dpsub.s.h(<8 x i16>, <16 x i8>, <16 x i8>) nounwind
175 ; CHECK: llvm_mips_dpsub_s_h_test:
181 ; CHECK: .size llvm_mips_dpsub_s_h_test
183 @llvm_mips_dpsub_s_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16
184 @llvm_mips_dpsub_s_w_ARG2 = global <8 x i16> <i16 4, i16 5, i16 6, i16 7, i16 8, i16 9, i16 10, i16 11>, align 16
185 @llvm_mips_dpsub_s_w_ARG3 = global <8 x i16> <i16 12, i16 13, i16 14, i16 15, i16 16, i16 17, i16 18, i16 19>, align 16
186 @llvm_mips_dpsub_s_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16
188 define void @llvm_mips_dpsub_s_w_test() nounwind {
190 %0 = load <4 x i32>* @llvm_mips_dpsub_s_w_ARG1
191 %1 = load <8 x i16>* @llvm_mips_dpsub_s_w_ARG2
192 %2 = load <8 x i16>* @llvm_mips_dpsub_s_w_ARG3
193 %3 = tail call <4 x i32> @llvm.mips.dpsub.s.w(<4 x i32> %0, <8 x i16> %1, <8 x i16> %2)
194 store <4 x i32> %3, <4 x i32>* @llvm_mips_dpsub_s_w_RES
198 declare <4 x i32> @llvm.mips.dpsub.s.w(<4 x i32>, <8 x i16>, <8 x i16>) nounwind
200 ; CHECK: llvm_mips_dpsub_s_w_test:
206 ; CHECK: .size llvm_mips_dpsub_s_w_test
208 @llvm_mips_dpsub_s_d_ARG1 = global <2 x i64> <i64 0, i64 1>, align 16
209 @llvm_mips_dpsub_s_d_ARG2 = global <4 x i32> <i32 2, i32 3, i32 4, i32 5>, align 16
210 @llvm_mips_dpsub_s_d_ARG3 = global <4 x i32> <i32 6, i32 7, i32 8, i32 9>, align 16
211 @llvm_mips_dpsub_s_d_RES = global <2 x i64> <i64 0, i64 0>, align 16
213 define void @llvm_mips_dpsub_s_d_test() nounwind {
215 %0 = load <2 x i64>* @llvm_mips_dpsub_s_d_ARG1
216 %1 = load <4 x i32>* @llvm_mips_dpsub_s_d_ARG2
217 %2 = load <4 x i32>* @llvm_mips_dpsub_s_d_ARG3
218 %3 = tail call <2 x i64> @llvm.mips.dpsub.s.d(<2 x i64> %0, <4 x i32> %1, <4 x i32> %2)
219 store <2 x i64> %3, <2 x i64>* @llvm_mips_dpsub_s_d_RES
223 declare <2 x i64> @llvm.mips.dpsub.s.d(<2 x i64>, <4 x i32>, <4 x i32>) nounwind
225 ; CHECK: llvm_mips_dpsub_s_d_test:
231 ; CHECK: .size llvm_mips_dpsub_s_d_test
233 @llvm_mips_dpsub_u_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16
234 @llvm_mips_dpsub_u_h_ARG2 = global <16 x i8> <i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15, i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23>, align 16
235 @llvm_mips_dpsub_u_h_ARG3 = global <16 x i8> <i8 24, i8 25, i8 26, i8 27, i8 28, i8 29, i8 30, i8 31, i8 32, i8 33, i8 34, i8 35, i8 36, i8 37, i8 38, i8 39>, align 16
236 @llvm_mips_dpsub_u_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16
238 define void @llvm_mips_dpsub_u_h_test() nounwind {
240 %0 = load <8 x i16>* @llvm_mips_dpsub_u_h_ARG1
241 %1 = load <16 x i8>* @llvm_mips_dpsub_u_h_ARG2
242 %2 = load <16 x i8>* @llvm_mips_dpsub_u_h_ARG3
243 %3 = tail call <8 x i16> @llvm.mips.dpsub.u.h(<8 x i16> %0, <16 x i8> %1, <16 x i8> %2)
244 store <8 x i16> %3, <8 x i16>* @llvm_mips_dpsub_u_h_RES
248 declare <8 x i16> @llvm.mips.dpsub.u.h(<8 x i16>, <16 x i8>, <16 x i8>) nounwind
250 ; CHECK: llvm_mips_dpsub_u_h_test:
256 ; CHECK: .size llvm_mips_dpsub_u_h_test
258 @llvm_mips_dpsub_u_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16
259 @llvm_mips_dpsub_u_w_ARG2 = global <8 x i16> <i16 4, i16 5, i16 6, i16 7, i16 8, i16 9, i16 10, i16 11>, align 16
260 @llvm_mips_dpsub_u_w_ARG3 = global <8 x i16> <i16 12, i16 13, i16 14, i16 15, i16 16, i16 17, i16 18, i16 19>, align 16
261 @llvm_mips_dpsub_u_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16
263 define void @llvm_mips_dpsub_u_w_test() nounwind {
265 %0 = load <4 x i32>* @llvm_mips_dpsub_u_w_ARG1
266 %1 = load <8 x i16>* @llvm_mips_dpsub_u_w_ARG2
267 %2 = load <8 x i16>* @llvm_mips_dpsub_u_w_ARG3
268 %3 = tail call <4 x i32> @llvm.mips.dpsub.u.w(<4 x i32> %0, <8 x i16> %1, <8 x i16> %2)
269 store <4 x i32> %3, <4 x i32>* @llvm_mips_dpsub_u_w_RES
273 declare <4 x i32> @llvm.mips.dpsub.u.w(<4 x i32>, <8 x i16>, <8 x i16>) nounwind
275 ; CHECK: llvm_mips_dpsub_u_w_test:
281 ; CHECK: .size llvm_mips_dpsub_u_w_test
283 @llvm_mips_dpsub_u_d_ARG1 = global <2 x i64> <i64 0, i64 1>, align 16
284 @llvm_mips_dpsub_u_d_ARG2 = global <4 x i32> <i32 2, i32 3, i32 4, i32 5>, align 16
285 @llvm_mips_dpsub_u_d_ARG3 = global <4 x i32> <i32 6, i32 7, i32 8, i32 9>, align 16
286 @llvm_mips_dpsub_u_d_RES = global <2 x i64> <i64 0, i64 0>, align 16
288 define void @llvm_mips_dpsub_u_d_test() nounwind {
290 %0 = load <2 x i64>* @llvm_mips_dpsub_u_d_ARG1
291 %1 = load <4 x i32>* @llvm_mips_dpsub_u_d_ARG2
292 %2 = load <4 x i32>* @llvm_mips_dpsub_u_d_ARG3
293 %3 = tail call <2 x i64> @llvm.mips.dpsub.u.d(<2 x i64> %0, <4 x i32> %1, <4 x i32> %2)
294 store <2 x i64> %3, <2 x i64>* @llvm_mips_dpsub_u_d_RES
298 declare <2 x i64> @llvm.mips.dpsub.u.d(<2 x i64>, <4 x i32>, <4 x i32>) nounwind
300 ; CHECK: llvm_mips_dpsub_u_d_test:
306 ; CHECK: .size llvm_mips_dpsub_u_d_test