1 ; Test the MSA intrinsics that are encoded with the 3R instruction format and
4 ; RUN: llc -march=mips -mattr=+msa < %s | FileCheck %s
6 @llvm_mips_ldx_b_ARG = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
7 @llvm_mips_ldx_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16
9 define void @llvm_mips_ldx_b_test(i32 %a1) nounwind {
11 %0 = bitcast <16 x i8>* @llvm_mips_ldx_b_ARG to i8*
12 %1 = tail call <16 x i8> @llvm.mips.ldx.b(i8* %0, i32 %a1)
13 store <16 x i8> %1, <16 x i8>* @llvm_mips_ldx_b_RES
17 declare <16 x i8> @llvm.mips.ldx.b(i8*, i32) nounwind
19 ; CHECK: llvm_mips_ldx_b_test:
20 ; CHECK: ldx.b [[R1:\$w[0-9]+]], $4(
22 ; CHECK: .size llvm_mips_ldx_b_test
24 @llvm_mips_ldx_h_ARG = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16
25 @llvm_mips_ldx_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16
27 define void @llvm_mips_ldx_h_test(i32 %a1) nounwind {
29 %0 = bitcast <8 x i16>* @llvm_mips_ldx_h_ARG to i8*
30 %1 = tail call <8 x i16> @llvm.mips.ldx.h(i8* %0, i32 %a1)
31 store <8 x i16> %1, <8 x i16>* @llvm_mips_ldx_h_RES
35 declare <8 x i16> @llvm.mips.ldx.h(i8*, i32) nounwind
37 ; CHECK: llvm_mips_ldx_h_test:
38 ; CHECK: ldx.h [[R1:\$w[0-9]+]], $4(
40 ; CHECK: .size llvm_mips_ldx_h_test
42 @llvm_mips_ldx_w_ARG = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16
43 @llvm_mips_ldx_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16
45 define void @llvm_mips_ldx_w_test(i32 %a1) nounwind {
47 %0 = bitcast <4 x i32>* @llvm_mips_ldx_w_ARG to i8*
48 %1 = tail call <4 x i32> @llvm.mips.ldx.w(i8* %0, i32 %a1)
49 store <4 x i32> %1, <4 x i32>* @llvm_mips_ldx_w_RES
53 declare <4 x i32> @llvm.mips.ldx.w(i8*, i32) nounwind
55 ; CHECK: llvm_mips_ldx_w_test:
56 ; CHECK: ldx.w [[R1:\$w[0-9]+]], $4(
58 ; CHECK: .size llvm_mips_ldx_w_test
60 @llvm_mips_ldx_d_ARG = global <2 x i64> <i64 0, i64 1>, align 16
61 @llvm_mips_ldx_d_RES = global <2 x i64> <i64 0, i64 0>, align 16
63 define void @llvm_mips_ldx_d_test(i32 %a1) nounwind {
65 %0 = bitcast <2 x i64>* @llvm_mips_ldx_d_ARG to i8*
66 %1 = tail call <2 x i64> @llvm.mips.ldx.d(i8* %0, i32 %a1)
67 store <2 x i64> %1, <2 x i64>* @llvm_mips_ldx_d_RES
71 declare <2 x i64> @llvm.mips.ldx.d(i8*, i32) nounwind
73 ; CHECK: llvm_mips_ldx_d_test:
74 ; CHECK: ldx.d [[R1:\$w[0-9]+]], $4(
76 ; CHECK: .size llvm_mips_ldx_d_test
78 @llvm_mips_stx_b_ARG = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
79 @llvm_mips_stx_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16
81 define void @llvm_mips_stx_b_test(i32 %a1) nounwind {
83 %0 = load <16 x i8>* @llvm_mips_stx_b_ARG
84 %1 = bitcast <16 x i8>* @llvm_mips_stx_b_RES to i8*
85 tail call void @llvm.mips.stx.b(<16 x i8> %0, i8* %1, i32 %a1)
89 declare void @llvm.mips.stx.b(<16 x i8>, i8*, i32) nounwind
91 ; CHECK: llvm_mips_stx_b_test:
93 ; CHECK: stx.b [[R1:\$w[0-9]+]], $4(
94 ; CHECK: .size llvm_mips_stx_b_test
96 @llvm_mips_stx_h_ARG = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16
97 @llvm_mips_stx_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16
99 define void @llvm_mips_stx_h_test(i32 %a1) nounwind {
101 %0 = load <8 x i16>* @llvm_mips_stx_h_ARG
102 %1 = bitcast <8 x i16>* @llvm_mips_stx_h_RES to i8*
103 tail call void @llvm.mips.stx.h(<8 x i16> %0, i8* %1, i32 %a1)
107 declare void @llvm.mips.stx.h(<8 x i16>, i8*, i32) nounwind
109 ; CHECK: llvm_mips_stx_h_test:
111 ; CHECK: stx.h [[R1:\$w[0-9]+]], $4(
112 ; CHECK: .size llvm_mips_stx_h_test
114 @llvm_mips_stx_w_ARG = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16
115 @llvm_mips_stx_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16
117 define void @llvm_mips_stx_w_test(i32 %a1) nounwind {
119 %0 = load <4 x i32>* @llvm_mips_stx_w_ARG
120 %1 = bitcast <4 x i32>* @llvm_mips_stx_w_RES to i8*
121 tail call void @llvm.mips.stx.w(<4 x i32> %0, i8* %1, i32 %a1)
125 declare void @llvm.mips.stx.w(<4 x i32>, i8*, i32) nounwind
127 ; CHECK: llvm_mips_stx_w_test:
129 ; CHECK: stx.w [[R1:\$w[0-9]+]], $4(
130 ; CHECK: .size llvm_mips_stx_w_test
132 @llvm_mips_stx_d_ARG = global <2 x i64> <i64 0, i64 1>, align 16
133 @llvm_mips_stx_d_RES = global <2 x i64> <i64 0, i64 0>, align 16
135 define void @llvm_mips_stx_d_test(i32 %a1) nounwind {
137 %0 = load <2 x i64>* @llvm_mips_stx_d_ARG
138 %1 = bitcast <2 x i64>* @llvm_mips_stx_d_RES to i8*
139 tail call void @llvm.mips.stx.d(<2 x i64> %0, i8* %1, i32 %a1)
143 declare void @llvm.mips.stx.d(<2 x i64>, i8*, i32) nounwind
145 ; CHECK: llvm_mips_stx_d_test:
147 ; CHECK: stx.d [[R1:\$w[0-9]+]], $4(
148 ; CHECK: .size llvm_mips_stx_d_test