1 ; Test the MSA intrinsics that are encoded with the 3RF instruction format.
3 ; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s
5 @llvm_mips_fadd_w_ARG1 = global <4 x float> <float 0.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00>, align 16
6 @llvm_mips_fadd_w_ARG2 = global <4 x float> <float 4.000000e+00, float 5.000000e+00, float 6.000000e+00, float 7.000000e+00>, align 16
7 @llvm_mips_fadd_w_RES = global <4 x float> <float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00>, align 16
9 define void @llvm_mips_fadd_w_test() nounwind {
11 %0 = load <4 x float>* @llvm_mips_fadd_w_ARG1
12 %1 = load <4 x float>* @llvm_mips_fadd_w_ARG2
13 %2 = tail call <4 x float> @llvm.mips.fadd.w(<4 x float> %0, <4 x float> %1)
14 store <4 x float> %2, <4 x float>* @llvm_mips_fadd_w_RES
18 declare <4 x float> @llvm.mips.fadd.w(<4 x float>, <4 x float>) nounwind
20 ; CHECK: llvm_mips_fadd_w_test:
25 ; CHECK: .size llvm_mips_fadd_w_test
27 @llvm_mips_fadd_d_ARG1 = global <2 x double> <double 0.000000e+00, double 1.000000e+00>, align 16
28 @llvm_mips_fadd_d_ARG2 = global <2 x double> <double 2.000000e+00, double 3.000000e+00>, align 16
29 @llvm_mips_fadd_d_RES = global <2 x double> <double 0.000000e+00, double 0.000000e+00>, align 16
31 define void @llvm_mips_fadd_d_test() nounwind {
33 %0 = load <2 x double>* @llvm_mips_fadd_d_ARG1
34 %1 = load <2 x double>* @llvm_mips_fadd_d_ARG2
35 %2 = tail call <2 x double> @llvm.mips.fadd.d(<2 x double> %0, <2 x double> %1)
36 store <2 x double> %2, <2 x double>* @llvm_mips_fadd_d_RES
40 declare <2 x double> @llvm.mips.fadd.d(<2 x double>, <2 x double>) nounwind
42 ; CHECK: llvm_mips_fadd_d_test:
47 ; CHECK: .size llvm_mips_fadd_d_test
49 define void @fadd_w_test() nounwind {
51 %0 = load <4 x float>* @llvm_mips_fadd_w_ARG1
52 %1 = load <4 x float>* @llvm_mips_fadd_w_ARG2
53 %2 = fadd <4 x float> %0, %1
54 store <4 x float> %2, <4 x float>* @llvm_mips_fadd_w_RES
63 ; CHECK: .size fadd_w_test
65 define void @fadd_d_test() nounwind {
67 %0 = load <2 x double>* @llvm_mips_fadd_d_ARG1
68 %1 = load <2 x double>* @llvm_mips_fadd_d_ARG2
69 %2 = fadd <2 x double> %0, %1
70 store <2 x double> %2, <2 x double>* @llvm_mips_fadd_d_RES
79 ; CHECK: .size fadd_d_test
81 @llvm_mips_fdiv_w_ARG1 = global <4 x float> <float 0.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00>, align 16
82 @llvm_mips_fdiv_w_ARG2 = global <4 x float> <float 4.000000e+00, float 5.000000e+00, float 6.000000e+00, float 7.000000e+00>, align 16
83 @llvm_mips_fdiv_w_RES = global <4 x float> <float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00>, align 16
85 define void @llvm_mips_fdiv_w_test() nounwind {
87 %0 = load <4 x float>* @llvm_mips_fdiv_w_ARG1
88 %1 = load <4 x float>* @llvm_mips_fdiv_w_ARG2
89 %2 = tail call <4 x float> @llvm.mips.fdiv.w(<4 x float> %0, <4 x float> %1)
90 store <4 x float> %2, <4 x float>* @llvm_mips_fdiv_w_RES
94 declare <4 x float> @llvm.mips.fdiv.w(<4 x float>, <4 x float>) nounwind
96 ; CHECK: llvm_mips_fdiv_w_test:
101 ; CHECK: .size llvm_mips_fdiv_w_test
103 @llvm_mips_fdiv_d_ARG1 = global <2 x double> <double 0.000000e+00, double 1.000000e+00>, align 16
104 @llvm_mips_fdiv_d_ARG2 = global <2 x double> <double 2.000000e+00, double 3.000000e+00>, align 16
105 @llvm_mips_fdiv_d_RES = global <2 x double> <double 0.000000e+00, double 0.000000e+00>, align 16
107 define void @llvm_mips_fdiv_d_test() nounwind {
109 %0 = load <2 x double>* @llvm_mips_fdiv_d_ARG1
110 %1 = load <2 x double>* @llvm_mips_fdiv_d_ARG2
111 %2 = tail call <2 x double> @llvm.mips.fdiv.d(<2 x double> %0, <2 x double> %1)
112 store <2 x double> %2, <2 x double>* @llvm_mips_fdiv_d_RES
116 declare <2 x double> @llvm.mips.fdiv.d(<2 x double>, <2 x double>) nounwind
118 ; CHECK: llvm_mips_fdiv_d_test:
123 ; CHECK: .size llvm_mips_fdiv_d_test
125 define void @fdiv_w_test() nounwind {
127 %0 = load <4 x float>* @llvm_mips_fdiv_w_ARG1
128 %1 = load <4 x float>* @llvm_mips_fdiv_w_ARG2
129 %2 = fdiv <4 x float> %0, %1
130 store <4 x float> %2, <4 x float>* @llvm_mips_fdiv_w_RES
134 ; CHECK: fdiv_w_test:
139 ; CHECK: .size fdiv_w_test
141 define void @fdiv_d_test() nounwind {
143 %0 = load <2 x double>* @llvm_mips_fdiv_d_ARG1
144 %1 = load <2 x double>* @llvm_mips_fdiv_d_ARG2
145 %2 = fdiv <2 x double> %0, %1
146 store <2 x double> %2, <2 x double>* @llvm_mips_fdiv_d_RES
150 ; CHECK: fdiv_d_test:
155 ; CHECK: .size fdiv_d_test
157 @llvm_mips_fmin_w_ARG1 = global <4 x float> <float 0.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00>, align 16
158 @llvm_mips_fmin_w_ARG2 = global <4 x float> <float 4.000000e+00, float 5.000000e+00, float 6.000000e+00, float 7.000000e+00>, align 16
159 @llvm_mips_fmin_w_RES = global <4 x float> <float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00>, align 16
161 define void @llvm_mips_fmin_w_test() nounwind {
163 %0 = load <4 x float>* @llvm_mips_fmin_w_ARG1
164 %1 = load <4 x float>* @llvm_mips_fmin_w_ARG2
165 %2 = tail call <4 x float> @llvm.mips.fmin.w(<4 x float> %0, <4 x float> %1)
166 store <4 x float> %2, <4 x float>* @llvm_mips_fmin_w_RES
170 declare <4 x float> @llvm.mips.fmin.w(<4 x float>, <4 x float>) nounwind
172 ; CHECK: llvm_mips_fmin_w_test:
177 ; CHECK: .size llvm_mips_fmin_w_test
179 @llvm_mips_fmin_d_ARG1 = global <2 x double> <double 0.000000e+00, double 1.000000e+00>, align 16
180 @llvm_mips_fmin_d_ARG2 = global <2 x double> <double 2.000000e+00, double 3.000000e+00>, align 16
181 @llvm_mips_fmin_d_RES = global <2 x double> <double 0.000000e+00, double 0.000000e+00>, align 16
183 define void @llvm_mips_fmin_d_test() nounwind {
185 %0 = load <2 x double>* @llvm_mips_fmin_d_ARG1
186 %1 = load <2 x double>* @llvm_mips_fmin_d_ARG2
187 %2 = tail call <2 x double> @llvm.mips.fmin.d(<2 x double> %0, <2 x double> %1)
188 store <2 x double> %2, <2 x double>* @llvm_mips_fmin_d_RES
192 declare <2 x double> @llvm.mips.fmin.d(<2 x double>, <2 x double>) nounwind
194 ; CHECK: llvm_mips_fmin_d_test:
199 ; CHECK: .size llvm_mips_fmin_d_test
201 @llvm_mips_fmin_a_w_ARG1 = global <4 x float> <float 0.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00>, align 16
202 @llvm_mips_fmin_a_w_ARG2 = global <4 x float> <float 4.000000e+00, float 5.000000e+00, float 6.000000e+00, float 7.000000e+00>, align 16
203 @llvm_mips_fmin_a_w_RES = global <4 x float> <float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00>, align 16
205 define void @llvm_mips_fmin_a_w_test() nounwind {
207 %0 = load <4 x float>* @llvm_mips_fmin_a_w_ARG1
208 %1 = load <4 x float>* @llvm_mips_fmin_a_w_ARG2
209 %2 = tail call <4 x float> @llvm.mips.fmin.a.w(<4 x float> %0, <4 x float> %1)
210 store <4 x float> %2, <4 x float>* @llvm_mips_fmin_a_w_RES
214 declare <4 x float> @llvm.mips.fmin.a.w(<4 x float>, <4 x float>) nounwind
216 ; CHECK: llvm_mips_fmin_a_w_test:
221 ; CHECK: .size llvm_mips_fmin_a_w_test
223 @llvm_mips_fmin_a_d_ARG1 = global <2 x double> <double 0.000000e+00, double 1.000000e+00>, align 16
224 @llvm_mips_fmin_a_d_ARG2 = global <2 x double> <double 2.000000e+00, double 3.000000e+00>, align 16
225 @llvm_mips_fmin_a_d_RES = global <2 x double> <double 0.000000e+00, double 0.000000e+00>, align 16
227 define void @llvm_mips_fmin_a_d_test() nounwind {
229 %0 = load <2 x double>* @llvm_mips_fmin_a_d_ARG1
230 %1 = load <2 x double>* @llvm_mips_fmin_a_d_ARG2
231 %2 = tail call <2 x double> @llvm.mips.fmin.a.d(<2 x double> %0, <2 x double> %1)
232 store <2 x double> %2, <2 x double>* @llvm_mips_fmin_a_d_RES
236 declare <2 x double> @llvm.mips.fmin.a.d(<2 x double>, <2 x double>) nounwind
238 ; CHECK: llvm_mips_fmin_a_d_test:
243 ; CHECK: .size llvm_mips_fmin_a_d_test
245 @llvm_mips_fmax_w_ARG1 = global <4 x float> <float 0.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00>, align 16
246 @llvm_mips_fmax_w_ARG2 = global <4 x float> <float 4.000000e+00, float 5.000000e+00, float 6.000000e+00, float 7.000000e+00>, align 16
247 @llvm_mips_fmax_w_RES = global <4 x float> <float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00>, align 16
249 define void @llvm_mips_fmax_w_test() nounwind {
251 %0 = load <4 x float>* @llvm_mips_fmax_w_ARG1
252 %1 = load <4 x float>* @llvm_mips_fmax_w_ARG2
253 %2 = tail call <4 x float> @llvm.mips.fmax.w(<4 x float> %0, <4 x float> %1)
254 store <4 x float> %2, <4 x float>* @llvm_mips_fmax_w_RES
258 declare <4 x float> @llvm.mips.fmax.w(<4 x float>, <4 x float>) nounwind
260 ; CHECK: llvm_mips_fmax_w_test:
265 ; CHECK: .size llvm_mips_fmax_w_test
267 @llvm_mips_fmax_d_ARG1 = global <2 x double> <double 0.000000e+00, double 1.000000e+00>, align 16
268 @llvm_mips_fmax_d_ARG2 = global <2 x double> <double 2.000000e+00, double 3.000000e+00>, align 16
269 @llvm_mips_fmax_d_RES = global <2 x double> <double 0.000000e+00, double 0.000000e+00>, align 16
271 define void @llvm_mips_fmax_d_test() nounwind {
273 %0 = load <2 x double>* @llvm_mips_fmax_d_ARG1
274 %1 = load <2 x double>* @llvm_mips_fmax_d_ARG2
275 %2 = tail call <2 x double> @llvm.mips.fmax.d(<2 x double> %0, <2 x double> %1)
276 store <2 x double> %2, <2 x double>* @llvm_mips_fmax_d_RES
280 declare <2 x double> @llvm.mips.fmax.d(<2 x double>, <2 x double>) nounwind
282 ; CHECK: llvm_mips_fmax_d_test:
287 ; CHECK: .size llvm_mips_fmax_d_test
289 @llvm_mips_fmax_a_w_ARG1 = global <4 x float> <float 0.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00>, align 16
290 @llvm_mips_fmax_a_w_ARG2 = global <4 x float> <float 4.000000e+00, float 5.000000e+00, float 6.000000e+00, float 7.000000e+00>, align 16
291 @llvm_mips_fmax_a_w_RES = global <4 x float> <float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00>, align 16
293 define void @llvm_mips_fmax_a_w_test() nounwind {
295 %0 = load <4 x float>* @llvm_mips_fmax_a_w_ARG1
296 %1 = load <4 x float>* @llvm_mips_fmax_a_w_ARG2
297 %2 = tail call <4 x float> @llvm.mips.fmax.a.w(<4 x float> %0, <4 x float> %1)
298 store <4 x float> %2, <4 x float>* @llvm_mips_fmax_a_w_RES
302 declare <4 x float> @llvm.mips.fmax.a.w(<4 x float>, <4 x float>) nounwind
304 ; CHECK: llvm_mips_fmax_a_w_test:
309 ; CHECK: .size llvm_mips_fmax_a_w_test
311 @llvm_mips_fmax_a_d_ARG1 = global <2 x double> <double 0.000000e+00, double 1.000000e+00>, align 16
312 @llvm_mips_fmax_a_d_ARG2 = global <2 x double> <double 2.000000e+00, double 3.000000e+00>, align 16
313 @llvm_mips_fmax_a_d_RES = global <2 x double> <double 0.000000e+00, double 0.000000e+00>, align 16
315 define void @llvm_mips_fmax_a_d_test() nounwind {
317 %0 = load <2 x double>* @llvm_mips_fmax_a_d_ARG1
318 %1 = load <2 x double>* @llvm_mips_fmax_a_d_ARG2
319 %2 = tail call <2 x double> @llvm.mips.fmax.a.d(<2 x double> %0, <2 x double> %1)
320 store <2 x double> %2, <2 x double>* @llvm_mips_fmax_a_d_RES
324 declare <2 x double> @llvm.mips.fmax.a.d(<2 x double>, <2 x double>) nounwind
326 ; CHECK: llvm_mips_fmax_a_d_test:
331 ; CHECK: .size llvm_mips_fmax_a_d_test
333 @llvm_mips_fmul_w_ARG1 = global <4 x float> <float 0.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00>, align 16
334 @llvm_mips_fmul_w_ARG2 = global <4 x float> <float 4.000000e+00, float 5.000000e+00, float 6.000000e+00, float 7.000000e+00>, align 16
335 @llvm_mips_fmul_w_RES = global <4 x float> <float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00>, align 16
337 define void @llvm_mips_fmul_w_test() nounwind {
339 %0 = load <4 x float>* @llvm_mips_fmul_w_ARG1
340 %1 = load <4 x float>* @llvm_mips_fmul_w_ARG2
341 %2 = tail call <4 x float> @llvm.mips.fmul.w(<4 x float> %0, <4 x float> %1)
342 store <4 x float> %2, <4 x float>* @llvm_mips_fmul_w_RES
346 declare <4 x float> @llvm.mips.fmul.w(<4 x float>, <4 x float>) nounwind
348 ; CHECK: llvm_mips_fmul_w_test:
353 ; CHECK: .size llvm_mips_fmul_w_test
355 @llvm_mips_fmul_d_ARG1 = global <2 x double> <double 0.000000e+00, double 1.000000e+00>, align 16
356 @llvm_mips_fmul_d_ARG2 = global <2 x double> <double 2.000000e+00, double 3.000000e+00>, align 16
357 @llvm_mips_fmul_d_RES = global <2 x double> <double 0.000000e+00, double 0.000000e+00>, align 16
359 define void @llvm_mips_fmul_d_test() nounwind {
361 %0 = load <2 x double>* @llvm_mips_fmul_d_ARG1
362 %1 = load <2 x double>* @llvm_mips_fmul_d_ARG2
363 %2 = tail call <2 x double> @llvm.mips.fmul.d(<2 x double> %0, <2 x double> %1)
364 store <2 x double> %2, <2 x double>* @llvm_mips_fmul_d_RES
368 declare <2 x double> @llvm.mips.fmul.d(<2 x double>, <2 x double>) nounwind
370 ; CHECK: llvm_mips_fmul_d_test:
375 ; CHECK: .size llvm_mips_fmul_d_test
377 define void @fmul_w_test() nounwind {
379 %0 = load <4 x float>* @llvm_mips_fmul_w_ARG1
380 %1 = load <4 x float>* @llvm_mips_fmul_w_ARG2
381 %2 = fmul <4 x float> %0, %1
382 store <4 x float> %2, <4 x float>* @llvm_mips_fmul_w_RES
386 ; CHECK: fmul_w_test:
391 ; CHECK: .size fmul_w_test
393 define void @fmul_d_test() nounwind {
395 %0 = load <2 x double>* @llvm_mips_fmul_d_ARG1
396 %1 = load <2 x double>* @llvm_mips_fmul_d_ARG2
397 %2 = fmul <2 x double> %0, %1
398 store <2 x double> %2, <2 x double>* @llvm_mips_fmul_d_RES
402 ; CHECK: fmul_d_test:
407 ; CHECK: .size fmul_d_test
409 @llvm_mips_fsub_w_ARG1 = global <4 x float> <float 0.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00>, align 16
410 @llvm_mips_fsub_w_ARG2 = global <4 x float> <float 4.000000e+00, float 5.000000e+00, float 6.000000e+00, float 7.000000e+00>, align 16
411 @llvm_mips_fsub_w_RES = global <4 x float> <float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00>, align 16
413 define void @llvm_mips_fsub_w_test() nounwind {
415 %0 = load <4 x float>* @llvm_mips_fsub_w_ARG1
416 %1 = load <4 x float>* @llvm_mips_fsub_w_ARG2
417 %2 = tail call <4 x float> @llvm.mips.fsub.w(<4 x float> %0, <4 x float> %1)
418 store <4 x float> %2, <4 x float>* @llvm_mips_fsub_w_RES
422 declare <4 x float> @llvm.mips.fsub.w(<4 x float>, <4 x float>) nounwind
424 ; CHECK: llvm_mips_fsub_w_test:
429 ; CHECK: .size llvm_mips_fsub_w_test
431 @llvm_mips_fsub_d_ARG1 = global <2 x double> <double 0.000000e+00, double 1.000000e+00>, align 16
432 @llvm_mips_fsub_d_ARG2 = global <2 x double> <double 2.000000e+00, double 3.000000e+00>, align 16
433 @llvm_mips_fsub_d_RES = global <2 x double> <double 0.000000e+00, double 0.000000e+00>, align 16
435 define void @llvm_mips_fsub_d_test() nounwind {
437 %0 = load <2 x double>* @llvm_mips_fsub_d_ARG1
438 %1 = load <2 x double>* @llvm_mips_fsub_d_ARG2
439 %2 = tail call <2 x double> @llvm.mips.fsub.d(<2 x double> %0, <2 x double> %1)
440 store <2 x double> %2, <2 x double>* @llvm_mips_fsub_d_RES
444 declare <2 x double> @llvm.mips.fsub.d(<2 x double>, <2 x double>) nounwind
446 ; CHECK: llvm_mips_fsub_d_test:
451 ; CHECK: .size llvm_mips_fsub_d_test
454 define void @fsub_w_test() nounwind {
456 %0 = load <4 x float>* @llvm_mips_fsub_w_ARG1
457 %1 = load <4 x float>* @llvm_mips_fsub_w_ARG2
458 %2 = fsub <4 x float> %0, %1
459 store <4 x float> %2, <4 x float>* @llvm_mips_fsub_w_RES
463 ; CHECK: fsub_w_test:
468 ; CHECK: .size fsub_w_test
470 define void @fsub_d_test() nounwind {
472 %0 = load <2 x double>* @llvm_mips_fsub_d_ARG1
473 %1 = load <2 x double>* @llvm_mips_fsub_d_ARG2
474 %2 = fsub <2 x double> %0, %1
475 store <2 x double> %2, <2 x double>* @llvm_mips_fsub_d_RES
479 ; CHECK: fsub_d_test:
484 ; CHECK: .size fsub_d_test