1 ; Test the MSA floating-point conversion intrinsics that are encoded with the
2 ; 3RF instruction format.
4 ; RUN: llc -march=mips -mattr=+msa < %s | FileCheck %s
6 @llvm_mips_fexdo_h_ARG1 = global <4 x float> <float 0.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00>, align 16
7 @llvm_mips_fexdo_h_ARG2 = global <4 x float> <float 4.000000e+00, float 5.000000e+00, float 6.000000e+00, float 7.000000e+00>, align 16
8 @llvm_mips_fexdo_h_RES = global <8 x half> <half 0.000000e+00, half 0.000000e+00, half 0.000000e+00, half 0.000000e+00, half 0.000000e+00, half 0.000000e+00, half 0.000000e+00, half 0.000000e+00>, align 16
10 define void @llvm_mips_fexdo_h_test() nounwind {
12 %0 = load <4 x float>* @llvm_mips_fexdo_h_ARG1
13 %1 = load <4 x float>* @llvm_mips_fexdo_h_ARG2
14 %2 = tail call <8 x half> @llvm.mips.fexdo.h(<4 x float> %0, <4 x float> %1)
15 store <8 x half> %2, <8 x half>* @llvm_mips_fexdo_h_RES
19 declare <8 x half> @llvm.mips.fexdo.h(<4 x float>, <4 x float>) nounwind
21 ; CHECK: llvm_mips_fexdo_h_test:
26 ; CHECK: .size llvm_mips_fexdo_h_test
28 @llvm_mips_fexdo_w_ARG1 = global <2 x double> <double 0.000000e+00, double 1.000000e+00>, align 16
29 @llvm_mips_fexdo_w_ARG2 = global <2 x double> <double 2.000000e+00, double 3.000000e+00>, align 16
30 @llvm_mips_fexdo_w_RES = global <4 x float> <float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00>, align 16
32 define void @llvm_mips_fexdo_w_test() nounwind {
34 %0 = load <2 x double>* @llvm_mips_fexdo_w_ARG1
35 %1 = load <2 x double>* @llvm_mips_fexdo_w_ARG2
36 %2 = tail call <4 x float> @llvm.mips.fexdo.w(<2 x double> %0, <2 x double> %1)
37 store <4 x float> %2, <4 x float>* @llvm_mips_fexdo_w_RES
41 declare <4 x float> @llvm.mips.fexdo.w(<2 x double>, <2 x double>) nounwind
43 ; CHECK: llvm_mips_fexdo_w_test:
48 ; CHECK: .size llvm_mips_fexdo_w_test