1 ; Test the MSA intrinsics that are encoded with the 3RF instruction format and
2 ; produce an integer as a result.
4 ; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s
6 @llvm_mips_fcaf_w_ARG1 = global <4 x float> <float 0.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00>, align 16
7 @llvm_mips_fcaf_w_ARG2 = global <4 x float> <float 4.000000e+00, float 5.000000e+00, float 6.000000e+00, float 7.000000e+00>, align 16
8 @llvm_mips_fcaf_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16
10 define void @llvm_mips_fcaf_w_test() nounwind {
12 %0 = load <4 x float>* @llvm_mips_fcaf_w_ARG1
13 %1 = load <4 x float>* @llvm_mips_fcaf_w_ARG2
14 %2 = tail call <4 x i32> @llvm.mips.fcaf.w(<4 x float> %0, <4 x float> %1)
15 store <4 x i32> %2, <4 x i32>* @llvm_mips_fcaf_w_RES
19 declare <4 x i32> @llvm.mips.fcaf.w(<4 x float>, <4 x float>) nounwind
21 ; CHECK: llvm_mips_fcaf_w_test:
26 ; CHECK: .size llvm_mips_fcaf_w_test
28 @llvm_mips_fcaf_d_ARG1 = global <2 x double> <double 0.000000e+00, double 1.000000e+00>, align 16
29 @llvm_mips_fcaf_d_ARG2 = global <2 x double> <double 2.000000e+00, double 3.000000e+00>, align 16
30 @llvm_mips_fcaf_d_RES = global <2 x i64> <i64 0, i64 0>, align 16
32 define void @llvm_mips_fcaf_d_test() nounwind {
34 %0 = load <2 x double>* @llvm_mips_fcaf_d_ARG1
35 %1 = load <2 x double>* @llvm_mips_fcaf_d_ARG2
36 %2 = tail call <2 x i64> @llvm.mips.fcaf.d(<2 x double> %0, <2 x double> %1)
37 store <2 x i64> %2, <2 x i64>* @llvm_mips_fcaf_d_RES
41 declare <2 x i64> @llvm.mips.fcaf.d(<2 x double>, <2 x double>) nounwind
43 ; CHECK: llvm_mips_fcaf_d_test:
48 ; CHECK: .size llvm_mips_fcaf_d_test
50 @llvm_mips_fceq_w_ARG1 = global <4 x float> <float 0.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00>, align 16
51 @llvm_mips_fceq_w_ARG2 = global <4 x float> <float 4.000000e+00, float 5.000000e+00, float 6.000000e+00, float 7.000000e+00>, align 16
52 @llvm_mips_fceq_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16
54 define void @llvm_mips_fceq_w_test() nounwind {
56 %0 = load <4 x float>* @llvm_mips_fceq_w_ARG1
57 %1 = load <4 x float>* @llvm_mips_fceq_w_ARG2
58 %2 = tail call <4 x i32> @llvm.mips.fceq.w(<4 x float> %0, <4 x float> %1)
59 store <4 x i32> %2, <4 x i32>* @llvm_mips_fceq_w_RES
63 declare <4 x i32> @llvm.mips.fceq.w(<4 x float>, <4 x float>) nounwind
65 ; CHECK: llvm_mips_fceq_w_test:
70 ; CHECK: .size llvm_mips_fceq_w_test
72 @llvm_mips_fceq_d_ARG1 = global <2 x double> <double 0.000000e+00, double 1.000000e+00>, align 16
73 @llvm_mips_fceq_d_ARG2 = global <2 x double> <double 2.000000e+00, double 3.000000e+00>, align 16
74 @llvm_mips_fceq_d_RES = global <2 x i64> <i64 0, i64 0>, align 16
76 define void @llvm_mips_fceq_d_test() nounwind {
78 %0 = load <2 x double>* @llvm_mips_fceq_d_ARG1
79 %1 = load <2 x double>* @llvm_mips_fceq_d_ARG2
80 %2 = tail call <2 x i64> @llvm.mips.fceq.d(<2 x double> %0, <2 x double> %1)
81 store <2 x i64> %2, <2 x i64>* @llvm_mips_fceq_d_RES
85 declare <2 x i64> @llvm.mips.fceq.d(<2 x double>, <2 x double>) nounwind
87 ; CHECK: llvm_mips_fceq_d_test:
92 ; CHECK: .size llvm_mips_fceq_d_test
94 @llvm_mips_fcle_w_ARG1 = global <4 x float> <float 0.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00>, align 16
95 @llvm_mips_fcle_w_ARG2 = global <4 x float> <float 4.000000e+00, float 5.000000e+00, float 6.000000e+00, float 7.000000e+00>, align 16
96 @llvm_mips_fcle_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16
98 define void @llvm_mips_fcle_w_test() nounwind {
100 %0 = load <4 x float>* @llvm_mips_fcle_w_ARG1
101 %1 = load <4 x float>* @llvm_mips_fcle_w_ARG2
102 %2 = tail call <4 x i32> @llvm.mips.fcle.w(<4 x float> %0, <4 x float> %1)
103 store <4 x i32> %2, <4 x i32>* @llvm_mips_fcle_w_RES
107 declare <4 x i32> @llvm.mips.fcle.w(<4 x float>, <4 x float>) nounwind
109 ; CHECK: llvm_mips_fcle_w_test:
114 ; CHECK: .size llvm_mips_fcle_w_test
116 @llvm_mips_fcle_d_ARG1 = global <2 x double> <double 0.000000e+00, double 1.000000e+00>, align 16
117 @llvm_mips_fcle_d_ARG2 = global <2 x double> <double 2.000000e+00, double 3.000000e+00>, align 16
118 @llvm_mips_fcle_d_RES = global <2 x i64> <i64 0, i64 0>, align 16
120 define void @llvm_mips_fcle_d_test() nounwind {
122 %0 = load <2 x double>* @llvm_mips_fcle_d_ARG1
123 %1 = load <2 x double>* @llvm_mips_fcle_d_ARG2
124 %2 = tail call <2 x i64> @llvm.mips.fcle.d(<2 x double> %0, <2 x double> %1)
125 store <2 x i64> %2, <2 x i64>* @llvm_mips_fcle_d_RES
129 declare <2 x i64> @llvm.mips.fcle.d(<2 x double>, <2 x double>) nounwind
131 ; CHECK: llvm_mips_fcle_d_test:
136 ; CHECK: .size llvm_mips_fcle_d_test
138 @llvm_mips_fclt_w_ARG1 = global <4 x float> <float 0.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00>, align 16
139 @llvm_mips_fclt_w_ARG2 = global <4 x float> <float 4.000000e+00, float 5.000000e+00, float 6.000000e+00, float 7.000000e+00>, align 16
140 @llvm_mips_fclt_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16
142 define void @llvm_mips_fclt_w_test() nounwind {
144 %0 = load <4 x float>* @llvm_mips_fclt_w_ARG1
145 %1 = load <4 x float>* @llvm_mips_fclt_w_ARG2
146 %2 = tail call <4 x i32> @llvm.mips.fclt.w(<4 x float> %0, <4 x float> %1)
147 store <4 x i32> %2, <4 x i32>* @llvm_mips_fclt_w_RES
151 declare <4 x i32> @llvm.mips.fclt.w(<4 x float>, <4 x float>) nounwind
153 ; CHECK: llvm_mips_fclt_w_test:
158 ; CHECK: .size llvm_mips_fclt_w_test
160 @llvm_mips_fclt_d_ARG1 = global <2 x double> <double 0.000000e+00, double 1.000000e+00>, align 16
161 @llvm_mips_fclt_d_ARG2 = global <2 x double> <double 2.000000e+00, double 3.000000e+00>, align 16
162 @llvm_mips_fclt_d_RES = global <2 x i64> <i64 0, i64 0>, align 16
164 define void @llvm_mips_fclt_d_test() nounwind {
166 %0 = load <2 x double>* @llvm_mips_fclt_d_ARG1
167 %1 = load <2 x double>* @llvm_mips_fclt_d_ARG2
168 %2 = tail call <2 x i64> @llvm.mips.fclt.d(<2 x double> %0, <2 x double> %1)
169 store <2 x i64> %2, <2 x i64>* @llvm_mips_fclt_d_RES
173 declare <2 x i64> @llvm.mips.fclt.d(<2 x double>, <2 x double>) nounwind
175 ; CHECK: llvm_mips_fclt_d_test:
180 ; CHECK: .size llvm_mips_fclt_d_test
182 @llvm_mips_fcor_w_ARG1 = global <4 x float> <float 0.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00>, align 16
183 @llvm_mips_fcor_w_ARG2 = global <4 x float> <float 4.000000e+00, float 5.000000e+00, float 6.000000e+00, float 7.000000e+00>, align 16
184 @llvm_mips_fcor_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16
186 define void @llvm_mips_fcor_w_test() nounwind {
188 %0 = load <4 x float>* @llvm_mips_fcor_w_ARG1
189 %1 = load <4 x float>* @llvm_mips_fcor_w_ARG2
190 %2 = tail call <4 x i32> @llvm.mips.fcor.w(<4 x float> %0, <4 x float> %1)
191 store <4 x i32> %2, <4 x i32>* @llvm_mips_fcor_w_RES
195 declare <4 x i32> @llvm.mips.fcor.w(<4 x float>, <4 x float>) nounwind
197 ; CHECK: llvm_mips_fcor_w_test:
202 ; CHECK: .size llvm_mips_fcor_w_test
204 @llvm_mips_fcor_d_ARG1 = global <2 x double> <double 0.000000e+00, double 1.000000e+00>, align 16
205 @llvm_mips_fcor_d_ARG2 = global <2 x double> <double 2.000000e+00, double 3.000000e+00>, align 16
206 @llvm_mips_fcor_d_RES = global <2 x i64> <i64 0, i64 0>, align 16
208 define void @llvm_mips_fcor_d_test() nounwind {
210 %0 = load <2 x double>* @llvm_mips_fcor_d_ARG1
211 %1 = load <2 x double>* @llvm_mips_fcor_d_ARG2
212 %2 = tail call <2 x i64> @llvm.mips.fcor.d(<2 x double> %0, <2 x double> %1)
213 store <2 x i64> %2, <2 x i64>* @llvm_mips_fcor_d_RES
217 declare <2 x i64> @llvm.mips.fcor.d(<2 x double>, <2 x double>) nounwind
219 ; CHECK: llvm_mips_fcor_d_test:
224 ; CHECK: .size llvm_mips_fcor_d_test
226 @llvm_mips_fcne_w_ARG1 = global <4 x float> <float 0.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00>, align 16
227 @llvm_mips_fcne_w_ARG2 = global <4 x float> <float 4.000000e+00, float 5.000000e+00, float 6.000000e+00, float 7.000000e+00>, align 16
228 @llvm_mips_fcne_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16
230 define void @llvm_mips_fcne_w_test() nounwind {
232 %0 = load <4 x float>* @llvm_mips_fcne_w_ARG1
233 %1 = load <4 x float>* @llvm_mips_fcne_w_ARG2
234 %2 = tail call <4 x i32> @llvm.mips.fcne.w(<4 x float> %0, <4 x float> %1)
235 store <4 x i32> %2, <4 x i32>* @llvm_mips_fcne_w_RES
239 declare <4 x i32> @llvm.mips.fcne.w(<4 x float>, <4 x float>) nounwind
241 ; CHECK: llvm_mips_fcne_w_test:
246 ; CHECK: .size llvm_mips_fcne_w_test
248 @llvm_mips_fcne_d_ARG1 = global <2 x double> <double 0.000000e+00, double 1.000000e+00>, align 16
249 @llvm_mips_fcne_d_ARG2 = global <2 x double> <double 2.000000e+00, double 3.000000e+00>, align 16
250 @llvm_mips_fcne_d_RES = global <2 x i64> <i64 0, i64 0>, align 16
252 define void @llvm_mips_fcne_d_test() nounwind {
254 %0 = load <2 x double>* @llvm_mips_fcne_d_ARG1
255 %1 = load <2 x double>* @llvm_mips_fcne_d_ARG2
256 %2 = tail call <2 x i64> @llvm.mips.fcne.d(<2 x double> %0, <2 x double> %1)
257 store <2 x i64> %2, <2 x i64>* @llvm_mips_fcne_d_RES
261 declare <2 x i64> @llvm.mips.fcne.d(<2 x double>, <2 x double>) nounwind
263 ; CHECK: llvm_mips_fcne_d_test:
268 ; CHECK: .size llvm_mips_fcne_d_test
270 @llvm_mips_fcueq_w_ARG1 = global <4 x float> <float 0.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00>, align 16
271 @llvm_mips_fcueq_w_ARG2 = global <4 x float> <float 4.000000e+00, float 5.000000e+00, float 6.000000e+00, float 7.000000e+00>, align 16
272 @llvm_mips_fcueq_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16
274 define void @llvm_mips_fcueq_w_test() nounwind {
276 %0 = load <4 x float>* @llvm_mips_fcueq_w_ARG1
277 %1 = load <4 x float>* @llvm_mips_fcueq_w_ARG2
278 %2 = tail call <4 x i32> @llvm.mips.fcueq.w(<4 x float> %0, <4 x float> %1)
279 store <4 x i32> %2, <4 x i32>* @llvm_mips_fcueq_w_RES
283 declare <4 x i32> @llvm.mips.fcueq.w(<4 x float>, <4 x float>) nounwind
285 ; CHECK: llvm_mips_fcueq_w_test:
290 ; CHECK: .size llvm_mips_fcueq_w_test
292 @llvm_mips_fcueq_d_ARG1 = global <2 x double> <double 0.000000e+00, double 1.000000e+00>, align 16
293 @llvm_mips_fcueq_d_ARG2 = global <2 x double> <double 2.000000e+00, double 3.000000e+00>, align 16
294 @llvm_mips_fcueq_d_RES = global <2 x i64> <i64 0, i64 0>, align 16
296 define void @llvm_mips_fcueq_d_test() nounwind {
298 %0 = load <2 x double>* @llvm_mips_fcueq_d_ARG1
299 %1 = load <2 x double>* @llvm_mips_fcueq_d_ARG2
300 %2 = tail call <2 x i64> @llvm.mips.fcueq.d(<2 x double> %0, <2 x double> %1)
301 store <2 x i64> %2, <2 x i64>* @llvm_mips_fcueq_d_RES
305 declare <2 x i64> @llvm.mips.fcueq.d(<2 x double>, <2 x double>) nounwind
307 ; CHECK: llvm_mips_fcueq_d_test:
312 ; CHECK: .size llvm_mips_fcueq_d_test
314 @llvm_mips_fcult_w_ARG1 = global <4 x float> <float 0.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00>, align 16
315 @llvm_mips_fcult_w_ARG2 = global <4 x float> <float 4.000000e+00, float 5.000000e+00, float 6.000000e+00, float 7.000000e+00>, align 16
316 @llvm_mips_fcult_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16
318 define void @llvm_mips_fcult_w_test() nounwind {
320 %0 = load <4 x float>* @llvm_mips_fcult_w_ARG1
321 %1 = load <4 x float>* @llvm_mips_fcult_w_ARG2
322 %2 = tail call <4 x i32> @llvm.mips.fcult.w(<4 x float> %0, <4 x float> %1)
323 store <4 x i32> %2, <4 x i32>* @llvm_mips_fcult_w_RES
327 declare <4 x i32> @llvm.mips.fcult.w(<4 x float>, <4 x float>) nounwind
329 ; CHECK: llvm_mips_fcult_w_test:
334 ; CHECK: .size llvm_mips_fcult_w_test
336 @llvm_mips_fcult_d_ARG1 = global <2 x double> <double 0.000000e+00, double 1.000000e+00>, align 16
337 @llvm_mips_fcult_d_ARG2 = global <2 x double> <double 2.000000e+00, double 3.000000e+00>, align 16
338 @llvm_mips_fcult_d_RES = global <2 x i64> <i64 0, i64 0>, align 16
340 define void @llvm_mips_fcult_d_test() nounwind {
342 %0 = load <2 x double>* @llvm_mips_fcult_d_ARG1
343 %1 = load <2 x double>* @llvm_mips_fcult_d_ARG2
344 %2 = tail call <2 x i64> @llvm.mips.fcult.d(<2 x double> %0, <2 x double> %1)
345 store <2 x i64> %2, <2 x i64>* @llvm_mips_fcult_d_RES
349 declare <2 x i64> @llvm.mips.fcult.d(<2 x double>, <2 x double>) nounwind
351 ; CHECK: llvm_mips_fcult_d_test:
356 ; CHECK: .size llvm_mips_fcult_d_test
358 @llvm_mips_fcule_w_ARG1 = global <4 x float> <float 0.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00>, align 16
359 @llvm_mips_fcule_w_ARG2 = global <4 x float> <float 4.000000e+00, float 5.000000e+00, float 6.000000e+00, float 7.000000e+00>, align 16
360 @llvm_mips_fcule_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16
362 define void @llvm_mips_fcule_w_test() nounwind {
364 %0 = load <4 x float>* @llvm_mips_fcule_w_ARG1
365 %1 = load <4 x float>* @llvm_mips_fcule_w_ARG2
366 %2 = tail call <4 x i32> @llvm.mips.fcule.w(<4 x float> %0, <4 x float> %1)
367 store <4 x i32> %2, <4 x i32>* @llvm_mips_fcule_w_RES
371 declare <4 x i32> @llvm.mips.fcule.w(<4 x float>, <4 x float>) nounwind
373 ; CHECK: llvm_mips_fcule_w_test:
378 ; CHECK: .size llvm_mips_fcule_w_test
380 @llvm_mips_fcule_d_ARG1 = global <2 x double> <double 0.000000e+00, double 1.000000e+00>, align 16
381 @llvm_mips_fcule_d_ARG2 = global <2 x double> <double 2.000000e+00, double 3.000000e+00>, align 16
382 @llvm_mips_fcule_d_RES = global <2 x i64> <i64 0, i64 0>, align 16
384 define void @llvm_mips_fcule_d_test() nounwind {
386 %0 = load <2 x double>* @llvm_mips_fcule_d_ARG1
387 %1 = load <2 x double>* @llvm_mips_fcule_d_ARG2
388 %2 = tail call <2 x i64> @llvm.mips.fcule.d(<2 x double> %0, <2 x double> %1)
389 store <2 x i64> %2, <2 x i64>* @llvm_mips_fcule_d_RES
393 declare <2 x i64> @llvm.mips.fcule.d(<2 x double>, <2 x double>) nounwind
395 ; CHECK: llvm_mips_fcule_d_test:
400 ; CHECK: .size llvm_mips_fcule_d_test
402 @llvm_mips_fcun_w_ARG1 = global <4 x float> <float 0.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00>, align 16
403 @llvm_mips_fcun_w_ARG2 = global <4 x float> <float 4.000000e+00, float 5.000000e+00, float 6.000000e+00, float 7.000000e+00>, align 16
404 @llvm_mips_fcun_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16
406 define void @llvm_mips_fcun_w_test() nounwind {
408 %0 = load <4 x float>* @llvm_mips_fcun_w_ARG1
409 %1 = load <4 x float>* @llvm_mips_fcun_w_ARG2
410 %2 = tail call <4 x i32> @llvm.mips.fcun.w(<4 x float> %0, <4 x float> %1)
411 store <4 x i32> %2, <4 x i32>* @llvm_mips_fcun_w_RES
415 declare <4 x i32> @llvm.mips.fcun.w(<4 x float>, <4 x float>) nounwind
417 ; CHECK: llvm_mips_fcun_w_test:
422 ; CHECK: .size llvm_mips_fcun_w_test
424 @llvm_mips_fcun_d_ARG1 = global <2 x double> <double 0.000000e+00, double 1.000000e+00>, align 16
425 @llvm_mips_fcun_d_ARG2 = global <2 x double> <double 2.000000e+00, double 3.000000e+00>, align 16
426 @llvm_mips_fcun_d_RES = global <2 x i64> <i64 0, i64 0>, align 16
428 define void @llvm_mips_fcun_d_test() nounwind {
430 %0 = load <2 x double>* @llvm_mips_fcun_d_ARG1
431 %1 = load <2 x double>* @llvm_mips_fcun_d_ARG2
432 %2 = tail call <2 x i64> @llvm.mips.fcun.d(<2 x double> %0, <2 x double> %1)
433 store <2 x i64> %2, <2 x i64>* @llvm_mips_fcun_d_RES
437 declare <2 x i64> @llvm.mips.fcun.d(<2 x double>, <2 x double>) nounwind
439 ; CHECK: llvm_mips_fcun_d_test:
444 ; CHECK: .size llvm_mips_fcun_d_test
446 @llvm_mips_fcune_w_ARG1 = global <4 x float> <float 0.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00>, align 16
447 @llvm_mips_fcune_w_ARG2 = global <4 x float> <float 4.000000e+00, float 5.000000e+00, float 6.000000e+00, float 7.000000e+00>, align 16
448 @llvm_mips_fcune_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16
450 define void @llvm_mips_fcune_w_test() nounwind {
452 %0 = load <4 x float>* @llvm_mips_fcune_w_ARG1
453 %1 = load <4 x float>* @llvm_mips_fcune_w_ARG2
454 %2 = tail call <4 x i32> @llvm.mips.fcune.w(<4 x float> %0, <4 x float> %1)
455 store <4 x i32> %2, <4 x i32>* @llvm_mips_fcune_w_RES
459 declare <4 x i32> @llvm.mips.fcune.w(<4 x float>, <4 x float>) nounwind
461 ; CHECK: llvm_mips_fcune_w_test:
466 ; CHECK: .size llvm_mips_fcune_w_test
468 @llvm_mips_fcune_d_ARG1 = global <2 x double> <double 0.000000e+00, double 1.000000e+00>, align 16
469 @llvm_mips_fcune_d_ARG2 = global <2 x double> <double 2.000000e+00, double 3.000000e+00>, align 16
470 @llvm_mips_fcune_d_RES = global <2 x i64> <i64 0, i64 0>, align 16
472 define void @llvm_mips_fcune_d_test() nounwind {
474 %0 = load <2 x double>* @llvm_mips_fcune_d_ARG1
475 %1 = load <2 x double>* @llvm_mips_fcune_d_ARG2
476 %2 = tail call <2 x i64> @llvm.mips.fcune.d(<2 x double> %0, <2 x double> %1)
477 store <2 x i64> %2, <2 x i64>* @llvm_mips_fcune_d_RES
481 declare <2 x i64> @llvm.mips.fcune.d(<2 x double>, <2 x double>) nounwind
483 ; CHECK: llvm_mips_fcune_d_test:
488 ; CHECK: .size llvm_mips_fcune_d_test
490 @llvm_mips_fsaf_w_ARG1 = global <4 x float> <float 0.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00>, align 16
491 @llvm_mips_fsaf_w_ARG2 = global <4 x float> <float 4.000000e+00, float 5.000000e+00, float 6.000000e+00, float 7.000000e+00>, align 16
492 @llvm_mips_fsaf_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16
494 define void @llvm_mips_fsaf_w_test() nounwind {
496 %0 = load <4 x float>* @llvm_mips_fsaf_w_ARG1
497 %1 = load <4 x float>* @llvm_mips_fsaf_w_ARG2
498 %2 = tail call <4 x i32> @llvm.mips.fsaf.w(<4 x float> %0, <4 x float> %1)
499 store <4 x i32> %2, <4 x i32>* @llvm_mips_fsaf_w_RES
503 declare <4 x i32> @llvm.mips.fsaf.w(<4 x float>, <4 x float>) nounwind
505 ; CHECK: llvm_mips_fsaf_w_test:
510 ; CHECK: .size llvm_mips_fsaf_w_test
512 @llvm_mips_fsaf_d_ARG1 = global <2 x double> <double 0.000000e+00, double 1.000000e+00>, align 16
513 @llvm_mips_fsaf_d_ARG2 = global <2 x double> <double 2.000000e+00, double 3.000000e+00>, align 16
514 @llvm_mips_fsaf_d_RES = global <2 x i64> <i64 0, i64 0>, align 16
516 define void @llvm_mips_fsaf_d_test() nounwind {
518 %0 = load <2 x double>* @llvm_mips_fsaf_d_ARG1
519 %1 = load <2 x double>* @llvm_mips_fsaf_d_ARG2
520 %2 = tail call <2 x i64> @llvm.mips.fsaf.d(<2 x double> %0, <2 x double> %1)
521 store <2 x i64> %2, <2 x i64>* @llvm_mips_fsaf_d_RES
525 declare <2 x i64> @llvm.mips.fsaf.d(<2 x double>, <2 x double>) nounwind
527 ; CHECK: llvm_mips_fsaf_d_test:
532 ; CHECK: .size llvm_mips_fsaf_d_test
534 @llvm_mips_fseq_w_ARG1 = global <4 x float> <float 0.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00>, align 16
535 @llvm_mips_fseq_w_ARG2 = global <4 x float> <float 4.000000e+00, float 5.000000e+00, float 6.000000e+00, float 7.000000e+00>, align 16
536 @llvm_mips_fseq_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16
538 define void @llvm_mips_fseq_w_test() nounwind {
540 %0 = load <4 x float>* @llvm_mips_fseq_w_ARG1
541 %1 = load <4 x float>* @llvm_mips_fseq_w_ARG2
542 %2 = tail call <4 x i32> @llvm.mips.fseq.w(<4 x float> %0, <4 x float> %1)
543 store <4 x i32> %2, <4 x i32>* @llvm_mips_fseq_w_RES
547 declare <4 x i32> @llvm.mips.fseq.w(<4 x float>, <4 x float>) nounwind
549 ; CHECK: llvm_mips_fseq_w_test:
554 ; CHECK: .size llvm_mips_fseq_w_test
556 @llvm_mips_fseq_d_ARG1 = global <2 x double> <double 0.000000e+00, double 1.000000e+00>, align 16
557 @llvm_mips_fseq_d_ARG2 = global <2 x double> <double 2.000000e+00, double 3.000000e+00>, align 16
558 @llvm_mips_fseq_d_RES = global <2 x i64> <i64 0, i64 0>, align 16
560 define void @llvm_mips_fseq_d_test() nounwind {
562 %0 = load <2 x double>* @llvm_mips_fseq_d_ARG1
563 %1 = load <2 x double>* @llvm_mips_fseq_d_ARG2
564 %2 = tail call <2 x i64> @llvm.mips.fseq.d(<2 x double> %0, <2 x double> %1)
565 store <2 x i64> %2, <2 x i64>* @llvm_mips_fseq_d_RES
569 declare <2 x i64> @llvm.mips.fseq.d(<2 x double>, <2 x double>) nounwind
571 ; CHECK: llvm_mips_fseq_d_test:
576 ; CHECK: .size llvm_mips_fseq_d_test
578 @llvm_mips_fsle_w_ARG1 = global <4 x float> <float 0.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00>, align 16
579 @llvm_mips_fsle_w_ARG2 = global <4 x float> <float 4.000000e+00, float 5.000000e+00, float 6.000000e+00, float 7.000000e+00>, align 16
580 @llvm_mips_fsle_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16
582 define void @llvm_mips_fsle_w_test() nounwind {
584 %0 = load <4 x float>* @llvm_mips_fsle_w_ARG1
585 %1 = load <4 x float>* @llvm_mips_fsle_w_ARG2
586 %2 = tail call <4 x i32> @llvm.mips.fsle.w(<4 x float> %0, <4 x float> %1)
587 store <4 x i32> %2, <4 x i32>* @llvm_mips_fsle_w_RES
591 declare <4 x i32> @llvm.mips.fsle.w(<4 x float>, <4 x float>) nounwind
593 ; CHECK: llvm_mips_fsle_w_test:
598 ; CHECK: .size llvm_mips_fsle_w_test
600 @llvm_mips_fsle_d_ARG1 = global <2 x double> <double 0.000000e+00, double 1.000000e+00>, align 16
601 @llvm_mips_fsle_d_ARG2 = global <2 x double> <double 2.000000e+00, double 3.000000e+00>, align 16
602 @llvm_mips_fsle_d_RES = global <2 x i64> <i64 0, i64 0>, align 16
604 define void @llvm_mips_fsle_d_test() nounwind {
606 %0 = load <2 x double>* @llvm_mips_fsle_d_ARG1
607 %1 = load <2 x double>* @llvm_mips_fsle_d_ARG2
608 %2 = tail call <2 x i64> @llvm.mips.fsle.d(<2 x double> %0, <2 x double> %1)
609 store <2 x i64> %2, <2 x i64>* @llvm_mips_fsle_d_RES
613 declare <2 x i64> @llvm.mips.fsle.d(<2 x double>, <2 x double>) nounwind
615 ; CHECK: llvm_mips_fsle_d_test:
620 ; CHECK: .size llvm_mips_fsle_d_test
622 @llvm_mips_fslt_w_ARG1 = global <4 x float> <float 0.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00>, align 16
623 @llvm_mips_fslt_w_ARG2 = global <4 x float> <float 4.000000e+00, float 5.000000e+00, float 6.000000e+00, float 7.000000e+00>, align 16
624 @llvm_mips_fslt_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16
626 define void @llvm_mips_fslt_w_test() nounwind {
628 %0 = load <4 x float>* @llvm_mips_fslt_w_ARG1
629 %1 = load <4 x float>* @llvm_mips_fslt_w_ARG2
630 %2 = tail call <4 x i32> @llvm.mips.fslt.w(<4 x float> %0, <4 x float> %1)
631 store <4 x i32> %2, <4 x i32>* @llvm_mips_fslt_w_RES
635 declare <4 x i32> @llvm.mips.fslt.w(<4 x float>, <4 x float>) nounwind
637 ; CHECK: llvm_mips_fslt_w_test:
642 ; CHECK: .size llvm_mips_fslt_w_test
644 @llvm_mips_fslt_d_ARG1 = global <2 x double> <double 0.000000e+00, double 1.000000e+00>, align 16
645 @llvm_mips_fslt_d_ARG2 = global <2 x double> <double 2.000000e+00, double 3.000000e+00>, align 16
646 @llvm_mips_fslt_d_RES = global <2 x i64> <i64 0, i64 0>, align 16
648 define void @llvm_mips_fslt_d_test() nounwind {
650 %0 = load <2 x double>* @llvm_mips_fslt_d_ARG1
651 %1 = load <2 x double>* @llvm_mips_fslt_d_ARG2
652 %2 = tail call <2 x i64> @llvm.mips.fslt.d(<2 x double> %0, <2 x double> %1)
653 store <2 x i64> %2, <2 x i64>* @llvm_mips_fslt_d_RES
657 declare <2 x i64> @llvm.mips.fslt.d(<2 x double>, <2 x double>) nounwind
659 ; CHECK: llvm_mips_fslt_d_test:
664 ; CHECK: .size llvm_mips_fslt_d_test
666 @llvm_mips_fsor_w_ARG1 = global <4 x float> <float 0.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00>, align 16
667 @llvm_mips_fsor_w_ARG2 = global <4 x float> <float 4.000000e+00, float 5.000000e+00, float 6.000000e+00, float 7.000000e+00>, align 16
668 @llvm_mips_fsor_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16
670 define void @llvm_mips_fsor_w_test() nounwind {
672 %0 = load <4 x float>* @llvm_mips_fsor_w_ARG1
673 %1 = load <4 x float>* @llvm_mips_fsor_w_ARG2
674 %2 = tail call <4 x i32> @llvm.mips.fsor.w(<4 x float> %0, <4 x float> %1)
675 store <4 x i32> %2, <4 x i32>* @llvm_mips_fsor_w_RES
679 declare <4 x i32> @llvm.mips.fsor.w(<4 x float>, <4 x float>) nounwind
681 ; CHECK: llvm_mips_fsor_w_test:
686 ; CHECK: .size llvm_mips_fsor_w_test
688 @llvm_mips_fsor_d_ARG1 = global <2 x double> <double 0.000000e+00, double 1.000000e+00>, align 16
689 @llvm_mips_fsor_d_ARG2 = global <2 x double> <double 2.000000e+00, double 3.000000e+00>, align 16
690 @llvm_mips_fsor_d_RES = global <2 x i64> <i64 0, i64 0>, align 16
692 define void @llvm_mips_fsor_d_test() nounwind {
694 %0 = load <2 x double>* @llvm_mips_fsor_d_ARG1
695 %1 = load <2 x double>* @llvm_mips_fsor_d_ARG2
696 %2 = tail call <2 x i64> @llvm.mips.fsor.d(<2 x double> %0, <2 x double> %1)
697 store <2 x i64> %2, <2 x i64>* @llvm_mips_fsor_d_RES
701 declare <2 x i64> @llvm.mips.fsor.d(<2 x double>, <2 x double>) nounwind
703 ; CHECK: llvm_mips_fsor_d_test:
708 ; CHECK: .size llvm_mips_fsor_d_test
710 @llvm_mips_fsne_w_ARG1 = global <4 x float> <float 0.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00>, align 16
711 @llvm_mips_fsne_w_ARG2 = global <4 x float> <float 4.000000e+00, float 5.000000e+00, float 6.000000e+00, float 7.000000e+00>, align 16
712 @llvm_mips_fsne_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16
714 define void @llvm_mips_fsne_w_test() nounwind {
716 %0 = load <4 x float>* @llvm_mips_fsne_w_ARG1
717 %1 = load <4 x float>* @llvm_mips_fsne_w_ARG2
718 %2 = tail call <4 x i32> @llvm.mips.fsne.w(<4 x float> %0, <4 x float> %1)
719 store <4 x i32> %2, <4 x i32>* @llvm_mips_fsne_w_RES
723 declare <4 x i32> @llvm.mips.fsne.w(<4 x float>, <4 x float>) nounwind
725 ; CHECK: llvm_mips_fsne_w_test:
730 ; CHECK: .size llvm_mips_fsne_w_test
732 @llvm_mips_fsne_d_ARG1 = global <2 x double> <double 0.000000e+00, double 1.000000e+00>, align 16
733 @llvm_mips_fsne_d_ARG2 = global <2 x double> <double 2.000000e+00, double 3.000000e+00>, align 16
734 @llvm_mips_fsne_d_RES = global <2 x i64> <i64 0, i64 0>, align 16
736 define void @llvm_mips_fsne_d_test() nounwind {
738 %0 = load <2 x double>* @llvm_mips_fsne_d_ARG1
739 %1 = load <2 x double>* @llvm_mips_fsne_d_ARG2
740 %2 = tail call <2 x i64> @llvm.mips.fsne.d(<2 x double> %0, <2 x double> %1)
741 store <2 x i64> %2, <2 x i64>* @llvm_mips_fsne_d_RES
745 declare <2 x i64> @llvm.mips.fsne.d(<2 x double>, <2 x double>) nounwind
747 ; CHECK: llvm_mips_fsne_d_test:
752 ; CHECK: .size llvm_mips_fsne_d_test
754 @llvm_mips_fsueq_w_ARG1 = global <4 x float> <float 0.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00>, align 16
755 @llvm_mips_fsueq_w_ARG2 = global <4 x float> <float 4.000000e+00, float 5.000000e+00, float 6.000000e+00, float 7.000000e+00>, align 16
756 @llvm_mips_fsueq_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16
758 define void @llvm_mips_fsueq_w_test() nounwind {
760 %0 = load <4 x float>* @llvm_mips_fsueq_w_ARG1
761 %1 = load <4 x float>* @llvm_mips_fsueq_w_ARG2
762 %2 = tail call <4 x i32> @llvm.mips.fsueq.w(<4 x float> %0, <4 x float> %1)
763 store <4 x i32> %2, <4 x i32>* @llvm_mips_fsueq_w_RES
767 declare <4 x i32> @llvm.mips.fsueq.w(<4 x float>, <4 x float>) nounwind
769 ; CHECK: llvm_mips_fsueq_w_test:
774 ; CHECK: .size llvm_mips_fsueq_w_test
776 @llvm_mips_fsueq_d_ARG1 = global <2 x double> <double 0.000000e+00, double 1.000000e+00>, align 16
777 @llvm_mips_fsueq_d_ARG2 = global <2 x double> <double 2.000000e+00, double 3.000000e+00>, align 16
778 @llvm_mips_fsueq_d_RES = global <2 x i64> <i64 0, i64 0>, align 16
780 define void @llvm_mips_fsueq_d_test() nounwind {
782 %0 = load <2 x double>* @llvm_mips_fsueq_d_ARG1
783 %1 = load <2 x double>* @llvm_mips_fsueq_d_ARG2
784 %2 = tail call <2 x i64> @llvm.mips.fsueq.d(<2 x double> %0, <2 x double> %1)
785 store <2 x i64> %2, <2 x i64>* @llvm_mips_fsueq_d_RES
789 declare <2 x i64> @llvm.mips.fsueq.d(<2 x double>, <2 x double>) nounwind
791 ; CHECK: llvm_mips_fsueq_d_test:
796 ; CHECK: .size llvm_mips_fsueq_d_test
798 @llvm_mips_fsult_w_ARG1 = global <4 x float> <float 0.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00>, align 16
799 @llvm_mips_fsult_w_ARG2 = global <4 x float> <float 4.000000e+00, float 5.000000e+00, float 6.000000e+00, float 7.000000e+00>, align 16
800 @llvm_mips_fsult_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16
802 define void @llvm_mips_fsult_w_test() nounwind {
804 %0 = load <4 x float>* @llvm_mips_fsult_w_ARG1
805 %1 = load <4 x float>* @llvm_mips_fsult_w_ARG2
806 %2 = tail call <4 x i32> @llvm.mips.fsult.w(<4 x float> %0, <4 x float> %1)
807 store <4 x i32> %2, <4 x i32>* @llvm_mips_fsult_w_RES
811 declare <4 x i32> @llvm.mips.fsult.w(<4 x float>, <4 x float>) nounwind
813 ; CHECK: llvm_mips_fsult_w_test:
818 ; CHECK: .size llvm_mips_fsult_w_test
820 @llvm_mips_fsult_d_ARG1 = global <2 x double> <double 0.000000e+00, double 1.000000e+00>, align 16
821 @llvm_mips_fsult_d_ARG2 = global <2 x double> <double 2.000000e+00, double 3.000000e+00>, align 16
822 @llvm_mips_fsult_d_RES = global <2 x i64> <i64 0, i64 0>, align 16
824 define void @llvm_mips_fsult_d_test() nounwind {
826 %0 = load <2 x double>* @llvm_mips_fsult_d_ARG1
827 %1 = load <2 x double>* @llvm_mips_fsult_d_ARG2
828 %2 = tail call <2 x i64> @llvm.mips.fsult.d(<2 x double> %0, <2 x double> %1)
829 store <2 x i64> %2, <2 x i64>* @llvm_mips_fsult_d_RES
833 declare <2 x i64> @llvm.mips.fsult.d(<2 x double>, <2 x double>) nounwind
835 ; CHECK: llvm_mips_fsult_d_test:
840 ; CHECK: .size llvm_mips_fsult_d_test
842 @llvm_mips_fsule_w_ARG1 = global <4 x float> <float 0.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00>, align 16
843 @llvm_mips_fsule_w_ARG2 = global <4 x float> <float 4.000000e+00, float 5.000000e+00, float 6.000000e+00, float 7.000000e+00>, align 16
844 @llvm_mips_fsule_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16
846 define void @llvm_mips_fsule_w_test() nounwind {
848 %0 = load <4 x float>* @llvm_mips_fsule_w_ARG1
849 %1 = load <4 x float>* @llvm_mips_fsule_w_ARG2
850 %2 = tail call <4 x i32> @llvm.mips.fsule.w(<4 x float> %0, <4 x float> %1)
851 store <4 x i32> %2, <4 x i32>* @llvm_mips_fsule_w_RES
855 declare <4 x i32> @llvm.mips.fsule.w(<4 x float>, <4 x float>) nounwind
857 ; CHECK: llvm_mips_fsule_w_test:
862 ; CHECK: .size llvm_mips_fsule_w_test
864 @llvm_mips_fsule_d_ARG1 = global <2 x double> <double 0.000000e+00, double 1.000000e+00>, align 16
865 @llvm_mips_fsule_d_ARG2 = global <2 x double> <double 2.000000e+00, double 3.000000e+00>, align 16
866 @llvm_mips_fsule_d_RES = global <2 x i64> <i64 0, i64 0>, align 16
868 define void @llvm_mips_fsule_d_test() nounwind {
870 %0 = load <2 x double>* @llvm_mips_fsule_d_ARG1
871 %1 = load <2 x double>* @llvm_mips_fsule_d_ARG2
872 %2 = tail call <2 x i64> @llvm.mips.fsule.d(<2 x double> %0, <2 x double> %1)
873 store <2 x i64> %2, <2 x i64>* @llvm_mips_fsule_d_RES
877 declare <2 x i64> @llvm.mips.fsule.d(<2 x double>, <2 x double>) nounwind
879 ; CHECK: llvm_mips_fsule_d_test:
884 ; CHECK: .size llvm_mips_fsule_d_test
886 @llvm_mips_fsun_w_ARG1 = global <4 x float> <float 0.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00>, align 16
887 @llvm_mips_fsun_w_ARG2 = global <4 x float> <float 4.000000e+00, float 5.000000e+00, float 6.000000e+00, float 7.000000e+00>, align 16
888 @llvm_mips_fsun_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16
890 define void @llvm_mips_fsun_w_test() nounwind {
892 %0 = load <4 x float>* @llvm_mips_fsun_w_ARG1
893 %1 = load <4 x float>* @llvm_mips_fsun_w_ARG2
894 %2 = tail call <4 x i32> @llvm.mips.fsun.w(<4 x float> %0, <4 x float> %1)
895 store <4 x i32> %2, <4 x i32>* @llvm_mips_fsun_w_RES
899 declare <4 x i32> @llvm.mips.fsun.w(<4 x float>, <4 x float>) nounwind
901 ; CHECK: llvm_mips_fsun_w_test:
906 ; CHECK: .size llvm_mips_fsun_w_test
908 @llvm_mips_fsun_d_ARG1 = global <2 x double> <double 0.000000e+00, double 1.000000e+00>, align 16
909 @llvm_mips_fsun_d_ARG2 = global <2 x double> <double 2.000000e+00, double 3.000000e+00>, align 16
910 @llvm_mips_fsun_d_RES = global <2 x i64> <i64 0, i64 0>, align 16
912 define void @llvm_mips_fsun_d_test() nounwind {
914 %0 = load <2 x double>* @llvm_mips_fsun_d_ARG1
915 %1 = load <2 x double>* @llvm_mips_fsun_d_ARG2
916 %2 = tail call <2 x i64> @llvm.mips.fsun.d(<2 x double> %0, <2 x double> %1)
917 store <2 x i64> %2, <2 x i64>* @llvm_mips_fsun_d_RES
921 declare <2 x i64> @llvm.mips.fsun.d(<2 x double>, <2 x double>) nounwind
923 ; CHECK: llvm_mips_fsun_d_test:
928 ; CHECK: .size llvm_mips_fsun_d_test
930 @llvm_mips_fsune_w_ARG1 = global <4 x float> <float 0.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00>, align 16
931 @llvm_mips_fsune_w_ARG2 = global <4 x float> <float 4.000000e+00, float 5.000000e+00, float 6.000000e+00, float 7.000000e+00>, align 16
932 @llvm_mips_fsune_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16
934 define void @llvm_mips_fsune_w_test() nounwind {
936 %0 = load <4 x float>* @llvm_mips_fsune_w_ARG1
937 %1 = load <4 x float>* @llvm_mips_fsune_w_ARG2
938 %2 = tail call <4 x i32> @llvm.mips.fsune.w(<4 x float> %0, <4 x float> %1)
939 store <4 x i32> %2, <4 x i32>* @llvm_mips_fsune_w_RES
943 declare <4 x i32> @llvm.mips.fsune.w(<4 x float>, <4 x float>) nounwind
945 ; CHECK: llvm_mips_fsune_w_test:
950 ; CHECK: .size llvm_mips_fsune_w_test
952 @llvm_mips_fsune_d_ARG1 = global <2 x double> <double 0.000000e+00, double 1.000000e+00>, align 16
953 @llvm_mips_fsune_d_ARG2 = global <2 x double> <double 2.000000e+00, double 3.000000e+00>, align 16
954 @llvm_mips_fsune_d_RES = global <2 x i64> <i64 0, i64 0>, align 16
956 define void @llvm_mips_fsune_d_test() nounwind {
958 %0 = load <2 x double>* @llvm_mips_fsune_d_ARG1
959 %1 = load <2 x double>* @llvm_mips_fsune_d_ARG2
960 %2 = tail call <2 x i64> @llvm.mips.fsune.d(<2 x double> %0, <2 x double> %1)
961 store <2 x i64> %2, <2 x i64>* @llvm_mips_fsune_d_RES
965 declare <2 x i64> @llvm.mips.fsune.d(<2 x double>, <2 x double>) nounwind
967 ; CHECK: llvm_mips_fsune_d_test:
972 ; CHECK: .size llvm_mips_fsune_d_test