1 ; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck -check-prefix=ALL -check-prefix=O32 -check-prefix=MIPS32 -check-prefix=ALL-BE %s
2 ; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | FileCheck -check-prefix=ALL -check-prefix=O32 -check-prefix=MIPS32 -check-prefix=ALL-LE %s
3 ; RUN: llc -march=mips64 -target-abi n32 -mattr=+msa,+fp64 < %s | FileCheck -check-prefix=ALL -check-prefix=N32 -check-prefix=MIPS64 -check-prefix=ALL-BE %s
4 ; RUN: llc -march=mips64el -target-abi n32 -mattr=+msa,+fp64 < %s | FileCheck -check-prefix=ALL -check-prefix=N32 -check-prefix=MIPS64 -check-prefix=ALL-LE %s
5 ; RUN: llc -march=mips64 -mattr=+msa,+fp64 < %s | FileCheck -check-prefix=ALL -check-prefix=N64 -check-prefix=MIPS64 -check-prefix=ALL-BE %s
6 ; RUN: llc -march=mips64el -mattr=+msa,+fp64 < %s | FileCheck -check-prefix=ALL -check-prefix=N64 -check-prefix=MIPS64 -check-prefix=ALL-LE %s
8 @v4i8 = global <4 x i8> <i8 0, i8 0, i8 0, i8 0>
9 @v16i8 = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>
10 @v8i16 = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>
11 @v4i32 = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>
12 @v2i64 = global <2 x i64> <i64 0, i64 0>
16 define void @const_v16i8() nounwind {
17 ; ALL-LABEL: const_v16i8:
19 store volatile <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, <16 x i8>*@v16i8
20 ; ALL: ldi.b [[R1:\$w[0-9]+]], 0
22 store volatile <16 x i8> <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>, <16 x i8>*@v16i8
23 ; ALL: ldi.b [[R1:\$w[0-9]+]], 1
25 store volatile <16 x i8> <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 31>, <16 x i8>*@v16i8
26 ; O32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($
27 ; N32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst($
28 ; N64: daddiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst($
29 ; ALL: ld.b [[R1:\$w[0-9]+]], 0([[G_PTR]])
31 store volatile <16 x i8> <i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6>, <16 x i8>*@v16i8
32 ; O32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($
33 ; N32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst($
34 ; N64: daddiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst($
35 ; ALL: ld.b [[R1:\$w[0-9]+]], 0([[G_PTR]])
37 store volatile <16 x i8> <i8 1, i8 0, i8 1, i8 0, i8 1, i8 0, i8 1, i8 0, i8 1, i8 0, i8 1, i8 0, i8 1, i8 0, i8 1, i8 0>, <16 x i8>*@v16i8
38 ; ALL-BE: ldi.h [[R1:\$w[0-9]+]], 256
39 ; ALL-LE: ldi.h [[R1:\$w[0-9]+]], 1
41 store volatile <16 x i8> <i8 1, i8 2, i8 3, i8 4, i8 1, i8 2, i8 3, i8 4, i8 1, i8 2, i8 3, i8 4, i8 1, i8 2, i8 3, i8 4>, <16 x i8>*@v16i8
42 ; ALL-BE-DAG: lui [[R2:\$[0-9]+]], 258
43 ; ALL-LE-DAG: lui [[R2:\$[0-9]+]], 1027
44 ; ALL-BE-DAG: ori [[R2]], [[R2]], 772
45 ; ALL-LE-DAG: ori [[R2]], [[R2]], 513
46 ; ALL-DAG: fill.w [[R1:\$w[0-9]+]], [[R2]]
48 store volatile <16 x i8> <i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8>, <16 x i8>*@v16i8
49 ; O32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($
50 ; N32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst($
51 ; N64: daddiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst($
52 ; ALL: ld.b [[R1:\$w[0-9]+]], 0([[G_PTR]])
57 define void @const_v8i16() nounwind {
58 ; ALL-LABEL: const_v8i16:
60 store volatile <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, <8 x i16>*@v8i16
61 ; ALL: ldi.b [[R1:\$w[0-9]+]], 0
63 store volatile <8 x i16> <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>, <8 x i16>*@v8i16
64 ; ALL: ldi.h [[R1:\$w[0-9]+]], 1
66 store volatile <8 x i16> <i16 1, i16 1, i16 1, i16 2, i16 1, i16 1, i16 1, i16 31>, <8 x i16>*@v8i16
67 ; O32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($
68 ; N32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst($
69 ; N64: daddiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst($
70 ; ALL: ld.h [[R1:\$w[0-9]+]], 0([[G_PTR]])
72 store volatile <8 x i16> <i16 1028, i16 1028, i16 1028, i16 1028, i16 1028, i16 1028, i16 1028, i16 1028>, <8 x i16>*@v8i16
73 ; ALL: ldi.b [[R1:\$w[0-9]+]], 4
75 store volatile <8 x i16> <i16 1, i16 2, i16 1, i16 2, i16 1, i16 2, i16 1, i16 2>, <8 x i16>*@v8i16
76 ; ALL-BE-DAG: lui [[R2:\$[0-9]+]], 1
77 ; ALL-LE-DAG: lui [[R2:\$[0-9]+]], 2
78 ; ALL-BE-DAG: ori [[R2]], [[R2]], 2
79 ; ALL-LE-DAG: ori [[R2]], [[R2]], 1
80 ; ALL-DAG: fill.w [[R1:\$w[0-9]+]], [[R2]]
82 store volatile <8 x i16> <i16 1, i16 2, i16 3, i16 4, i16 1, i16 2, i16 3, i16 4>, <8 x i16>*@v8i16
83 ; O32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($
84 ; N32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst($
85 ; N64: daddiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst($
86 ; ALL: ld.h [[R1:\$w[0-9]+]], 0([[G_PTR]])
91 define void @const_v4i32() nounwind {
92 ; ALL-LABEL: const_v4i32:
94 store volatile <4 x i32> <i32 0, i32 0, i32 0, i32 0>, <4 x i32>*@v4i32
95 ; ALL: ldi.b [[R1:\$w[0-9]+]], 0
97 store volatile <4 x i32> <i32 1, i32 1, i32 1, i32 1>, <4 x i32>*@v4i32
98 ; ALL: ldi.w [[R1:\$w[0-9]+]], 1
100 store volatile <4 x i32> <i32 1, i32 1, i32 1, i32 31>, <4 x i32>*@v4i32
101 ; O32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($
102 ; N32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst($
103 ; N64: daddiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst($
104 ; ALL: ld.w [[R1:\$w[0-9]+]], 0([[G_PTR]])
106 store volatile <4 x i32> <i32 16843009, i32 16843009, i32 16843009, i32 16843009>, <4 x i32>*@v4i32
107 ; ALL: ldi.b [[R1:\$w[0-9]+]], 1
109 store volatile <4 x i32> <i32 65537, i32 65537, i32 65537, i32 65537>, <4 x i32>*@v4i32
110 ; ALL: ldi.h [[R1:\$w[0-9]+]], 1
112 store volatile <4 x i32> <i32 1, i32 2, i32 1, i32 2>, <4 x i32>*@v4i32
113 ; O32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($
114 ; N32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst($
115 ; N64: daddiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst($
116 ; ALL: ld.w [[R1:\$w[0-9]+]], 0([[G_PTR]])
118 store volatile <4 x i32> <i32 3, i32 4, i32 5, i32 6>, <4 x i32>*@v4i32
119 ; O32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($
120 ; N32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst($
121 ; N64: daddiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst($
122 ; ALL: ld.w [[R1:\$w[0-9]+]], 0([[G_PTR]])
127 define void @const_v2i64() nounwind {
128 ; ALL-LABEL: const_v2i64:
130 store volatile <2 x i64> <i64 0, i64 0>, <2 x i64>*@v2i64
131 ; ALL: ldi.b [[R1:\$w[0-9]+]], 0
133 store volatile <2 x i64> <i64 72340172838076673, i64 72340172838076673>, <2 x i64>*@v2i64
134 ; ALL: ldi.b [[R1:\$w[0-9]+]], 1
136 store volatile <2 x i64> <i64 281479271743489, i64 281479271743489>, <2 x i64>*@v2i64
137 ; ALL: ldi.h [[R1:\$w[0-9]+]], 1
139 store volatile <2 x i64> <i64 4294967297, i64 4294967297>, <2 x i64>*@v2i64
140 ; ALL: ldi.w [[R1:\$w[0-9]+]], 1
142 store volatile <2 x i64> <i64 1, i64 1>, <2 x i64>*@v2i64
143 ; ALL: ldi.d [[R1:\$w[0-9]+]], 1
145 store volatile <2 x i64> <i64 1, i64 31>, <2 x i64>*@v2i64
146 ; O32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($
147 ; N32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst($
148 ; N64: daddiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst($
149 ; MIPS32: ld.w [[R1:\$w[0-9]+]], 0([[G_PTR]])
150 ; MIPS64: ld.d [[R1:\$w[0-9]+]], 0([[G_PTR]])
152 store volatile <2 x i64> <i64 3, i64 4>, <2 x i64>*@v2i64
153 ; O32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($
154 ; N32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst($
155 ; N64: daddiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst($
156 ; MIPS32: ld.w [[R1:\$w[0-9]+]], 0([[G_PTR]])
157 ; MIPS64: ld.d [[R1:\$w[0-9]+]], 0([[G_PTR]])
162 define void @nonconst_v16i8(i8 signext %a, i8 signext %b, i8 signext %c, i8 signext %d, i8 signext %e, i8 signext %f, i8 signext %g, i8 signext %h) nounwind {
163 ; ALL-LABEL: nonconst_v16i8:
165 %1 = insertelement <16 x i8> undef, i8 %a, i32 0
166 %2 = insertelement <16 x i8> %1, i8 %b, i32 1
167 %3 = insertelement <16 x i8> %2, i8 %c, i32 2
168 %4 = insertelement <16 x i8> %3, i8 %d, i32 3
169 %5 = insertelement <16 x i8> %4, i8 %e, i32 4
170 %6 = insertelement <16 x i8> %5, i8 %f, i32 5
171 %7 = insertelement <16 x i8> %6, i8 %g, i32 6
172 %8 = insertelement <16 x i8> %7, i8 %h, i32 7
173 %9 = insertelement <16 x i8> %8, i8 %h, i32 8
174 %10 = insertelement <16 x i8> %9, i8 %h, i32 9
175 %11 = insertelement <16 x i8> %10, i8 %h, i32 10
176 %12 = insertelement <16 x i8> %11, i8 %h, i32 11
177 %13 = insertelement <16 x i8> %12, i8 %h, i32 12
178 %14 = insertelement <16 x i8> %13, i8 %h, i32 13
179 %15 = insertelement <16 x i8> %14, i8 %h, i32 14
180 %16 = insertelement <16 x i8> %15, i8 %h, i32 15
181 ; ALL-DAG: insert.b [[R1:\$w[0-9]+]][0], $4
182 ; ALL-DAG: insert.b [[R1]][1], $5
183 ; ALL-DAG: insert.b [[R1]][2], $6
184 ; ALL-DAG: insert.b [[R1]][3], $7
185 ; MIPS32-DAG: lw [[R2:\$[0-9]+]], 16($sp)
186 ; MIPS32-DAG: insert.b [[R1]][4], [[R2]]
187 ; MIPS64-DAG: insert.b [[R1]][4], $8
188 ; MIPS32-DAG: lw [[R3:\$[0-9]+]], 20($sp)
189 ; MIPS32-DAG: insert.b [[R1]][5], [[R3]]
190 ; MIPS64-DAG: insert.b [[R1]][5], $9
191 ; MIPS32-DAG: lw [[R4:\$[0-9]+]], 24($sp)
192 ; MIPS32-DAG: insert.b [[R1]][6], [[R4]]
193 ; MIPS64-DAG: insert.b [[R1]][6], $10
194 ; MIPS32-DAG: lw [[R5:\$[0-9]+]], 28($sp)
195 ; MIPS32-DAG: insert.b [[R1]][7], [[R5]]
196 ; MIPS64-DAG: insert.b [[R1]][7], [[R5:\$11]]
197 ; ALL-DAG: insert.b [[R1]][8], [[R5]]
198 ; ALL-DAG: insert.b [[R1]][9], [[R5]]
199 ; ALL-DAG: insert.b [[R1]][10], [[R5]]
200 ; ALL-DAG: insert.b [[R1]][11], [[R5]]
201 ; ALL-DAG: insert.b [[R1]][12], [[R5]]
202 ; ALL-DAG: insert.b [[R1]][13], [[R5]]
203 ; ALL-DAG: insert.b [[R1]][14], [[R5]]
204 ; ALL-DAG: insert.b [[R1]][15], [[R5]]
206 store volatile <16 x i8> %16, <16 x i8>*@v16i8
211 define void @nonconst_v8i16(i16 signext %a, i16 signext %b, i16 signext %c, i16 signext %d, i16 signext %e, i16 signext %f, i16 signext %g, i16 signext %h) nounwind {
212 ; ALL-LABEL: nonconst_v8i16:
214 %1 = insertelement <8 x i16> undef, i16 %a, i32 0
215 %2 = insertelement <8 x i16> %1, i16 %b, i32 1
216 %3 = insertelement <8 x i16> %2, i16 %c, i32 2
217 %4 = insertelement <8 x i16> %3, i16 %d, i32 3
218 %5 = insertelement <8 x i16> %4, i16 %e, i32 4
219 %6 = insertelement <8 x i16> %5, i16 %f, i32 5
220 %7 = insertelement <8 x i16> %6, i16 %g, i32 6
221 %8 = insertelement <8 x i16> %7, i16 %h, i32 7
222 ; ALL-DAG: insert.h [[R1:\$w[0-9]+]][0], $4
223 ; ALL-DAG: insert.h [[R1]][1], $5
224 ; ALL-DAG: insert.h [[R1]][2], $6
225 ; ALL-DAG: insert.h [[R1]][3], $7
226 ; MIPS32-DAG: lw [[R2:\$[0-9]+]], 16($sp)
227 ; MIPS32-DAG: insert.h [[R1]][4], [[R2]]
228 ; MIPS64-DAG: insert.h [[R1]][4], $8
229 ; MIPS32-DAG: lw [[R2:\$[0-9]+]], 20($sp)
230 ; MIPS32-DAG: insert.h [[R1]][5], [[R2]]
231 ; MIPS64-DAG: insert.h [[R1]][5], $9
232 ; MIPS32-DAG: lw [[R2:\$[0-9]+]], 24($sp)
233 ; MIPS32-DAG: insert.h [[R1]][6], [[R2]]
234 ; MIPS64-DAG: insert.h [[R1]][6], $10
235 ; MIPS32-DAG: lw [[R2:\$[0-9]+]], 28($sp)
236 ; MIPS32-DAG: insert.h [[R1]][7], [[R2]]
237 ; MIPS64-DAG: insert.h [[R1]][7], $11
239 store volatile <8 x i16> %8, <8 x i16>*@v8i16
244 define void @nonconst_v4i32(i32 signext %a, i32 signext %b, i32 signext %c, i32 signext %d) nounwind {
245 ; ALL-LABEL: nonconst_v4i32:
247 %1 = insertelement <4 x i32> undef, i32 %a, i32 0
248 %2 = insertelement <4 x i32> %1, i32 %b, i32 1
249 %3 = insertelement <4 x i32> %2, i32 %c, i32 2
250 %4 = insertelement <4 x i32> %3, i32 %d, i32 3
251 ; ALL: insert.w [[R1:\$w[0-9]+]][0], $4
252 ; ALL: insert.w [[R1]][1], $5
253 ; ALL: insert.w [[R1]][2], $6
254 ; ALL: insert.w [[R1]][3], $7
256 store volatile <4 x i32> %4, <4 x i32>*@v4i32
261 define void @nonconst_v2i64(i64 signext %a, i64 signext %b) nounwind {
262 ; ALL-LABEL: nonconst_v2i64:
264 %1 = insertelement <2 x i64> undef, i64 %a, i32 0
265 %2 = insertelement <2 x i64> %1, i64 %b, i32 1
266 ; MIPS32: insert.w [[R1:\$w[0-9]+]][0], $4
267 ; MIPS32: insert.w [[R1]][1], $5
268 ; MIPS32: insert.w [[R1]][2], $6
269 ; MIPS32: insert.w [[R1]][3], $7
270 ; MIPS64: insert.d [[R1:\$w[0-9]+]][0], $4
271 ; MIPS64: insert.d [[R1]][1], $5
273 store volatile <2 x i64> %2, <2 x i64>*@v2i64
278 define i32 @extract_sext_v16i8() nounwind {
279 ; ALL-LABEL: extract_sext_v16i8:
281 %1 = load <16 x i8>, <16 x i8>* @v16i8
282 ; ALL-DAG: ld.b [[R1:\$w[0-9]+]],
284 %2 = add <16 x i8> %1, %1
285 ; ALL-DAG: addv.b [[R2:\$w[0-9]+]], [[R1]], [[R1]]
287 %3 = extractelement <16 x i8> %2, i32 1
288 %4 = sext i8 %3 to i32
289 ; ALL-DAG: copy_s.b [[R3:\$[0-9]+]], [[R1]][1]
296 define i32 @extract_sext_v8i16() nounwind {
297 ; ALL-LABEL: extract_sext_v8i16:
299 %1 = load <8 x i16>, <8 x i16>* @v8i16
300 ; ALL-DAG: ld.h [[R1:\$w[0-9]+]],
302 %2 = add <8 x i16> %1, %1
303 ; ALL-DAG: addv.h [[R2:\$w[0-9]+]], [[R1]], [[R1]]
305 %3 = extractelement <8 x i16> %2, i32 1
306 %4 = sext i16 %3 to i32
307 ; ALL-DAG: copy_s.h [[R3:\$[0-9]+]], [[R1]][1]
314 define i32 @extract_sext_v4i32() nounwind {
315 ; ALL-LABEL: extract_sext_v4i32:
317 %1 = load <4 x i32>, <4 x i32>* @v4i32
318 ; ALL-DAG: ld.w [[R1:\$w[0-9]+]],
320 %2 = add <4 x i32> %1, %1
321 ; ALL-DAG: addv.w [[R2:\$w[0-9]+]], [[R1]], [[R1]]
323 %3 = extractelement <4 x i32> %2, i32 1
324 ; ALL-DAG: copy_s.w [[R3:\$[0-9]+]], [[R1]][1]
329 define i64 @extract_sext_v2i64() nounwind {
330 ; ALL-LABEL: extract_sext_v2i64:
332 %1 = load <2 x i64>, <2 x i64>* @v2i64
333 ; ALL-DAG: ld.d [[R1:\$w[0-9]+]],
335 %2 = add <2 x i64> %1, %1
336 ; ALL-DAG: addv.d [[R2:\$w[0-9]+]], [[R1]], [[R1]]
338 %3 = extractelement <2 x i64> %2, i32 1
339 ; MIPS32-DAG: copy_s.w [[R3:\$[0-9]+]], [[R1]][2]
340 ; MIPS32-DAG: copy_s.w [[R4:\$[0-9]+]], [[R1]][3]
341 ; MIPS64-DAG: copy_s.d [[R3:\$[0-9]+]], [[R1]][1]
348 define i32 @extract_zext_v16i8() nounwind {
349 ; ALL-LABEL: extract_zext_v16i8:
351 %1 = load <16 x i8>, <16 x i8>* @v16i8
352 ; ALL-DAG: ld.b [[R1:\$w[0-9]+]],
354 %2 = add <16 x i8> %1, %1
355 ; ALL-DAG: addv.b [[R2:\$w[0-9]+]], [[R1]], [[R1]]
357 %3 = extractelement <16 x i8> %2, i32 1
358 %4 = zext i8 %3 to i32
359 ; ALL-DAG: copy_u.b [[R3:\$[0-9]+]], [[R1]][1]
365 define i32 @extract_zext_v8i16() nounwind {
366 ; ALL-LABEL: extract_zext_v8i16:
368 %1 = load <8 x i16>, <8 x i16>* @v8i16
369 ; ALL-DAG: ld.h [[R1:\$w[0-9]+]],
371 %2 = add <8 x i16> %1, %1
372 ; ALL-DAG: addv.h [[R2:\$w[0-9]+]], [[R1]], [[R1]]
374 %3 = extractelement <8 x i16> %2, i32 1
375 %4 = zext i16 %3 to i32
376 ; ALL-DAG: copy_u.h [[R3:\$[0-9]+]], [[R1]][1]
382 define i32 @extract_zext_v4i32() nounwind {
383 ; ALL-LABEL: extract_zext_v4i32:
385 %1 = load <4 x i32>, <4 x i32>* @v4i32
386 ; ALL-DAG: ld.w [[R1:\$w[0-9]+]],
388 %2 = add <4 x i32> %1, %1
389 ; ALL-DAG: addv.w [[R2:\$w[0-9]+]], [[R1]], [[R1]]
391 %3 = extractelement <4 x i32> %2, i32 1
392 ; ALL-DAG: copy_{{[su]}}.w [[R3:\$[0-9]+]], [[R1]][1]
397 define i64 @extract_zext_v2i64() nounwind {
398 ; ALL-LABEL: extract_zext_v2i64:
400 %1 = load <2 x i64>, <2 x i64>* @v2i64
401 ; ALL-DAG: ld.d [[R1:\$w[0-9]+]],
403 %2 = add <2 x i64> %1, %1
404 ; ALL-DAG: addv.d [[R2:\$w[0-9]+]], [[R1]], [[R1]]
406 %3 = extractelement <2 x i64> %2, i32 1
407 ; MIPS32-DAG: copy_{{[su]}}.w [[R3:\$[0-9]+]], [[R1]][2]
408 ; MIPS32-DAG: copy_{{[su]}}.w [[R4:\$[0-9]+]], [[R1]][3]
409 ; MIPS64-DAG: copy_{{[su]}}.d [[R3:\$[0-9]+]], [[R1]][1]
415 define i32 @extract_sext_v16i8_vidx() nounwind {
416 ; ALL-LABEL: extract_sext_v16i8_vidx:
418 %1 = load <16 x i8>, <16 x i8>* @v16i8
419 ; O32-DAG: lw [[PTR_V:\$[0-9]+]], %got(v16i8)(
420 ; N32-DAG: lw [[PTR_V:\$[0-9]+]], %got_disp(v16i8)(
421 ; N64-DAG: ld [[PTR_V:\$[0-9]+]], %got_disp(v16i8)(
422 ; ALL-DAG: ld.b [[R1:\$w[0-9]+]], 0([[PTR_V]])
424 %2 = add <16 x i8> %1, %1
425 ; ALL-DAG: addv.b [[R2:\$w[0-9]+]], [[R1]], [[R1]]
427 %3 = load i32, i32* @i32
428 ; O32-DAG: lw [[PTR_I:\$[0-9]+]], %got(i32)(
429 ; N32-DAG: lw [[PTR_I:\$[0-9]+]], %got_disp(i32)(
430 ; N64-DAG: ld [[PTR_I:\$[0-9]+]], %got_disp(i32)(
431 ; ALL-DAG: lw [[IDX:\$[0-9]+]], 0([[PTR_I]])
433 %4 = extractelement <16 x i8> %2, i32 %3
434 %5 = sext i8 %4 to i32
435 ; ALL-DAG: splat.b $w[[R3:[0-9]+]], [[R1]]{{\[}}[[IDX]]]
436 ; ALL-DAG: mfc1 [[R5:\$[0-9]+]], $f[[R3]]
437 ; ALL-DAG: sra [[R6:\$[0-9]+]], [[R5]], 24
442 define i32 @extract_sext_v8i16_vidx() nounwind {
443 ; ALL-LABEL: extract_sext_v8i16_vidx:
445 %1 = load <8 x i16>, <8 x i16>* @v8i16
446 ; O32-DAG: lw [[PTR_V:\$[0-9]+]], %got(v8i16)(
447 ; N32-DAG: lw [[PTR_V:\$[0-9]+]], %got_disp(v8i16)(
448 ; N64-DAG: ld [[PTR_V:\$[0-9]+]], %got_disp(v8i16)(
449 ; ALL-DAG: ld.h [[R1:\$w[0-9]+]], 0([[PTR_V]])
451 %2 = add <8 x i16> %1, %1
452 ; ALL-DAG: addv.h [[R2:\$w[0-9]+]], [[R1]], [[R1]]
454 %3 = load i32, i32* @i32
455 ; O32-DAG: lw [[PTR_I:\$[0-9]+]], %got(i32)(
456 ; N32-DAG: lw [[PTR_I:\$[0-9]+]], %got_disp(i32)(
457 ; N64-DAG: ld [[PTR_I:\$[0-9]+]], %got_disp(i32)(
458 ; ALL-DAG: lw [[IDX:\$[0-9]+]], 0([[PTR_I]])
460 %4 = extractelement <8 x i16> %2, i32 %3
461 %5 = sext i16 %4 to i32
462 ; ALL-DAG: splat.h $w[[R3:[0-9]+]], [[R1]]{{\[}}[[IDX]]]
463 ; ALL-DAG: mfc1 [[R5:\$[0-9]+]], $f[[R3]]
464 ; ALL-DAG: sra [[R6:\$[0-9]+]], [[R5]], 16
469 define i32 @extract_sext_v4i32_vidx() nounwind {
470 ; ALL-LABEL: extract_sext_v4i32_vidx:
472 %1 = load <4 x i32>, <4 x i32>* @v4i32
473 ; O32-DAG: lw [[PTR_V:\$[0-9]+]], %got(v4i32)(
474 ; N32-DAG: lw [[PTR_V:\$[0-9]+]], %got_disp(v4i32)(
475 ; N64-DAG: ld [[PTR_V:\$[0-9]+]], %got_disp(v4i32)(
476 ; ALL-DAG: ld.w [[R1:\$w[0-9]+]], 0([[PTR_V]])
478 %2 = add <4 x i32> %1, %1
479 ; ALL-DAG: addv.w [[R2:\$w[0-9]+]], [[R1]], [[R1]]
481 %3 = load i32, i32* @i32
482 ; O32-DAG: lw [[PTR_I:\$[0-9]+]], %got(i32)(
483 ; N32-DAG: lw [[PTR_I:\$[0-9]+]], %got_disp(i32)(
484 ; N64-DAG: ld [[PTR_I:\$[0-9]+]], %got_disp(i32)(
485 ; ALL-DAG: lw [[IDX:\$[0-9]+]], 0([[PTR_I]])
487 %4 = extractelement <4 x i32> %2, i32 %3
488 ; ALL-DAG: splat.w $w[[R3:[0-9]+]], [[R1]]{{\[}}[[IDX]]]
489 ; ALL-DAG: mfc1 [[R5:\$[0-9]+]], $f[[R3]]
495 define i64 @extract_sext_v2i64_vidx() nounwind {
496 ; ALL-LABEL: extract_sext_v2i64_vidx:
498 %1 = load <2 x i64>, <2 x i64>* @v2i64
499 ; O32-DAG: lw [[PTR_V:\$[0-9]+]], %got(v2i64)(
500 ; N32-DAG: lw [[PTR_V:\$[0-9]+]], %got_disp(v2i64)(
501 ; N64-DAG: ld [[PTR_V:\$[0-9]+]], %got_disp(v2i64)(
502 ; ALL-DAG: ld.d [[R1:\$w[0-9]+]], 0([[PTR_V]])
504 %2 = add <2 x i64> %1, %1
505 ; ALL-DAG: addv.d [[R2:\$w[0-9]+]], [[R1]], [[R1]]
507 %3 = load i32, i32* @i32
508 ; O32-DAG: lw [[PTR_I:\$[0-9]+]], %got(i32)(
509 ; N32-DAG: lw [[PTR_I:\$[0-9]+]], %got_disp(i32)(
510 ; N64-DAG: ld [[PTR_I:\$[0-9]+]], %got_disp(i32)(
511 ; ALL-DAG: lw [[IDX:\$[0-9]+]], 0([[PTR_I]])
513 %4 = extractelement <2 x i64> %2, i32 %3
514 ; MIPS32-DAG: splat.w $w[[R3:[0-9]+]], [[R1]]{{\[}}[[IDX]]]
515 ; MIPS32-DAG: mfc1 [[R5:\$[0-9]+]], $f[[R3]]
516 ; MIPS32-DAG: splat.w $w[[R4:[0-9]+]], [[R1]]{{\[}}[[IDX]]]
517 ; MIPS32-DAG: mfc1 [[R6:\$[0-9]+]], $f[[R4]]
518 ; MIPS64-DAG: splat.d $w[[R3:[0-9]+]], [[R1]]{{\[}}[[IDX]]]
519 ; MIPS64-DAG: dmfc1 [[R5:\$[0-9]+]], $f[[R3]]
525 define i32 @extract_zext_v16i8_vidx() nounwind {
526 ; ALL-LABEL: extract_zext_v16i8_vidx:
528 %1 = load <16 x i8>, <16 x i8>* @v16i8
529 ; O32-DAG: lw [[PTR_V:\$[0-9]+]], %got(v16i8)(
530 ; N32-DAG: lw [[PTR_V:\$[0-9]+]], %got_disp(v16i8)(
531 ; N64-DAG: ld [[PTR_V:\$[0-9]+]], %got_disp(v16i8)(
532 ; ALL-DAG: ld.b [[R1:\$w[0-9]+]], 0([[PTR_V]])
534 %2 = add <16 x i8> %1, %1
535 ; ALL-DAG: addv.b [[R2:\$w[0-9]+]], [[R1]], [[R1]]
537 %3 = load i32, i32* @i32
538 ; O32-DAG: lw [[PTR_I:\$[0-9]+]], %got(i32)(
539 ; N32-DAG: lw [[PTR_I:\$[0-9]+]], %got_disp(i32)(
540 ; N64-DAG: ld [[PTR_I:\$[0-9]+]], %got_disp(i32)(
541 ; ALL-DAG: lw [[IDX:\$[0-9]+]], 0([[PTR_I]])
543 %4 = extractelement <16 x i8> %2, i32 %3
544 %5 = zext i8 %4 to i32
545 ; ALL-DAG: splat.b $w[[R3:[0-9]+]], [[R1]]{{\[}}[[IDX]]]
546 ; ALL-DAG: mfc1 [[R5:\$[0-9]+]], $f[[R3]]
547 ; ALL-DAG: srl [[R6:\$[0-9]+]], [[R5]], 24
552 define i32 @extract_zext_v8i16_vidx() nounwind {
553 ; ALL-LABEL: extract_zext_v8i16_vidx:
555 %1 = load <8 x i16>, <8 x i16>* @v8i16
556 ; O32-DAG: lw [[PTR_V:\$[0-9]+]], %got(v8i16)(
557 ; N32-DAG: lw [[PTR_V:\$[0-9]+]], %got_disp(v8i16)(
558 ; N64-DAG: ld [[PTR_V:\$[0-9]+]], %got_disp(v8i16)(
559 ; ALL-DAG: ld.h [[R1:\$w[0-9]+]], 0([[PTR_V]])
561 %2 = add <8 x i16> %1, %1
562 ; ALL-DAG: addv.h [[R2:\$w[0-9]+]], [[R1]], [[R1]]
564 %3 = load i32, i32* @i32
565 ; O32-DAG: lw [[PTR_I:\$[0-9]+]], %got(i32)(
566 ; N32-DAG: lw [[PTR_I:\$[0-9]+]], %got_disp(i32)(
567 ; N64-DAG: ld [[PTR_I:\$[0-9]+]], %got_disp(i32)(
568 ; ALL-DAG: lw [[IDX:\$[0-9]+]], 0([[PTR_I]])
570 %4 = extractelement <8 x i16> %2, i32 %3
571 %5 = zext i16 %4 to i32
572 ; ALL-DAG: splat.h $w[[R3:[0-9]+]], [[R1]]{{\[}}[[IDX]]]
573 ; ALL-DAG: mfc1 [[R5:\$[0-9]+]], $f[[R3]]
574 ; ALL-DAG: srl [[R6:\$[0-9]+]], [[R5]], 16
579 define i32 @extract_zext_v4i32_vidx() nounwind {
580 ; ALL-LABEL: extract_zext_v4i32_vidx:
582 %1 = load <4 x i32>, <4 x i32>* @v4i32
583 ; O32-DAG: lw [[PTR_V:\$[0-9]+]], %got(v4i32)(
584 ; N32-DAG: lw [[PTR_V:\$[0-9]+]], %got_disp(v4i32)(
585 ; N64-DAG: ld [[PTR_V:\$[0-9]+]], %got_disp(v4i32)(
586 ; ALL-DAG: ld.w [[R1:\$w[0-9]+]], 0([[PTR_V]])
588 %2 = add <4 x i32> %1, %1
589 ; ALL-DAG: addv.w [[R2:\$w[0-9]+]], [[R1]], [[R1]]
591 %3 = load i32, i32* @i32
592 ; O32-DAG: lw [[PTR_I:\$[0-9]+]], %got(i32)(
593 ; N32-DAG: lw [[PTR_I:\$[0-9]+]], %got_disp(i32)(
594 ; N64-DAG: ld [[PTR_I:\$[0-9]+]], %got_disp(i32)(
595 ; ALL-DAG: lw [[IDX:\$[0-9]+]], 0([[PTR_I]])
597 %4 = extractelement <4 x i32> %2, i32 %3
598 ; ALL-DAG: splat.w $w[[R3:[0-9]+]], [[R1]]{{\[}}[[IDX]]]
599 ; ALL-DAG: mfc1 [[R5:\$[0-9]+]], $f[[R3]]
605 define i64 @extract_zext_v2i64_vidx() nounwind {
606 ; ALL-LABEL: extract_zext_v2i64_vidx:
608 %1 = load <2 x i64>, <2 x i64>* @v2i64
609 ; O32-DAG: lw [[PTR_V:\$[0-9]+]], %got(v2i64)(
610 ; N32-DAG: lw [[PTR_V:\$[0-9]+]], %got_disp(v2i64)(
611 ; N64-DAG: ld [[PTR_V:\$[0-9]+]], %got_disp(v2i64)(
612 ; ALL-DAG: ld.d [[R1:\$w[0-9]+]], 0([[PTR_V]])
614 %2 = add <2 x i64> %1, %1
615 ; ALL-DAG: addv.d [[R2:\$w[0-9]+]], [[R1]], [[R1]]
617 %3 = load i32, i32* @i32
618 ; O32-DAG: lw [[PTR_I:\$[0-9]+]], %got(i32)(
619 ; N32-DAG: lw [[PTR_I:\$[0-9]+]], %got_disp(i32)(
620 ; N64-DAG: ld [[PTR_I:\$[0-9]+]], %got_disp(i32)(
621 ; ALL-DAG: lw [[IDX:\$[0-9]+]], 0([[PTR_I]])
623 %4 = extractelement <2 x i64> %2, i32 %3
624 ; MIPS32-DAG: splat.w $w[[R3:[0-9]+]], [[R1]]{{\[}}[[IDX]]]
625 ; MIPS32-DAG: mfc1 [[R5:\$[0-9]+]], $f[[R3]]
626 ; MIPS32-DAG: splat.w $w[[R4:[0-9]+]], [[R1]]{{\[}}[[IDX]]]
627 ; MIPS32-DAG: mfc1 [[R6:\$[0-9]+]], $f[[R4]]
628 ; MIPS64-DAG: splat.d $w[[R3:[0-9]+]], [[R1]]{{\[}}[[IDX]]]
629 ; MIPS64-DAG: dmfc1 [[R5:\$[0-9]+]], $f[[R3]]
635 define void @insert_v16i8(i32 signext %a) nounwind {
636 ; ALL-LABEL: insert_v16i8:
638 %1 = load <16 x i8>, <16 x i8>* @v16i8
639 ; ALL-DAG: ld.b [[R1:\$w[0-9]+]],
641 %a2 = trunc i32 %a to i8
642 %a3 = sext i8 %a2 to i32
643 %a4 = trunc i32 %a3 to i8
647 %2 = insertelement <16 x i8> %1, i8 %a4, i32 1
648 ; ALL-DAG: insert.b [[R1]][1], $4
650 store <16 x i8> %2, <16 x i8>* @v16i8
651 ; ALL-DAG: st.b [[R1]]
656 define void @insert_v8i16(i32 signext %a) nounwind {
657 ; ALL-LABEL: insert_v8i16:
659 %1 = load <8 x i16>, <8 x i16>* @v8i16
660 ; ALL-DAG: ld.h [[R1:\$w[0-9]+]],
662 %a2 = trunc i32 %a to i16
663 %a3 = sext i16 %a2 to i32
664 %a4 = trunc i32 %a3 to i16
668 %2 = insertelement <8 x i16> %1, i16 %a4, i32 1
669 ; ALL-DAG: insert.h [[R1]][1], $4
671 store <8 x i16> %2, <8 x i16>* @v8i16
672 ; ALL-DAG: st.h [[R1]]
677 define void @insert_v4i32(i32 signext %a) nounwind {
678 ; ALL-LABEL: insert_v4i32:
680 %1 = load <4 x i32>, <4 x i32>* @v4i32
681 ; ALL-DAG: ld.w [[R1:\$w[0-9]+]],
686 %2 = insertelement <4 x i32> %1, i32 %a, i32 1
687 ; ALL-DAG: insert.w [[R1]][1], $4
689 store <4 x i32> %2, <4 x i32>* @v4i32
690 ; ALL-DAG: st.w [[R1]]
695 define void @insert_v2i64(i64 signext %a) nounwind {
696 ; ALL-LABEL: insert_v2i64:
698 %1 = load <2 x i64>, <2 x i64>* @v2i64
699 ; MIPS32-DAG: ld.w [[R1:\$w[0-9]+]],
700 ; MIPS64-DAG: ld.d [[R1:\$w[0-9]+]],
705 %2 = insertelement <2 x i64> %1, i64 %a, i32 1
706 ; MIPS32-DAG: insert.w [[R1]][2], $4
707 ; MIPS32-DAG: insert.w [[R1]][3], $5
708 ; MIPS64-DAG: insert.d [[R1]][1], $4
710 store <2 x i64> %2, <2 x i64>* @v2i64
711 ; MIPS32-DAG: st.w [[R1]]
712 ; MIPS64-DAG: st.d [[R1]]
717 define void @insert_v16i8_vidx(i32 signext %a) nounwind {
718 ; ALL-LABEL: insert_v16i8_vidx:
720 %1 = load <16 x i8>, <16 x i8>* @v16i8
721 ; ALL-DAG: ld.b [[R1:\$w[0-9]+]],
723 %2 = load i32, i32* @i32
724 ; O32-DAG: lw [[PTR_I:\$[0-9]+]], %got(i32)(
725 ; N32-DAG: lw [[PTR_I:\$[0-9]+]], %got_disp(i32)(
726 ; N64-DAG: ld [[PTR_I:\$[0-9]+]], %got_disp(i32)(
727 ; ALL-DAG: lw [[IDX:\$[0-9]+]], 0([[PTR_I]])
729 %a2 = trunc i32 %a to i8
730 %a3 = sext i8 %a2 to i32
731 %a4 = trunc i32 %a3 to i8
735 %3 = insertelement <16 x i8> %1, i8 %a4, i32 %2
736 ; ALL-DAG: sld.b [[R1]], [[R1]]{{\[}}[[IDX]]]
737 ; ALL-DAG: insert.b [[R1]][0], $4
738 ; O32-DAG: neg [[NIDX:\$[0-9]+]], [[IDX]]
739 ; N32-DAG: neg [[NIDX:\$[0-9]+]], [[IDX]]
740 ; N64-DAG: dneg [[NIDX:\$[0-9]+]], [[IDX]]
741 ; ALL-DAG: sld.b [[R1]], [[R1]]{{\[}}[[NIDX]]]
743 store <16 x i8> %3, <16 x i8>* @v16i8
744 ; ALL-DAG: st.b [[R1]]
749 define void @insert_v8i16_vidx(i32 signext %a) nounwind {
750 ; ALL-LABEL: insert_v8i16_vidx:
752 %1 = load <8 x i16>, <8 x i16>* @v8i16
753 ; ALL-DAG: ld.h [[R1:\$w[0-9]+]],
755 %2 = load i32, i32* @i32
756 ; O32-DAG: lw [[PTR_I:\$[0-9]+]], %got(i32)(
757 ; N32-DAG: lw [[PTR_I:\$[0-9]+]], %got_disp(i32)(
758 ; N64-DAG: ld [[PTR_I:\$[0-9]+]], %got_disp(i32)(
759 ; ALL-DAG: lw [[IDX:\$[0-9]+]], 0([[PTR_I]])
761 %a2 = trunc i32 %a to i16
762 %a3 = sext i16 %a2 to i32
763 %a4 = trunc i32 %a3 to i16
767 %3 = insertelement <8 x i16> %1, i16 %a4, i32 %2
768 ; ALL-DAG: sll [[BIDX:\$[0-9]+]], [[IDX]], 1
769 ; ALL-DAG: sld.b [[R1]], [[R1]]{{\[}}[[BIDX]]]
770 ; ALL-DAG: insert.h [[R1]][0], $4
771 ; O32-DAG: neg [[NIDX:\$[0-9]+]], [[BIDX]]
772 ; N32-DAG: neg [[NIDX:\$[0-9]+]], [[BIDX]]
773 ; N64-DAG: dneg [[NIDX:\$[0-9]+]], [[BIDX]]
774 ; ALL-DAG: sld.b [[R1]], [[R1]]{{\[}}[[NIDX]]]
776 store <8 x i16> %3, <8 x i16>* @v8i16
777 ; ALL-DAG: st.h [[R1]]
782 define void @insert_v4i32_vidx(i32 signext %a) nounwind {
783 ; ALL-LABEL: insert_v4i32_vidx:
785 %1 = load <4 x i32>, <4 x i32>* @v4i32
786 ; ALL-DAG: ld.w [[R1:\$w[0-9]+]],
788 %2 = load i32, i32* @i32
789 ; O32-DAG: lw [[PTR_I:\$[0-9]+]], %got(i32)(
790 ; N32-DAG: lw [[PTR_I:\$[0-9]+]], %got_disp(i32)(
791 ; N64-DAG: ld [[PTR_I:\$[0-9]+]], %got_disp(i32)(
792 ; ALL-DAG: lw [[IDX:\$[0-9]+]], 0([[PTR_I]])
797 %3 = insertelement <4 x i32> %1, i32 %a, i32 %2
798 ; ALL-DAG: sll [[BIDX:\$[0-9]+]], [[IDX]], 2
799 ; ALL-DAG: sld.b [[R1]], [[R1]]{{\[}}[[BIDX]]]
800 ; ALL-DAG: insert.w [[R1]][0], $4
801 ; O32-DAG: neg [[NIDX:\$[0-9]+]], [[BIDX]]
802 ; N32-DAG: neg [[NIDX:\$[0-9]+]], [[BIDX]]
803 ; N64-DAG: dneg [[NIDX:\$[0-9]+]], [[BIDX]]
804 ; ALL-DAG: sld.b [[R1]], [[R1]]{{\[}}[[NIDX]]]
806 store <4 x i32> %3, <4 x i32>* @v4i32
807 ; ALL-DAG: st.w [[R1]]
812 define void @insert_v2i64_vidx(i64 signext %a) nounwind {
813 ; ALL-LABEL: insert_v2i64_vidx:
815 %1 = load <2 x i64>, <2 x i64>* @v2i64
816 ; MIPS32-DAG: ld.w [[R1:\$w[0-9]+]],
817 ; MIPS64-DAG: ld.d [[R1:\$w[0-9]+]],
819 %2 = load i32, i32* @i32
820 ; O32-DAG: lw [[PTR_I:\$[0-9]+]], %got(i32)(
821 ; N32-DAG: lw [[PTR_I:\$[0-9]+]], %got_disp(i32)(
822 ; N64-DAG: ld [[PTR_I:\$[0-9]+]], %got_disp(i32)(
823 ; ALL-DAG: lw [[IDX:\$[0-9]+]], 0([[PTR_I]])
828 %3 = insertelement <2 x i64> %1, i64 %a, i32 %2
829 ; TODO: This code could be a lot better but it works. The legalizer splits
830 ; 64-bit inserts into two 32-bit inserts because there is no i64 type on
831 ; MIPS32. The obvious optimisation is to perform both insert.w's at once while
832 ; the vector is rotated.
833 ; MIPS32-DAG: sll [[BIDX:\$[0-9]+]], [[IDX]], 2
834 ; MIPS32-DAG: sld.b [[R1]], [[R1]]{{\[}}[[BIDX]]]
835 ; MIPS32-DAG: insert.w [[R1]][0], $4
836 ; MIPS32-DAG: neg [[NIDX:\$[0-9]+]], [[BIDX]]
837 ; MIPS32-DAG: sld.b [[R1]], [[R1]]{{\[}}[[NIDX]]]
838 ; MIPS32-DAG: addiu [[IDX2:\$[0-9]+]], [[IDX]], 1
839 ; MIPS32-DAG: sll [[BIDX:\$[0-9]+]], [[IDX2]], 2
840 ; MIPS32-DAG: sld.b [[R1]], [[R1]]{{\[}}[[BIDX]]]
841 ; MIPS32-DAG: insert.w [[R1]][0], $5
842 ; MIPS32-DAG: neg [[NIDX:\$[0-9]+]], [[BIDX]]
843 ; MIPS32-DAG: sld.b [[R1]], [[R1]]{{\[}}[[NIDX]]]
845 ; MIPS64-DAG: sll [[BIDX:\$[0-9]+]], [[IDX]], 3
846 ; MIPS64-DAG: sld.b [[R1]], [[R1]]{{\[}}[[BIDX]]]
847 ; MIPS64-DAG: insert.d [[R1]][0], $4
848 ; N32-DAG: neg [[NIDX:\$[0-9]+]], [[BIDX]]
849 ; N64-DAG: dneg [[NIDX:\$[0-9]+]], [[BIDX]]
850 ; MIPS64-DAG: sld.b [[R1]], [[R1]]{{\[}}[[NIDX]]]
852 store <2 x i64> %3, <2 x i64>* @v2i64
853 ; MIPS32-DAG: st.w [[R1]]
854 ; MIPS64-DAG: st.d [[R1]]
859 define void @truncstore() nounwind {
860 ; ALL-LABEL: truncstore:
862 store volatile <4 x i8> <i8 -1, i8 -1, i8 -1, i8 -1>, <4 x i8>*@v4i8
863 ; TODO: What code should be emitted?