1 ; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck -check-prefix=MIPS32 %s
2 ; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | FileCheck -check-prefix=MIPS32 %s
4 @v4f32 = global <4 x float> <float 0.0, float 0.0, float 0.0, float 0.0>
5 @v2f64 = global <2 x double> <double 0.0, double 0.0>
6 @f32 = global float 0.0
7 @f64 = global double 0.0
9 define void @const_v4f32() nounwind {
10 ; MIPS32: const_v4f32:
12 store volatile <4 x float> <float 0.0, float 0.0, float 0.0, float 0.0>, <4 x float>*@v4f32
13 ; MIPS32: ldi.b [[R1:\$w[0-9]+]], 0
15 store volatile <4 x float> <float 1.0, float 1.0, float 1.0, float 1.0>, <4 x float>*@v4f32
16 ; MIPS32: lui [[R1:\$[0-9]+]], 16256
17 ; MIPS32: fill.w [[R2:\$w[0-9]+]], [[R1]]
19 store volatile <4 x float> <float 1.0, float 1.0, float 1.0, float 31.0>, <4 x float>*@v4f32
20 ; MIPS32: ld.w [[R1:\$w[0-9]+]], %lo(
22 store volatile <4 x float> <float 65537.0, float 65537.0, float 65537.0, float 65537.0>, <4 x float>*@v4f32
23 ; MIPS32: lui [[R1:\$[0-9]+]], 18304
24 ; MIPS32: ori [[R2:\$[0-9]+]], [[R1]], 128
25 ; MIPS32: fill.w [[R3:\$w[0-9]+]], [[R2]]
27 store volatile <4 x float> <float 1.0, float 2.0, float 1.0, float 2.0>, <4 x float>*@v4f32
28 ; MIPS32: ld.w [[R1:\$w[0-9]+]], %lo(
30 store volatile <4 x float> <float 3.0, float 4.0, float 5.0, float 6.0>, <4 x float>*@v4f32
31 ; MIPS32: ld.w [[R1:\$w[0-9]+]], %lo(
34 ; MIPS32: .size const_v4f32
37 define void @const_v2f64() nounwind {
38 ; MIPS32: const_v2f64:
40 store volatile <2 x double> <double 0.0, double 0.0>, <2 x double>*@v2f64
41 ; MIPS32: ldi.b [[R1:\$w[0-9]+]], 0
43 store volatile <2 x double> <double 72340172838076673.0, double 72340172838076673.0>, <2 x double>*@v2f64
44 ; MIPS32: ld.d [[R1:\$w[0-9]+]], %lo(
46 store volatile <2 x double> <double 281479271743489.0, double 281479271743489.0>, <2 x double>*@v2f64
47 ; MIPS32: ld.d [[R1:\$w[0-9]+]], %lo(
49 store volatile <2 x double> <double 4294967297.0, double 4294967297.0>, <2 x double>*@v2f64
50 ; MIPS32: ld.d [[R1:\$w[0-9]+]], %lo(
52 store volatile <2 x double> <double 1.0, double 1.0>, <2 x double>*@v2f64
53 ; MIPS32: ld.d [[R1:\$w[0-9]+]], %lo(
55 store volatile <2 x double> <double 1.0, double 31.0>, <2 x double>*@v2f64
56 ; MIPS32: ld.d [[R1:\$w[0-9]+]], %lo(
58 store volatile <2 x double> <double 3.0, double 4.0>, <2 x double>*@v2f64
59 ; MIPS32: ld.d [[R1:\$w[0-9]+]], %lo(
62 ; MIPS32: .size const_v2f64
65 define void @nonconst_v4f32() nounwind {
66 ; MIPS32: nonconst_v4f32:
69 %2 = insertelement <4 x float> undef, float %1, i32 0
70 %3 = insertelement <4 x float> %2, float %1, i32 1
71 %4 = insertelement <4 x float> %3, float %1, i32 2
72 %5 = insertelement <4 x float> %4, float %1, i32 3
73 store volatile <4 x float> %5, <4 x float>*@v4f32
74 ; MIPS32: lwc1 $f[[R1:[0-9]+]], 0(
75 ; MIPS32: splati.w [[R2:\$w[0-9]+]], $w[[R1]]
78 ; MIPS32: .size nonconst_v4f32
81 define void @nonconst_v2f64() nounwind {
82 ; MIPS32: nonconst_v2f64:
84 %1 = load double *@f64
85 %2 = insertelement <2 x double> undef, double %1, i32 0
86 %3 = insertelement <2 x double> %2, double %1, i32 1
87 store volatile <2 x double> %3, <2 x double>*@v2f64
88 ; MIPS32: ldc1 $f[[R1:[0-9]+]], 0(
89 ; MIPS32: splati.d [[R2:\$w[0-9]+]], $w[[R1]]
92 ; MIPS32: .size nonconst_v2f64
95 define float @extract_v4f32() nounwind {
96 ; MIPS32: extract_v4f32:
98 %1 = load <4 x float>* @v4f32
99 ; MIPS32-DAG: ld.w [[R1:\$w[0-9]+]],
101 %2 = fadd <4 x float> %1, %1
102 ; MIPS32-DAG: fadd.w [[R2:\$w[0-9]+]], [[R1]], [[R1]]
104 %3 = extractelement <4 x float> %2, i32 1
105 ; Element 1 can be obtained by splatting it across the vector and extracting
107 ; MIPS32-DAG: splati.w $w0, [[R1]][1]
110 ; MIPS32: .size extract_v4f32
113 define float @extract_v4f32_elt0() nounwind {
114 ; MIPS32: extract_v4f32_elt0:
116 %1 = load <4 x float>* @v4f32
117 ; MIPS32-DAG: ld.w [[R1:\$w[0-9]+]],
119 %2 = fadd <4 x float> %1, %1
120 ; MIPS32-DAG: fadd.w $w0, [[R1]], [[R1]]
122 %3 = extractelement <4 x float> %2, i32 0
123 ; Element 0 can be obtained by extracting $w0:sub_lo ($f0)
124 ; MIPS32-NOT: copy_u.w
128 ; MIPS32: .size extract_v4f32_elt0
131 define double @extract_v2f64() nounwind {
132 ; MIPS32: extract_v2f64:
134 %1 = load <2 x double>* @v2f64
135 ; MIPS32-DAG: ld.d [[R1:\$w[0-9]+]],
137 %2 = fadd <2 x double> %1, %1
138 ; MIPS32-DAG: fadd.d [[R2:\$w[0-9]+]], [[R1]], [[R1]]
140 %3 = extractelement <2 x double> %2, i32 1
141 ; Element 1 can be obtained by splatting it across the vector and extracting
143 ; MIPS32-DAG: splati.d $w0, [[R1]][1]
144 ; MIPS32-NOT: copy_u.w
151 ; MIPS32: .size extract_v2f64
154 define double @extract_v2f64_elt0() nounwind {
155 ; MIPS32: extract_v2f64_elt0:
157 %1 = load <2 x double>* @v2f64
158 ; MIPS32-DAG: ld.d [[R1:\$w[0-9]+]],
160 %2 = fadd <2 x double> %1, %1
161 ; MIPS32-DAG: fadd.d $w0, [[R1]], [[R1]]
163 %3 = extractelement <2 x double> %2, i32 0
164 ; Element 0 can be obtained by extracting $w0:sub_64 ($f0)
165 ; MIPS32-NOT: copy_u.w
172 ; MIPS32: .size extract_v2f64_elt0
175 define void @insert_v4f32(float %a) nounwind {
176 ; MIPS32: insert_v4f32:
178 %1 = load <4 x float>* @v4f32
179 ; MIPS32-DAG: ld.w [[R1:\$w[0-9]+]],
181 %2 = insertelement <4 x float> %1, float %a, i32 1
182 ; float argument passed in $f12
183 ; MIPS32-DAG: insve.w [[R1]][1], $w12[0]
185 store <4 x float> %2, <4 x float>* @v4f32
186 ; MIPS32-DAG: st.w [[R1]]
189 ; MIPS32: .size insert_v4f32
192 define void @insert_v2f64(double %a) nounwind {
193 ; MIPS32: insert_v2f64:
195 %1 = load <2 x double>* @v2f64
196 ; MIPS32-DAG: ld.d [[R1:\$w[0-9]+]],
198 %2 = insertelement <2 x double> %1, double %a, i32 1
199 ; double argument passed in $f12
200 ; MIPS32-DAG: insve.d [[R1]][1], $w12[0]
202 store <2 x double> %2, <2 x double>* @v2f64
203 ; MIPS32-DAG: st.d [[R1]]
206 ; MIPS32: .size insert_v2f64