1 ; Test the MSA intrinsics that are encoded with the BIT instruction format.
3 ; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s
5 @llvm_mips_sat_s_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
6 @llvm_mips_sat_s_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16
8 define void @llvm_mips_sat_s_b_test() nounwind {
10 %0 = load <16 x i8>* @llvm_mips_sat_s_b_ARG1
11 %1 = tail call <16 x i8> @llvm.mips.sat.s.b(<16 x i8> %0, i32 7)
12 store <16 x i8> %1, <16 x i8>* @llvm_mips_sat_s_b_RES
16 declare <16 x i8> @llvm.mips.sat.s.b(<16 x i8>, i32) nounwind
18 ; CHECK: llvm_mips_sat_s_b_test:
22 ; CHECK: .size llvm_mips_sat_s_b_test
24 @llvm_mips_sat_s_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16
25 @llvm_mips_sat_s_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16
27 define void @llvm_mips_sat_s_h_test() nounwind {
29 %0 = load <8 x i16>* @llvm_mips_sat_s_h_ARG1
30 %1 = tail call <8 x i16> @llvm.mips.sat.s.h(<8 x i16> %0, i32 7)
31 store <8 x i16> %1, <8 x i16>* @llvm_mips_sat_s_h_RES
35 declare <8 x i16> @llvm.mips.sat.s.h(<8 x i16>, i32) nounwind
37 ; CHECK: llvm_mips_sat_s_h_test:
41 ; CHECK: .size llvm_mips_sat_s_h_test
43 @llvm_mips_sat_s_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16
44 @llvm_mips_sat_s_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16
46 define void @llvm_mips_sat_s_w_test() nounwind {
48 %0 = load <4 x i32>* @llvm_mips_sat_s_w_ARG1
49 %1 = tail call <4 x i32> @llvm.mips.sat.s.w(<4 x i32> %0, i32 7)
50 store <4 x i32> %1, <4 x i32>* @llvm_mips_sat_s_w_RES
54 declare <4 x i32> @llvm.mips.sat.s.w(<4 x i32>, i32) nounwind
56 ; CHECK: llvm_mips_sat_s_w_test:
60 ; CHECK: .size llvm_mips_sat_s_w_test
62 @llvm_mips_sat_s_d_ARG1 = global <2 x i64> <i64 0, i64 1>, align 16
63 @llvm_mips_sat_s_d_RES = global <2 x i64> <i64 0, i64 0>, align 16
65 define void @llvm_mips_sat_s_d_test() nounwind {
67 %0 = load <2 x i64>* @llvm_mips_sat_s_d_ARG1
68 %1 = tail call <2 x i64> @llvm.mips.sat.s.d(<2 x i64> %0, i32 7)
69 store <2 x i64> %1, <2 x i64>* @llvm_mips_sat_s_d_RES
73 declare <2 x i64> @llvm.mips.sat.s.d(<2 x i64>, i32) nounwind
75 ; CHECK: llvm_mips_sat_s_d_test:
79 ; CHECK: .size llvm_mips_sat_s_d_test
81 @llvm_mips_sat_u_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
82 @llvm_mips_sat_u_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16
84 define void @llvm_mips_sat_u_b_test() nounwind {
86 %0 = load <16 x i8>* @llvm_mips_sat_u_b_ARG1
87 %1 = tail call <16 x i8> @llvm.mips.sat.u.b(<16 x i8> %0, i32 7)
88 store <16 x i8> %1, <16 x i8>* @llvm_mips_sat_u_b_RES
92 declare <16 x i8> @llvm.mips.sat.u.b(<16 x i8>, i32) nounwind
94 ; CHECK: llvm_mips_sat_u_b_test:
98 ; CHECK: .size llvm_mips_sat_u_b_test
100 @llvm_mips_sat_u_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16
101 @llvm_mips_sat_u_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16
103 define void @llvm_mips_sat_u_h_test() nounwind {
105 %0 = load <8 x i16>* @llvm_mips_sat_u_h_ARG1
106 %1 = tail call <8 x i16> @llvm.mips.sat.u.h(<8 x i16> %0, i32 7)
107 store <8 x i16> %1, <8 x i16>* @llvm_mips_sat_u_h_RES
111 declare <8 x i16> @llvm.mips.sat.u.h(<8 x i16>, i32) nounwind
113 ; CHECK: llvm_mips_sat_u_h_test:
117 ; CHECK: .size llvm_mips_sat_u_h_test
119 @llvm_mips_sat_u_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16
120 @llvm_mips_sat_u_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16
122 define void @llvm_mips_sat_u_w_test() nounwind {
124 %0 = load <4 x i32>* @llvm_mips_sat_u_w_ARG1
125 %1 = tail call <4 x i32> @llvm.mips.sat.u.w(<4 x i32> %0, i32 7)
126 store <4 x i32> %1, <4 x i32>* @llvm_mips_sat_u_w_RES
130 declare <4 x i32> @llvm.mips.sat.u.w(<4 x i32>, i32) nounwind
132 ; CHECK: llvm_mips_sat_u_w_test:
136 ; CHECK: .size llvm_mips_sat_u_w_test
138 @llvm_mips_sat_u_d_ARG1 = global <2 x i64> <i64 0, i64 1>, align 16
139 @llvm_mips_sat_u_d_RES = global <2 x i64> <i64 0, i64 0>, align 16
141 define void @llvm_mips_sat_u_d_test() nounwind {
143 %0 = load <2 x i64>* @llvm_mips_sat_u_d_ARG1
144 %1 = tail call <2 x i64> @llvm.mips.sat.u.d(<2 x i64> %0, i32 7)
145 store <2 x i64> %1, <2 x i64>* @llvm_mips_sat_u_d_RES
149 declare <2 x i64> @llvm.mips.sat.u.d(<2 x i64>, i32) nounwind
151 ; CHECK: llvm_mips_sat_u_d_test:
155 ; CHECK: .size llvm_mips_sat_u_d_test
157 @llvm_mips_slli_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
158 @llvm_mips_slli_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16
160 define void @llvm_mips_slli_b_test() nounwind {
162 %0 = load <16 x i8>* @llvm_mips_slli_b_ARG1
163 %1 = tail call <16 x i8> @llvm.mips.slli.b(<16 x i8> %0, i32 7)
164 store <16 x i8> %1, <16 x i8>* @llvm_mips_slli_b_RES
168 declare <16 x i8> @llvm.mips.slli.b(<16 x i8>, i32) nounwind
170 ; CHECK: llvm_mips_slli_b_test:
174 ; CHECK: .size llvm_mips_slli_b_test
176 @llvm_mips_slli_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16
177 @llvm_mips_slli_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16
179 define void @llvm_mips_slli_h_test() nounwind {
181 %0 = load <8 x i16>* @llvm_mips_slli_h_ARG1
182 %1 = tail call <8 x i16> @llvm.mips.slli.h(<8 x i16> %0, i32 7)
183 store <8 x i16> %1, <8 x i16>* @llvm_mips_slli_h_RES
187 declare <8 x i16> @llvm.mips.slli.h(<8 x i16>, i32) nounwind
189 ; CHECK: llvm_mips_slli_h_test:
193 ; CHECK: .size llvm_mips_slli_h_test
195 @llvm_mips_slli_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16
196 @llvm_mips_slli_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16
198 define void @llvm_mips_slli_w_test() nounwind {
200 %0 = load <4 x i32>* @llvm_mips_slli_w_ARG1
201 %1 = tail call <4 x i32> @llvm.mips.slli.w(<4 x i32> %0, i32 7)
202 store <4 x i32> %1, <4 x i32>* @llvm_mips_slli_w_RES
206 declare <4 x i32> @llvm.mips.slli.w(<4 x i32>, i32) nounwind
208 ; CHECK: llvm_mips_slli_w_test:
212 ; CHECK: .size llvm_mips_slli_w_test
214 @llvm_mips_slli_d_ARG1 = global <2 x i64> <i64 0, i64 1>, align 16
215 @llvm_mips_slli_d_RES = global <2 x i64> <i64 0, i64 0>, align 16
217 define void @llvm_mips_slli_d_test() nounwind {
219 %0 = load <2 x i64>* @llvm_mips_slli_d_ARG1
220 %1 = tail call <2 x i64> @llvm.mips.slli.d(<2 x i64> %0, i32 7)
221 store <2 x i64> %1, <2 x i64>* @llvm_mips_slli_d_RES
225 declare <2 x i64> @llvm.mips.slli.d(<2 x i64>, i32) nounwind
227 ; CHECK: llvm_mips_slli_d_test:
231 ; CHECK: .size llvm_mips_slli_d_test
233 @llvm_mips_srai_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
234 @llvm_mips_srai_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16
236 define void @llvm_mips_srai_b_test() nounwind {
238 %0 = load <16 x i8>* @llvm_mips_srai_b_ARG1
239 %1 = tail call <16 x i8> @llvm.mips.srai.b(<16 x i8> %0, i32 7)
240 store <16 x i8> %1, <16 x i8>* @llvm_mips_srai_b_RES
244 declare <16 x i8> @llvm.mips.srai.b(<16 x i8>, i32) nounwind
246 ; CHECK: llvm_mips_srai_b_test:
250 ; CHECK: .size llvm_mips_srai_b_test
252 @llvm_mips_srai_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16
253 @llvm_mips_srai_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16
255 define void @llvm_mips_srai_h_test() nounwind {
257 %0 = load <8 x i16>* @llvm_mips_srai_h_ARG1
258 %1 = tail call <8 x i16> @llvm.mips.srai.h(<8 x i16> %0, i32 7)
259 store <8 x i16> %1, <8 x i16>* @llvm_mips_srai_h_RES
263 declare <8 x i16> @llvm.mips.srai.h(<8 x i16>, i32) nounwind
265 ; CHECK: llvm_mips_srai_h_test:
269 ; CHECK: .size llvm_mips_srai_h_test
271 @llvm_mips_srai_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16
272 @llvm_mips_srai_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16
274 define void @llvm_mips_srai_w_test() nounwind {
276 %0 = load <4 x i32>* @llvm_mips_srai_w_ARG1
277 %1 = tail call <4 x i32> @llvm.mips.srai.w(<4 x i32> %0, i32 7)
278 store <4 x i32> %1, <4 x i32>* @llvm_mips_srai_w_RES
282 declare <4 x i32> @llvm.mips.srai.w(<4 x i32>, i32) nounwind
284 ; CHECK: llvm_mips_srai_w_test:
288 ; CHECK: .size llvm_mips_srai_w_test
290 @llvm_mips_srai_d_ARG1 = global <2 x i64> <i64 0, i64 1>, align 16
291 @llvm_mips_srai_d_RES = global <2 x i64> <i64 0, i64 0>, align 16
293 define void @llvm_mips_srai_d_test() nounwind {
295 %0 = load <2 x i64>* @llvm_mips_srai_d_ARG1
296 %1 = tail call <2 x i64> @llvm.mips.srai.d(<2 x i64> %0, i32 7)
297 store <2 x i64> %1, <2 x i64>* @llvm_mips_srai_d_RES
301 declare <2 x i64> @llvm.mips.srai.d(<2 x i64>, i32) nounwind
303 ; CHECK: llvm_mips_srai_d_test:
307 ; CHECK: .size llvm_mips_srai_d_test
309 @llvm_mips_srari_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
310 @llvm_mips_srari_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16
312 define void @llvm_mips_srari_b_test() nounwind {
314 %0 = load <16 x i8>* @llvm_mips_srari_b_ARG1
315 %1 = tail call <16 x i8> @llvm.mips.srari.b(<16 x i8> %0, i32 7)
316 store <16 x i8> %1, <16 x i8>* @llvm_mips_srari_b_RES
320 declare <16 x i8> @llvm.mips.srari.b(<16 x i8>, i32) nounwind
322 ; CHECK: llvm_mips_srari_b_test:
326 ; CHECK: .size llvm_mips_srari_b_test
328 @llvm_mips_srari_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16
329 @llvm_mips_srari_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16
331 define void @llvm_mips_srari_h_test() nounwind {
333 %0 = load <8 x i16>* @llvm_mips_srari_h_ARG1
334 %1 = tail call <8 x i16> @llvm.mips.srari.h(<8 x i16> %0, i32 7)
335 store <8 x i16> %1, <8 x i16>* @llvm_mips_srari_h_RES
339 declare <8 x i16> @llvm.mips.srari.h(<8 x i16>, i32) nounwind
341 ; CHECK: llvm_mips_srari_h_test:
345 ; CHECK: .size llvm_mips_srari_h_test
347 @llvm_mips_srari_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16
348 @llvm_mips_srari_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16
350 define void @llvm_mips_srari_w_test() nounwind {
352 %0 = load <4 x i32>* @llvm_mips_srari_w_ARG1
353 %1 = tail call <4 x i32> @llvm.mips.srari.w(<4 x i32> %0, i32 7)
354 store <4 x i32> %1, <4 x i32>* @llvm_mips_srari_w_RES
358 declare <4 x i32> @llvm.mips.srari.w(<4 x i32>, i32) nounwind
360 ; CHECK: llvm_mips_srari_w_test:
364 ; CHECK: .size llvm_mips_srari_w_test
366 @llvm_mips_srari_d_ARG1 = global <2 x i64> <i64 0, i64 1>, align 16
367 @llvm_mips_srari_d_RES = global <2 x i64> <i64 0, i64 0>, align 16
369 define void @llvm_mips_srari_d_test() nounwind {
371 %0 = load <2 x i64>* @llvm_mips_srari_d_ARG1
372 %1 = tail call <2 x i64> @llvm.mips.srari.d(<2 x i64> %0, i32 7)
373 store <2 x i64> %1, <2 x i64>* @llvm_mips_srari_d_RES
377 declare <2 x i64> @llvm.mips.srari.d(<2 x i64>, i32) nounwind
379 ; CHECK: llvm_mips_srari_d_test:
383 ; CHECK: .size llvm_mips_srari_d_test
385 @llvm_mips_srli_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
386 @llvm_mips_srli_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16
388 define void @llvm_mips_srli_b_test() nounwind {
390 %0 = load <16 x i8>* @llvm_mips_srli_b_ARG1
391 %1 = tail call <16 x i8> @llvm.mips.srli.b(<16 x i8> %0, i32 7)
392 store <16 x i8> %1, <16 x i8>* @llvm_mips_srli_b_RES
396 declare <16 x i8> @llvm.mips.srli.b(<16 x i8>, i32) nounwind
398 ; CHECK: llvm_mips_srli_b_test:
402 ; CHECK: .size llvm_mips_srli_b_test
404 @llvm_mips_srli_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16
405 @llvm_mips_srli_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16
407 define void @llvm_mips_srli_h_test() nounwind {
409 %0 = load <8 x i16>* @llvm_mips_srli_h_ARG1
410 %1 = tail call <8 x i16> @llvm.mips.srli.h(<8 x i16> %0, i32 7)
411 store <8 x i16> %1, <8 x i16>* @llvm_mips_srli_h_RES
415 declare <8 x i16> @llvm.mips.srli.h(<8 x i16>, i32) nounwind
417 ; CHECK: llvm_mips_srli_h_test:
421 ; CHECK: .size llvm_mips_srli_h_test
423 @llvm_mips_srli_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16
424 @llvm_mips_srli_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16
426 define void @llvm_mips_srli_w_test() nounwind {
428 %0 = load <4 x i32>* @llvm_mips_srli_w_ARG1
429 %1 = tail call <4 x i32> @llvm.mips.srli.w(<4 x i32> %0, i32 7)
430 store <4 x i32> %1, <4 x i32>* @llvm_mips_srli_w_RES
434 declare <4 x i32> @llvm.mips.srli.w(<4 x i32>, i32) nounwind
436 ; CHECK: llvm_mips_srli_w_test:
440 ; CHECK: .size llvm_mips_srli_w_test
442 @llvm_mips_srli_d_ARG1 = global <2 x i64> <i64 0, i64 1>, align 16
443 @llvm_mips_srli_d_RES = global <2 x i64> <i64 0, i64 0>, align 16
445 define void @llvm_mips_srli_d_test() nounwind {
447 %0 = load <2 x i64>* @llvm_mips_srli_d_ARG1
448 %1 = tail call <2 x i64> @llvm.mips.srli.d(<2 x i64> %0, i32 7)
449 store <2 x i64> %1, <2 x i64>* @llvm_mips_srli_d_RES
453 declare <2 x i64> @llvm.mips.srli.d(<2 x i64>, i32) nounwind
455 ; CHECK: llvm_mips_srli_d_test:
459 ; CHECK: .size llvm_mips_srli_d_test
461 @llvm_mips_srlri_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
462 @llvm_mips_srlri_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16
464 define void @llvm_mips_srlri_b_test() nounwind {
466 %0 = load <16 x i8>* @llvm_mips_srlri_b_ARG1
467 %1 = tail call <16 x i8> @llvm.mips.srlri.b(<16 x i8> %0, i32 7)
468 store <16 x i8> %1, <16 x i8>* @llvm_mips_srlri_b_RES
472 declare <16 x i8> @llvm.mips.srlri.b(<16 x i8>, i32) nounwind
474 ; CHECK: llvm_mips_srlri_b_test:
478 ; CHECK: .size llvm_mips_srlri_b_test
480 @llvm_mips_srlri_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16
481 @llvm_mips_srlri_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16
483 define void @llvm_mips_srlri_h_test() nounwind {
485 %0 = load <8 x i16>* @llvm_mips_srlri_h_ARG1
486 %1 = tail call <8 x i16> @llvm.mips.srlri.h(<8 x i16> %0, i32 7)
487 store <8 x i16> %1, <8 x i16>* @llvm_mips_srlri_h_RES
491 declare <8 x i16> @llvm.mips.srlri.h(<8 x i16>, i32) nounwind
493 ; CHECK: llvm_mips_srlri_h_test:
497 ; CHECK: .size llvm_mips_srlri_h_test
499 @llvm_mips_srlri_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16
500 @llvm_mips_srlri_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16
502 define void @llvm_mips_srlri_w_test() nounwind {
504 %0 = load <4 x i32>* @llvm_mips_srlri_w_ARG1
505 %1 = tail call <4 x i32> @llvm.mips.srlri.w(<4 x i32> %0, i32 7)
506 store <4 x i32> %1, <4 x i32>* @llvm_mips_srlri_w_RES
510 declare <4 x i32> @llvm.mips.srlri.w(<4 x i32>, i32) nounwind
512 ; CHECK: llvm_mips_srlri_w_test:
516 ; CHECK: .size llvm_mips_srlri_w_test
518 @llvm_mips_srlri_d_ARG1 = global <2 x i64> <i64 0, i64 1>, align 16
519 @llvm_mips_srlri_d_RES = global <2 x i64> <i64 0, i64 0>, align 16
521 define void @llvm_mips_srlri_d_test() nounwind {
523 %0 = load <2 x i64>* @llvm_mips_srlri_d_ARG1
524 %1 = tail call <2 x i64> @llvm.mips.srlri.d(<2 x i64> %0, i32 7)
525 store <2 x i64> %1, <2 x i64>* @llvm_mips_srlri_d_RES
529 declare <2 x i64> @llvm.mips.srlri.d(<2 x i64>, i32) nounwind
531 ; CHECK: llvm_mips_srlri_d_test:
535 ; CHECK: .size llvm_mips_srlri_d_test