1 ; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s
3 define void @ceq_v16i8(<16 x i8>* %c, <16 x i8>* %a, <16 x i8>* %b) nounwind {
6 %1 = load <16 x i8>* %a
7 ; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5)
8 %2 = load <16 x i8>* %b
9 ; CHECK-DAG: ld.b [[R2:\$w[0-9]+]], 0($6)
10 %3 = icmp eq <16 x i8> %1, %2
11 %4 = sext <16 x i1> %3 to <16 x i8>
12 ; CHECK-DAG: ceq.b [[R3:\$w[0-9]+]], [[R1]], [[R2]]
13 store <16 x i8> %4, <16 x i8>* %c
14 ; CHECK-DAG: st.b [[R3]], 0($4)
17 ; CHECK: .size ceq_v16i8
20 define void @ceq_v8i16(<8 x i16>* %c, <8 x i16>* %a, <8 x i16>* %b) nounwind {
23 %1 = load <8 x i16>* %a
24 ; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5)
25 %2 = load <8 x i16>* %b
26 ; CHECK-DAG: ld.h [[R2:\$w[0-9]+]], 0($6)
27 %3 = icmp eq <8 x i16> %1, %2
28 %4 = sext <8 x i1> %3 to <8 x i16>
29 ; CHECK-DAG: ceq.h [[R3:\$w[0-9]+]], [[R1]], [[R2]]
30 store <8 x i16> %4, <8 x i16>* %c
31 ; CHECK-DAG: st.h [[R3]], 0($4)
34 ; CHECK: .size ceq_v8i16
37 define void @ceq_v4i32(<4 x i32>* %c, <4 x i32>* %a, <4 x i32>* %b) nounwind {
40 %1 = load <4 x i32>* %a
41 ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
42 %2 = load <4 x i32>* %b
43 ; CHECK-DAG: ld.w [[R2:\$w[0-9]+]], 0($6)
44 %3 = icmp eq <4 x i32> %1, %2
45 %4 = sext <4 x i1> %3 to <4 x i32>
46 ; CHECK-DAG: ceq.w [[R3:\$w[0-9]+]], [[R1]], [[R2]]
47 store <4 x i32> %4, <4 x i32>* %c
48 ; CHECK-DAG: st.w [[R3]], 0($4)
51 ; CHECK: .size ceq_v4i32
54 define void @ceq_v2i64(<2 x i64>* %c, <2 x i64>* %a, <2 x i64>* %b) nounwind {
57 %1 = load <2 x i64>* %a
58 ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
59 %2 = load <2 x i64>* %b
60 ; CHECK-DAG: ld.d [[R2:\$w[0-9]+]], 0($6)
61 %3 = icmp eq <2 x i64> %1, %2
62 %4 = sext <2 x i1> %3 to <2 x i64>
63 ; CHECK-DAG: ceq.d [[R3:\$w[0-9]+]], [[R1]], [[R2]]
64 store <2 x i64> %4, <2 x i64>* %c
65 ; CHECK-DAG: st.d [[R3]], 0($4)
68 ; CHECK: .size ceq_v2i64
71 define void @cle_s_v16i8(<16 x i8>* %c, <16 x i8>* %a, <16 x i8>* %b) nounwind {
74 %1 = load <16 x i8>* %a
75 ; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5)
76 %2 = load <16 x i8>* %b
77 ; CHECK-DAG: ld.b [[R2:\$w[0-9]+]], 0($6)
78 %3 = icmp sle <16 x i8> %1, %2
79 %4 = sext <16 x i1> %3 to <16 x i8>
80 ; CHECK-DAG: cle_s.b [[R3:\$w[0-9]+]], [[R1]], [[R2]]
81 store <16 x i8> %4, <16 x i8>* %c
82 ; CHECK-DAG: st.b [[R3]], 0($4)
85 ; CHECK: .size cle_s_v16i8
88 define void @cle_s_v8i16(<8 x i16>* %c, <8 x i16>* %a, <8 x i16>* %b) nounwind {
91 %1 = load <8 x i16>* %a
92 ; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5)
93 %2 = load <8 x i16>* %b
94 ; CHECK-DAG: ld.h [[R2:\$w[0-9]+]], 0($6)
95 %3 = icmp sle <8 x i16> %1, %2
96 %4 = sext <8 x i1> %3 to <8 x i16>
97 ; CHECK-DAG: cle_s.h [[R3:\$w[0-9]+]], [[R1]], [[R2]]
98 store <8 x i16> %4, <8 x i16>* %c
99 ; CHECK-DAG: st.h [[R3]], 0($4)
102 ; CHECK: .size cle_s_v8i16
105 define void @cle_s_v4i32(<4 x i32>* %c, <4 x i32>* %a, <4 x i32>* %b) nounwind {
106 ; CHECK: cle_s_v4i32:
108 %1 = load <4 x i32>* %a
109 ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
110 %2 = load <4 x i32>* %b
111 ; CHECK-DAG: ld.w [[R2:\$w[0-9]+]], 0($6)
112 %3 = icmp sle <4 x i32> %1, %2
113 %4 = sext <4 x i1> %3 to <4 x i32>
114 ; CHECK-DAG: cle_s.w [[R3:\$w[0-9]+]], [[R1]], [[R2]]
115 store <4 x i32> %4, <4 x i32>* %c
116 ; CHECK-DAG: st.w [[R3]], 0($4)
119 ; CHECK: .size cle_s_v4i32
122 define void @cle_s_v2i64(<2 x i64>* %c, <2 x i64>* %a, <2 x i64>* %b) nounwind {
123 ; CHECK: cle_s_v2i64:
125 %1 = load <2 x i64>* %a
126 ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
127 %2 = load <2 x i64>* %b
128 ; CHECK-DAG: ld.d [[R2:\$w[0-9]+]], 0($6)
129 %3 = icmp sle <2 x i64> %1, %2
130 %4 = sext <2 x i1> %3 to <2 x i64>
131 ; CHECK-DAG: cle_s.d [[R3:\$w[0-9]+]], [[R1]], [[R2]]
132 store <2 x i64> %4, <2 x i64>* %c
133 ; CHECK-DAG: st.d [[R3]], 0($4)
136 ; CHECK: .size cle_s_v2i64
139 define void @cle_u_v16i8(<16 x i8>* %c, <16 x i8>* %a, <16 x i8>* %b) nounwind {
140 ; CHECK: cle_u_v16i8:
142 %1 = load <16 x i8>* %a
143 ; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5)
144 %2 = load <16 x i8>* %b
145 ; CHECK-DAG: ld.b [[R2:\$w[0-9]+]], 0($6)
146 %3 = icmp ule <16 x i8> %1, %2
147 %4 = sext <16 x i1> %3 to <16 x i8>
148 ; CHECK-DAG: cle_u.b [[R3:\$w[0-9]+]], [[R1]], [[R2]]
149 store <16 x i8> %4, <16 x i8>* %c
150 ; CHECK-DAG: st.b [[R3]], 0($4)
153 ; CHECK: .size cle_u_v16i8
156 define void @cle_u_v8i16(<8 x i16>* %c, <8 x i16>* %a, <8 x i16>* %b) nounwind {
157 ; CHECK: cle_u_v8i16:
159 %1 = load <8 x i16>* %a
160 ; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5)
161 %2 = load <8 x i16>* %b
162 ; CHECK-DAG: ld.h [[R2:\$w[0-9]+]], 0($6)
163 %3 = icmp ule <8 x i16> %1, %2
164 %4 = sext <8 x i1> %3 to <8 x i16>
165 ; CHECK-DAG: cle_u.h [[R3:\$w[0-9]+]], [[R1]], [[R2]]
166 store <8 x i16> %4, <8 x i16>* %c
167 ; CHECK-DAG: st.h [[R3]], 0($4)
170 ; CHECK: .size cle_u_v8i16
173 define void @cle_u_v4i32(<4 x i32>* %c, <4 x i32>* %a, <4 x i32>* %b) nounwind {
174 ; CHECK: cle_u_v4i32:
176 %1 = load <4 x i32>* %a
177 ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
178 %2 = load <4 x i32>* %b
179 ; CHECK-DAG: ld.w [[R2:\$w[0-9]+]], 0($6)
180 %3 = icmp ule <4 x i32> %1, %2
181 %4 = sext <4 x i1> %3 to <4 x i32>
182 ; CHECK-DAG: cle_u.w [[R3:\$w[0-9]+]], [[R1]], [[R2]]
183 store <4 x i32> %4, <4 x i32>* %c
184 ; CHECK-DAG: st.w [[R3]], 0($4)
187 ; CHECK: .size cle_u_v4i32
190 define void @cle_u_v2i64(<2 x i64>* %c, <2 x i64>* %a, <2 x i64>* %b) nounwind {
191 ; CHECK: cle_u_v2i64:
193 %1 = load <2 x i64>* %a
194 ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
195 %2 = load <2 x i64>* %b
196 ; CHECK-DAG: ld.d [[R2:\$w[0-9]+]], 0($6)
197 %3 = icmp ule <2 x i64> %1, %2
198 %4 = sext <2 x i1> %3 to <2 x i64>
199 ; CHECK-DAG: cle_u.d [[R3:\$w[0-9]+]], [[R1]], [[R2]]
200 store <2 x i64> %4, <2 x i64>* %c
201 ; CHECK-DAG: st.d [[R3]], 0($4)
204 ; CHECK: .size cle_u_v2i64
207 define void @clt_s_v16i8(<16 x i8>* %c, <16 x i8>* %a, <16 x i8>* %b) nounwind {
208 ; CHECK: clt_s_v16i8:
210 %1 = load <16 x i8>* %a
211 ; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5)
212 %2 = load <16 x i8>* %b
213 ; CHECK-DAG: ld.b [[R2:\$w[0-9]+]], 0($6)
214 %3 = icmp slt <16 x i8> %1, %2
215 %4 = sext <16 x i1> %3 to <16 x i8>
216 ; CHECK-DAG: clt_s.b [[R3:\$w[0-9]+]], [[R1]], [[R2]]
217 store <16 x i8> %4, <16 x i8>* %c
218 ; CHECK-DAG: st.b [[R3]], 0($4)
221 ; CHECK: .size clt_s_v16i8
224 define void @clt_s_v8i16(<8 x i16>* %c, <8 x i16>* %a, <8 x i16>* %b) nounwind {
225 ; CHECK: clt_s_v8i16:
227 %1 = load <8 x i16>* %a
228 ; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5)
229 %2 = load <8 x i16>* %b
230 ; CHECK-DAG: ld.h [[R2:\$w[0-9]+]], 0($6)
231 %3 = icmp slt <8 x i16> %1, %2
232 %4 = sext <8 x i1> %3 to <8 x i16>
233 ; CHECK-DAG: clt_s.h [[R3:\$w[0-9]+]], [[R1]], [[R2]]
234 store <8 x i16> %4, <8 x i16>* %c
235 ; CHECK-DAG: st.h [[R3]], 0($4)
238 ; CHECK: .size clt_s_v8i16
241 define void @clt_s_v4i32(<4 x i32>* %c, <4 x i32>* %a, <4 x i32>* %b) nounwind {
242 ; CHECK: clt_s_v4i32:
244 %1 = load <4 x i32>* %a
245 ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
246 %2 = load <4 x i32>* %b
247 ; CHECK-DAG: ld.w [[R2:\$w[0-9]+]], 0($6)
248 %3 = icmp slt <4 x i32> %1, %2
249 %4 = sext <4 x i1> %3 to <4 x i32>
250 ; CHECK-DAG: clt_s.w [[R3:\$w[0-9]+]], [[R1]], [[R2]]
251 store <4 x i32> %4, <4 x i32>* %c
252 ; CHECK-DAG: st.w [[R3]], 0($4)
255 ; CHECK: .size clt_s_v4i32
258 define void @clt_s_v2i64(<2 x i64>* %c, <2 x i64>* %a, <2 x i64>* %b) nounwind {
259 ; CHECK: clt_s_v2i64:
261 %1 = load <2 x i64>* %a
262 ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
263 %2 = load <2 x i64>* %b
264 ; CHECK-DAG: ld.d [[R2:\$w[0-9]+]], 0($6)
265 %3 = icmp slt <2 x i64> %1, %2
266 %4 = sext <2 x i1> %3 to <2 x i64>
267 ; CHECK-DAG: clt_s.d [[R3:\$w[0-9]+]], [[R1]], [[R2]]
268 store <2 x i64> %4, <2 x i64>* %c
269 ; CHECK-DAG: st.d [[R3]], 0($4)
272 ; CHECK: .size clt_s_v2i64
275 define void @clt_u_v16i8(<16 x i8>* %c, <16 x i8>* %a, <16 x i8>* %b) nounwind {
276 ; CHECK: clt_u_v16i8:
278 %1 = load <16 x i8>* %a
279 ; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5)
280 %2 = load <16 x i8>* %b
281 ; CHECK-DAG: ld.b [[R2:\$w[0-9]+]], 0($6)
282 %3 = icmp ult <16 x i8> %1, %2
283 %4 = sext <16 x i1> %3 to <16 x i8>
284 ; CHECK-DAG: clt_u.b [[R3:\$w[0-9]+]], [[R1]], [[R2]]
285 store <16 x i8> %4, <16 x i8>* %c
286 ; CHECK-DAG: st.b [[R3]], 0($4)
289 ; CHECK: .size clt_u_v16i8
292 define void @clt_u_v8i16(<8 x i16>* %c, <8 x i16>* %a, <8 x i16>* %b) nounwind {
293 ; CHECK: clt_u_v8i16:
295 %1 = load <8 x i16>* %a
296 ; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5)
297 %2 = load <8 x i16>* %b
298 ; CHECK-DAG: ld.h [[R2:\$w[0-9]+]], 0($6)
299 %3 = icmp ult <8 x i16> %1, %2
300 %4 = sext <8 x i1> %3 to <8 x i16>
301 ; CHECK-DAG: clt_u.h [[R3:\$w[0-9]+]], [[R1]], [[R2]]
302 store <8 x i16> %4, <8 x i16>* %c
303 ; CHECK-DAG: st.h [[R3]], 0($4)
306 ; CHECK: .size clt_u_v8i16
309 define void @clt_u_v4i32(<4 x i32>* %c, <4 x i32>* %a, <4 x i32>* %b) nounwind {
310 ; CHECK: clt_u_v4i32:
312 %1 = load <4 x i32>* %a
313 ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
314 %2 = load <4 x i32>* %b
315 ; CHECK-DAG: ld.w [[R2:\$w[0-9]+]], 0($6)
316 %3 = icmp ult <4 x i32> %1, %2
317 %4 = sext <4 x i1> %3 to <4 x i32>
318 ; CHECK-DAG: clt_u.w [[R3:\$w[0-9]+]], [[R1]], [[R2]]
319 store <4 x i32> %4, <4 x i32>* %c
320 ; CHECK-DAG: st.w [[R3]], 0($4)
323 ; CHECK: .size clt_u_v4i32
326 define void @clt_u_v2i64(<2 x i64>* %c, <2 x i64>* %a, <2 x i64>* %b) nounwind {
327 ; CHECK: clt_u_v2i64:
329 %1 = load <2 x i64>* %a
330 ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
331 %2 = load <2 x i64>* %b
332 ; CHECK-DAG: ld.d [[R2:\$w[0-9]+]], 0($6)
333 %3 = icmp ult <2 x i64> %1, %2
334 %4 = sext <2 x i1> %3 to <2 x i64>
335 ; CHECK-DAG: clt_u.d [[R3:\$w[0-9]+]], [[R1]], [[R2]]
336 store <2 x i64> %4, <2 x i64>* %c
337 ; CHECK-DAG: st.d [[R3]], 0($4)
340 ; CHECK: .size clt_u_v2i64
343 define void @ceqi_v16i8(<16 x i8>* %c, <16 x i8>* %a) nounwind {
346 %1 = load <16 x i8>* %a
347 ; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5)
348 %2 = icmp eq <16 x i8> %1, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
349 %3 = sext <16 x i1> %2 to <16 x i8>
350 ; CHECK-DAG: ceqi.b [[R3:\$w[0-9]+]], [[R1]], 1
351 store <16 x i8> %3, <16 x i8>* %c
352 ; CHECK-DAG: st.b [[R3]], 0($4)
355 ; CHECK: .size ceqi_v16i8
358 define void @ceqi_v8i16(<8 x i16>* %c, <8 x i16>* %a) nounwind {
361 %1 = load <8 x i16>* %a
362 ; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5)
363 %2 = icmp eq <8 x i16> %1, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
364 %3 = sext <8 x i1> %2 to <8 x i16>
365 ; CHECK-DAG: ceqi.h [[R3:\$w[0-9]+]], [[R1]], 1
366 store <8 x i16> %3, <8 x i16>* %c
367 ; CHECK-DAG: st.h [[R3]], 0($4)
370 ; CHECK: .size ceqi_v8i16
373 define void @ceqi_v4i32(<4 x i32>* %c, <4 x i32>* %a) nounwind {
376 %1 = load <4 x i32>* %a
377 ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
378 %2 = icmp eq <4 x i32> %1, <i32 1, i32 1, i32 1, i32 1>
379 %3 = sext <4 x i1> %2 to <4 x i32>
380 ; CHECK-DAG: ceqi.w [[R3:\$w[0-9]+]], [[R1]], 1
381 store <4 x i32> %3, <4 x i32>* %c
382 ; CHECK-DAG: st.w [[R3]], 0($4)
385 ; CHECK: .size ceqi_v4i32
388 define void @ceqi_v2i64(<2 x i64>* %c, <2 x i64>* %a) nounwind {
391 %1 = load <2 x i64>* %a
392 ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
393 %2 = icmp eq <2 x i64> %1, <i64 1, i64 1>
394 %3 = sext <2 x i1> %2 to <2 x i64>
395 ; CHECK-DAG: ceqi.d [[R3:\$w[0-9]+]], [[R1]], 1
396 store <2 x i64> %3, <2 x i64>* %c
397 ; CHECK-DAG: st.d [[R3]], 0($4)
400 ; CHECK: .size ceqi_v2i64
403 define void @clei_s_v16i8(<16 x i8>* %c, <16 x i8>* %a) nounwind {
404 ; CHECK: clei_s_v16i8:
406 %1 = load <16 x i8>* %a
407 ; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5)
408 %2 = icmp sle <16 x i8> %1, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
409 %3 = sext <16 x i1> %2 to <16 x i8>
410 ; CHECK-DAG: clei_s.b [[R3:\$w[0-9]+]], [[R1]], 1
411 store <16 x i8> %3, <16 x i8>* %c
412 ; CHECK-DAG: st.b [[R3]], 0($4)
415 ; CHECK: .size clei_s_v16i8
418 define void @clei_s_v8i16(<8 x i16>* %c, <8 x i16>* %a) nounwind {
419 ; CHECK: clei_s_v8i16:
421 %1 = load <8 x i16>* %a
422 ; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5)
423 %2 = icmp sle <8 x i16> %1, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
424 %3 = sext <8 x i1> %2 to <8 x i16>
425 ; CHECK-DAG: clei_s.h [[R3:\$w[0-9]+]], [[R1]], 1
426 store <8 x i16> %3, <8 x i16>* %c
427 ; CHECK-DAG: st.h [[R3]], 0($4)
430 ; CHECK: .size clei_s_v8i16
433 define void @clei_s_v4i32(<4 x i32>* %c, <4 x i32>* %a) nounwind {
434 ; CHECK: clei_s_v4i32:
436 %1 = load <4 x i32>* %a
437 ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
438 %2 = icmp sle <4 x i32> %1, <i32 1, i32 1, i32 1, i32 1>
439 %3 = sext <4 x i1> %2 to <4 x i32>
440 ; CHECK-DAG: clei_s.w [[R3:\$w[0-9]+]], [[R1]], 1
441 store <4 x i32> %3, <4 x i32>* %c
442 ; CHECK-DAG: st.w [[R3]], 0($4)
445 ; CHECK: .size clei_s_v4i32
448 define void @clei_s_v2i64(<2 x i64>* %c, <2 x i64>* %a) nounwind {
449 ; CHECK: clei_s_v2i64:
451 %1 = load <2 x i64>* %a
452 ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
453 %2 = icmp sle <2 x i64> %1, <i64 1, i64 1>
454 %3 = sext <2 x i1> %2 to <2 x i64>
455 ; CHECK-DAG: clei_s.d [[R3:\$w[0-9]+]], [[R1]], 1
456 store <2 x i64> %3, <2 x i64>* %c
457 ; CHECK-DAG: st.d [[R3]], 0($4)
460 ; CHECK: .size clei_s_v2i64
463 define void @clei_u_v16i8(<16 x i8>* %c, <16 x i8>* %a) nounwind {
464 ; CHECK: clei_u_v16i8:
466 %1 = load <16 x i8>* %a
467 ; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5)
468 %2 = icmp ule <16 x i8> %1, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
469 %3 = sext <16 x i1> %2 to <16 x i8>
470 ; CHECK-DAG: clei_u.b [[R3:\$w[0-9]+]], [[R1]], 1
471 store <16 x i8> %3, <16 x i8>* %c
472 ; CHECK-DAG: st.b [[R3]], 0($4)
475 ; CHECK: .size clei_u_v16i8
478 define void @clei_u_v8i16(<8 x i16>* %c, <8 x i16>* %a) nounwind {
479 ; CHECK: clei_u_v8i16:
481 %1 = load <8 x i16>* %a
482 ; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5)
483 %2 = icmp ule <8 x i16> %1, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
484 %3 = sext <8 x i1> %2 to <8 x i16>
485 ; CHECK-DAG: clei_u.h [[R3:\$w[0-9]+]], [[R1]], 1
486 store <8 x i16> %3, <8 x i16>* %c
487 ; CHECK-DAG: st.h [[R3]], 0($4)
490 ; CHECK: .size clei_u_v8i16
493 define void @clei_u_v4i32(<4 x i32>* %c, <4 x i32>* %a) nounwind {
494 ; CHECK: clei_u_v4i32:
496 %1 = load <4 x i32>* %a
497 ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
498 %2 = icmp ule <4 x i32> %1, <i32 1, i32 1, i32 1, i32 1>
499 %3 = sext <4 x i1> %2 to <4 x i32>
500 ; CHECK-DAG: clei_u.w [[R3:\$w[0-9]+]], [[R1]], 1
501 store <4 x i32> %3, <4 x i32>* %c
502 ; CHECK-DAG: st.w [[R3]], 0($4)
505 ; CHECK: .size clei_u_v4i32
508 define void @clei_u_v2i64(<2 x i64>* %c, <2 x i64>* %a) nounwind {
509 ; CHECK: clei_u_v2i64:
511 %1 = load <2 x i64>* %a
512 ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
513 %2 = icmp ule <2 x i64> %1, <i64 1, i64 1>
514 %3 = sext <2 x i1> %2 to <2 x i64>
515 ; CHECK-DAG: clei_u.d [[R3:\$w[0-9]+]], [[R1]], 1
516 store <2 x i64> %3, <2 x i64>* %c
517 ; CHECK-DAG: st.d [[R3]], 0($4)
520 ; CHECK: .size clei_u_v2i64
523 define void @clti_s_v16i8(<16 x i8>* %c, <16 x i8>* %a) nounwind {
524 ; CHECK: clti_s_v16i8:
526 %1 = load <16 x i8>* %a
527 ; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5)
528 %2 = icmp slt <16 x i8> %1, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
529 %3 = sext <16 x i1> %2 to <16 x i8>
530 ; CHECK-DAG: clti_s.b [[R3:\$w[0-9]+]], [[R1]], 1
531 store <16 x i8> %3, <16 x i8>* %c
532 ; CHECK-DAG: st.b [[R3]], 0($4)
535 ; CHECK: .size clti_s_v16i8
538 define void @clti_s_v8i16(<8 x i16>* %c, <8 x i16>* %a) nounwind {
539 ; CHECK: clti_s_v8i16:
541 %1 = load <8 x i16>* %a
542 ; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5)
543 %2 = icmp slt <8 x i16> %1, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
544 %3 = sext <8 x i1> %2 to <8 x i16>
545 ; CHECK-DAG: clti_s.h [[R3:\$w[0-9]+]], [[R1]], 1
546 store <8 x i16> %3, <8 x i16>* %c
547 ; CHECK-DAG: st.h [[R3]], 0($4)
550 ; CHECK: .size clti_s_v8i16
553 define void @clti_s_v4i32(<4 x i32>* %c, <4 x i32>* %a) nounwind {
554 ; CHECK: clti_s_v4i32:
556 %1 = load <4 x i32>* %a
557 ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
558 %2 = icmp slt <4 x i32> %1, <i32 1, i32 1, i32 1, i32 1>
559 %3 = sext <4 x i1> %2 to <4 x i32>
560 ; CHECK-DAG: clti_s.w [[R3:\$w[0-9]+]], [[R1]], 1
561 store <4 x i32> %3, <4 x i32>* %c
562 ; CHECK-DAG: st.w [[R3]], 0($4)
565 ; CHECK: .size clti_s_v4i32
568 define void @clti_s_v2i64(<2 x i64>* %c, <2 x i64>* %a) nounwind {
569 ; CHECK: clti_s_v2i64:
571 %1 = load <2 x i64>* %a
572 ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
573 %2 = icmp slt <2 x i64> %1, <i64 1, i64 1>
574 %3 = sext <2 x i1> %2 to <2 x i64>
575 ; CHECK-DAG: clti_s.d [[R3:\$w[0-9]+]], [[R1]], 1
576 store <2 x i64> %3, <2 x i64>* %c
577 ; CHECK-DAG: st.d [[R3]], 0($4)
580 ; CHECK: .size clti_s_v2i64
583 define void @clti_u_v16i8(<16 x i8>* %c, <16 x i8>* %a) nounwind {
584 ; CHECK: clti_u_v16i8:
586 %1 = load <16 x i8>* %a
587 ; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5)
588 %2 = icmp ult <16 x i8> %1, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
589 %3 = sext <16 x i1> %2 to <16 x i8>
590 ; CHECK-DAG: clti_u.b [[R3:\$w[0-9]+]], [[R1]], 1
591 store <16 x i8> %3, <16 x i8>* %c
592 ; CHECK-DAG: st.b [[R3]], 0($4)
595 ; CHECK: .size clti_u_v16i8
598 define void @clti_u_v8i16(<8 x i16>* %c, <8 x i16>* %a) nounwind {
599 ; CHECK: clti_u_v8i16:
601 %1 = load <8 x i16>* %a
602 ; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5)
603 %2 = icmp ult <8 x i16> %1, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
604 %3 = sext <8 x i1> %2 to <8 x i16>
605 ; CHECK-DAG: clti_u.h [[R3:\$w[0-9]+]], [[R1]], 1
606 store <8 x i16> %3, <8 x i16>* %c
607 ; CHECK-DAG: st.h [[R3]], 0($4)
610 ; CHECK: .size clti_u_v8i16
613 define void @clti_u_v4i32(<4 x i32>* %c, <4 x i32>* %a) nounwind {
614 ; CHECK: clti_u_v4i32:
616 %1 = load <4 x i32>* %a
617 ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
618 %2 = icmp ult <4 x i32> %1, <i32 1, i32 1, i32 1, i32 1>
619 %3 = sext <4 x i1> %2 to <4 x i32>
620 ; CHECK-DAG: clti_u.w [[R3:\$w[0-9]+]], [[R1]], 1
621 store <4 x i32> %3, <4 x i32>* %c
622 ; CHECK-DAG: st.w [[R3]], 0($4)
625 ; CHECK: .size clti_u_v4i32
628 define void @clti_u_v2i64(<2 x i64>* %c, <2 x i64>* %a) nounwind {
629 ; CHECK: clti_u_v2i64:
631 %1 = load <2 x i64>* %a
632 ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
633 %2 = icmp ult <2 x i64> %1, <i64 1, i64 1>
634 %3 = sext <2 x i1> %2 to <2 x i64>
635 ; CHECK-DAG: clti_u.d [[R3:\$w[0-9]+]], [[R1]], 1
636 store <2 x i64> %3, <2 x i64>* %c
637 ; CHECK-DAG: st.d [[R3]], 0($4)
640 ; CHECK: .size clti_u_v2i64
643 define void @bsel_s_v16i8(<16 x i8>* %d, <16 x i8>* %a, <16 x i8>* %b,
644 <16 x i8>* %c) nounwind {
645 ; CHECK: bsel_s_v16i8:
647 %1 = load <16 x i8>* %a
648 ; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5)
649 %2 = load <16 x i8>* %b
650 ; CHECK-DAG: ld.b [[R2:\$w[0-9]+]], 0($6)
651 %3 = load <16 x i8>* %c
652 ; CHECK-DAG: ld.b [[R3:\$w[0-9]+]], 0($7)
653 %4 = icmp sgt <16 x i8> %1, %2
654 ; CHECK-DAG: clt_s.b [[R4:\$w[0-9]+]], [[R2]], [[R1]]
655 %5 = select <16 x i1> %4, <16 x i8> %1, <16 x i8> %3
656 ; bmnz.v is the same operation
657 ; CHECK-DAG: bmnz.v [[R3]], [[R1]], [[R4]]
658 store <16 x i8> %5, <16 x i8>* %d
659 ; CHECK-DAG: st.b [[R3]], 0($4)
662 ; CHECK: .size bsel_s_v16i8
665 define void @bsel_s_v8i16(<8 x i16>* %d, <8 x i16>* %a, <8 x i16>* %b,
666 <8 x i16>* %c) nounwind {
667 ; CHECK: bsel_s_v8i16:
669 %1 = load <8 x i16>* %a
670 ; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5)
671 %2 = load <8 x i16>* %b
672 ; CHECK-DAG: ld.h [[R2:\$w[0-9]+]], 0($6)
673 %3 = load <8 x i16>* %c
674 ; CHECK-DAG: ld.h [[R3:\$w[0-9]+]], 0($7)
675 %4 = icmp sgt <8 x i16> %1, %2
676 ; CHECK-DAG: clt_s.h [[R4:\$w[0-9]+]], [[R2]], [[R1]]
677 %5 = select <8 x i1> %4, <8 x i16> %1, <8 x i16> %3
678 ; CHECK-DAG: bsel.v [[R4]], [[R1]], [[R3]]
679 store <8 x i16> %5, <8 x i16>* %d
680 ; CHECK-DAG: st.h [[R4]], 0($4)
683 ; CHECK: .size bsel_s_v8i16
686 define void @bsel_s_v4i32(<4 x i32>* %d, <4 x i32>* %a, <4 x i32>* %b,
687 <4 x i32>* %c) nounwind {
688 ; CHECK: bsel_s_v4i32:
690 %1 = load <4 x i32>* %a
691 ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
692 %2 = load <4 x i32>* %b
693 ; CHECK-DAG: ld.w [[R2:\$w[0-9]+]], 0($6)
694 %3 = load <4 x i32>* %c
695 ; CHECK-DAG: ld.w [[R3:\$w[0-9]+]], 0($7)
696 %4 = icmp sgt <4 x i32> %1, %2
697 ; CHECK-DAG: clt_s.w [[R4:\$w[0-9]+]], [[R2]], [[R1]]
698 %5 = select <4 x i1> %4, <4 x i32> %1, <4 x i32> %3
699 ; CHECK-DAG: bsel.v [[R4]], [[R1]], [[R3]]
700 store <4 x i32> %5, <4 x i32>* %d
701 ; CHECK-DAG: st.w [[R4]], 0($4)
704 ; CHECK: .size bsel_s_v4i32
707 define void @bsel_s_v2i64(<2 x i64>* %d, <2 x i64>* %a, <2 x i64>* %b,
708 <2 x i64>* %c) nounwind {
709 ; CHECK: bsel_s_v2i64:
711 %1 = load <2 x i64>* %a
712 ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
713 %2 = load <2 x i64>* %b
714 ; CHECK-DAG: ld.d [[R2:\$w[0-9]+]], 0($6)
715 %3 = load <2 x i64>* %c
716 ; CHECK-DAG: ld.d [[R3:\$w[0-9]+]], 0($7)
717 %4 = icmp sgt <2 x i64> %1, %2
718 ; CHECK-DAG: clt_s.d [[R4:\$w[0-9]+]], [[R2]], [[R1]]
719 %5 = select <2 x i1> %4, <2 x i64> %1, <2 x i64> %3
720 ; CHECK-DAG: bsel.v [[R4]], [[R1]], [[R3]]
721 store <2 x i64> %5, <2 x i64>* %d
722 ; CHECK-DAG: st.d [[R4]], 0($4)
725 ; CHECK: .size bsel_s_v2i64
728 define void @bsel_u_v16i8(<16 x i8>* %d, <16 x i8>* %a, <16 x i8>* %b,
729 <16 x i8>* %c) nounwind {
730 ; CHECK: bsel_u_v16i8:
732 %1 = load <16 x i8>* %a
733 ; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5)
734 %2 = load <16 x i8>* %b
735 ; CHECK-DAG: ld.b [[R2:\$w[0-9]+]], 0($6)
736 %3 = load <16 x i8>* %c
737 ; CHECK-DAG: ld.b [[R3:\$w[0-9]+]], 0($7)
738 %4 = icmp ugt <16 x i8> %1, %2
739 ; CHECK-DAG: clt_u.b [[R4:\$w[0-9]+]], [[R2]], [[R1]]
740 %5 = select <16 x i1> %4, <16 x i8> %1, <16 x i8> %3
741 ; bmnz.v is the same operation
742 ; CHECK-DAG: bmnz.v [[R3]], [[R1]], [[R4]]
743 store <16 x i8> %5, <16 x i8>* %d
744 ; CHECK-DAG: st.b [[R3]], 0($4)
747 ; CHECK: .size bsel_u_v16i8
750 define void @bsel_u_v8i16(<8 x i16>* %d, <8 x i16>* %a, <8 x i16>* %b,
751 <8 x i16>* %c) nounwind {
752 ; CHECK: bsel_u_v8i16:
754 %1 = load <8 x i16>* %a
755 ; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5)
756 %2 = load <8 x i16>* %b
757 ; CHECK-DAG: ld.h [[R2:\$w[0-9]+]], 0($6)
758 %3 = load <8 x i16>* %c
759 ; CHECK-DAG: ld.h [[R3:\$w[0-9]+]], 0($7)
760 %4 = icmp ugt <8 x i16> %1, %2
761 ; CHECK-DAG: clt_u.h [[R4:\$w[0-9]+]], [[R2]], [[R1]]
762 %5 = select <8 x i1> %4, <8 x i16> %1, <8 x i16> %3
763 ; CHECK-DAG: bsel.v [[R4]], [[R1]], [[R3]]
764 store <8 x i16> %5, <8 x i16>* %d
765 ; CHECK-DAG: st.h [[R4]], 0($4)
768 ; CHECK: .size bsel_u_v8i16
771 define void @bsel_u_v4i32(<4 x i32>* %d, <4 x i32>* %a, <4 x i32>* %b,
772 <4 x i32>* %c) nounwind {
773 ; CHECK: bsel_u_v4i32:
775 %1 = load <4 x i32>* %a
776 ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
777 %2 = load <4 x i32>* %b
778 ; CHECK-DAG: ld.w [[R2:\$w[0-9]+]], 0($6)
779 %3 = load <4 x i32>* %c
780 ; CHECK-DAG: ld.w [[R3:\$w[0-9]+]], 0($7)
781 %4 = icmp ugt <4 x i32> %1, %2
782 ; CHECK-DAG: clt_u.w [[R4:\$w[0-9]+]], [[R2]], [[R1]]
783 %5 = select <4 x i1> %4, <4 x i32> %1, <4 x i32> %3
784 ; CHECK-DAG: bsel.v [[R4]], [[R1]], [[R3]]
785 store <4 x i32> %5, <4 x i32>* %d
786 ; CHECK-DAG: st.w [[R4]], 0($4)
789 ; CHECK: .size bsel_u_v4i32
792 define void @bsel_u_v2i64(<2 x i64>* %d, <2 x i64>* %a, <2 x i64>* %b,
793 <2 x i64>* %c) nounwind {
794 ; CHECK: bsel_u_v2i64:
796 %1 = load <2 x i64>* %a
797 ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
798 %2 = load <2 x i64>* %b
799 ; CHECK-DAG: ld.d [[R2:\$w[0-9]+]], 0($6)
800 %3 = load <2 x i64>* %c
801 ; CHECK-DAG: ld.d [[R3:\$w[0-9]+]], 0($7)
802 %4 = icmp ugt <2 x i64> %1, %2
803 ; CHECK-DAG: clt_u.d [[R4:\$w[0-9]+]], [[R2]], [[R1]]
804 %5 = select <2 x i1> %4, <2 x i64> %1, <2 x i64> %3
805 ; CHECK-DAG: bsel.v [[R4]], [[R1]], [[R3]]
806 store <2 x i64> %5, <2 x i64>* %d
807 ; CHECK-DAG: st.d [[R4]], 0($4)
810 ; CHECK: .size bsel_u_v2i64
813 define void @bseli_s_v16i8(<16 x i8>* %d, <16 x i8>* %a, <16 x i8>* %b,
814 <16 x i8>* %c) nounwind {
815 ; CHECK: bseli_s_v16i8:
817 %1 = load <16 x i8>* %a
818 ; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5)
819 %2 = load <16 x i8>* %b
820 ; CHECK-DAG: ld.b [[R2:\$w[0-9]+]], 0($6)
821 %3 = icmp sgt <16 x i8> %1, %2
822 ; CHECK-DAG: clt_s.b [[R4:\$w[0-9]+]], [[R2]], [[R1]]
823 %4 = select <16 x i1> %3, <16 x i8> %1, <16 x i8> <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
824 ; CHECK-DAG: bseli.b [[R4]], [[R1]], 1
825 store <16 x i8> %4, <16 x i8>* %d
826 ; CHECK-DAG: st.b [[R4]], 0($4)
829 ; CHECK: .size bseli_s_v16i8
832 define void @bseli_s_v8i16(<8 x i16>* %d, <8 x i16>* %a, <8 x i16>* %b,
833 <8 x i16>* %c) nounwind {
834 ; CHECK: bseli_s_v8i16:
836 %1 = load <8 x i16>* %a
837 ; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5)
838 %2 = load <8 x i16>* %b
839 ; CHECK-DAG: ld.h [[R2:\$w[0-9]+]], 0($6)
840 %3 = icmp sgt <8 x i16> %1, %2
841 ; CHECK-DAG: clt_s.h [[R4:\$w[0-9]+]], [[R2]], [[R1]]
842 %4 = select <8 x i1> %3, <8 x i16> %1, <8 x i16> <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
843 ; CHECK-DAG: ldi.h [[R3:\$w[0-9]+]], 1
844 ; CHECK-DAG: bsel.v [[R4]], [[R1]], [[R3]]
845 store <8 x i16> %4, <8 x i16>* %d
846 ; CHECK-DAG: st.h [[R4]], 0($4)
849 ; CHECK: .size bseli_s_v8i16
852 define void @bseli_s_v4i32(<4 x i32>* %d, <4 x i32>* %a, <4 x i32>* %b,
853 <4 x i32>* %c) nounwind {
854 ; CHECK: bseli_s_v4i32:
856 %1 = load <4 x i32>* %a
857 ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
858 %2 = load <4 x i32>* %b
859 ; CHECK-DAG: ld.w [[R2:\$w[0-9]+]], 0($6)
860 %3 = icmp sgt <4 x i32> %1, %2
861 ; CHECK-DAG: clt_s.w [[R4:\$w[0-9]+]], [[R2]], [[R1]]
862 %4 = select <4 x i1> %3, <4 x i32> %1, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
863 ; CHECK-DAG: ldi.w [[R3:\$w[0-9]+]], 1
864 ; CHECK-DAG: bsel.v [[R4]], [[R1]], [[R3]]
865 store <4 x i32> %4, <4 x i32>* %d
866 ; CHECK-DAG: st.w [[R4]], 0($4)
869 ; CHECK: .size bseli_s_v4i32
872 define void @bseli_s_v2i64(<2 x i64>* %d, <2 x i64>* %a, <2 x i64>* %b,
873 <2 x i64>* %c) nounwind {
874 ; CHECK: bseli_s_v2i64:
876 %1 = load <2 x i64>* %a
877 ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
878 %2 = load <2 x i64>* %b
879 ; CHECK-DAG: ld.d [[R2:\$w[0-9]+]], 0($6)
880 %3 = icmp sgt <2 x i64> %1, %2
881 ; CHECK-DAG: clt_s.d [[R4:\$w[0-9]+]], [[R2]], [[R1]]
882 %4 = select <2 x i1> %3, <2 x i64> %1, <2 x i64> <i64 1, i64 1>
883 ; CHECK-DAG: ldi.d [[R3:\$w[0-9]+]], 1
884 ; CHECK-DAG: bsel.v [[R4]], [[R1]], [[R3]]
885 store <2 x i64> %4, <2 x i64>* %d
886 ; CHECK-DAG: st.d [[R4]], 0($4)
889 ; CHECK: .size bseli_s_v2i64
892 define void @bseli_u_v16i8(<16 x i8>* %d, <16 x i8>* %a, <16 x i8>* %b,
893 <16 x i8>* %c) nounwind {
894 ; CHECK: bseli_u_v16i8:
896 %1 = load <16 x i8>* %a
897 ; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5)
898 %2 = load <16 x i8>* %b
899 ; CHECK-DAG: ld.b [[R2:\$w[0-9]+]], 0($6)
900 %3 = icmp ugt <16 x i8> %1, %2
901 ; CHECK-DAG: clt_u.b [[R4:\$w[0-9]+]], [[R2]], [[R1]]
902 %4 = select <16 x i1> %3, <16 x i8> %1, <16 x i8> <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
903 ; CHECK-DAG: bseli.b [[R4]], [[R1]], 1
904 store <16 x i8> %4, <16 x i8>* %d
905 ; CHECK-DAG: st.b [[R4]], 0($4)
908 ; CHECK: .size bseli_u_v16i8
911 define void @bseli_u_v8i16(<8 x i16>* %d, <8 x i16>* %a, <8 x i16>* %b,
912 <8 x i16>* %c) nounwind {
913 ; CHECK: bseli_u_v8i16:
915 %1 = load <8 x i16>* %a
916 ; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5)
917 %2 = load <8 x i16>* %b
918 ; CHECK-DAG: ld.h [[R2:\$w[0-9]+]], 0($6)
919 %3 = icmp ugt <8 x i16> %1, %2
920 ; CHECK-DAG: clt_u.h [[R4:\$w[0-9]+]], [[R2]], [[R1]]
921 %4 = select <8 x i1> %3, <8 x i16> %1, <8 x i16> <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
922 ; CHECK-DAG: ldi.h [[R3:\$w[0-9]+]], 1
923 ; CHECK-DAG: bsel.v [[R4]], [[R1]], [[R3]]
924 store <8 x i16> %4, <8 x i16>* %d
925 ; CHECK-DAG: st.h [[R4]], 0($4)
928 ; CHECK: .size bseli_u_v8i16
931 define void @bseli_u_v4i32(<4 x i32>* %d, <4 x i32>* %a, <4 x i32>* %b,
932 <4 x i32>* %c) nounwind {
933 ; CHECK: bseli_u_v4i32:
935 %1 = load <4 x i32>* %a
936 ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
937 %2 = load <4 x i32>* %b
938 ; CHECK-DAG: ld.w [[R2:\$w[0-9]+]], 0($6)
939 %3 = icmp ugt <4 x i32> %1, %2
940 ; CHECK-DAG: clt_u.w [[R4:\$w[0-9]+]], [[R2]], [[R1]]
941 %4 = select <4 x i1> %3, <4 x i32> %1, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
942 ; CHECK-DAG: ldi.w [[R3:\$w[0-9]+]], 1
943 ; CHECK-DAG: bsel.v [[R4]], [[R1]], [[R3]]
944 store <4 x i32> %4, <4 x i32>* %d
945 ; CHECK-DAG: st.w [[R4]], 0($4)
948 ; CHECK: .size bseli_u_v4i32
951 define void @bseli_u_v2i64(<2 x i64>* %d, <2 x i64>* %a, <2 x i64>* %b,
952 <2 x i64>* %c) nounwind {
953 ; CHECK: bseli_u_v2i64:
955 %1 = load <2 x i64>* %a
956 ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
957 %2 = load <2 x i64>* %b
958 ; CHECK-DAG: ld.d [[R2:\$w[0-9]+]], 0($6)
959 %3 = icmp ugt <2 x i64> %1, %2
960 ; CHECK-DAG: clt_u.d [[R4:\$w[0-9]+]], [[R2]], [[R1]]
961 %4 = select <2 x i1> %3, <2 x i64> %1, <2 x i64> <i64 1, i64 1>
962 ; CHECK-DAG: ldi.d [[R3:\$w[0-9]+]], 1
963 ; CHECK-DAG: bsel.v [[R4]], [[R1]], [[R3]]
964 store <2 x i64> %4, <2 x i64>* %d
965 ; CHECK-DAG: st.d [[R4]], 0($4)
968 ; CHECK: .size bseli_u_v2i64
971 define void @max_s_v16i8(<16 x i8>* %c, <16 x i8>* %a, <16 x i8>* %b) nounwind {
972 ; CHECK: max_s_v16i8:
974 %1 = load <16 x i8>* %a
975 ; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5)
976 %2 = load <16 x i8>* %b
977 ; CHECK-DAG: ld.b [[R2:\$w[0-9]+]], 0($6)
978 %3 = icmp sgt <16 x i8> %1, %2
979 %4 = select <16 x i1> %3, <16 x i8> %1, <16 x i8> %2
980 ; CHECK-DAG: max_s.b [[R3:\$w[0-9]+]], [[R1]], [[R2]]
981 store <16 x i8> %4, <16 x i8>* %c
982 ; CHECK-DAG: st.b [[R3]], 0($4)
985 ; CHECK: .size max_s_v16i8
988 define void @max_s_v8i16(<8 x i16>* %c, <8 x i16>* %a, <8 x i16>* %b) nounwind {
989 ; CHECK: max_s_v8i16:
991 %1 = load <8 x i16>* %a
992 ; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5)
993 %2 = load <8 x i16>* %b
994 ; CHECK-DAG: ld.h [[R2:\$w[0-9]+]], 0($6)
995 %3 = icmp sgt <8 x i16> %1, %2
996 %4 = select <8 x i1> %3, <8 x i16> %1, <8 x i16> %2
997 ; CHECK-DAG: max_s.h [[R3:\$w[0-9]+]], [[R1]], [[R2]]
998 store <8 x i16> %4, <8 x i16>* %c
999 ; CHECK-DAG: st.h [[R3]], 0($4)
1002 ; CHECK: .size max_s_v8i16
1005 define void @max_s_v4i32(<4 x i32>* %c, <4 x i32>* %a, <4 x i32>* %b) nounwind {
1006 ; CHECK: max_s_v4i32:
1008 %1 = load <4 x i32>* %a
1009 ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
1010 %2 = load <4 x i32>* %b
1011 ; CHECK-DAG: ld.w [[R2:\$w[0-9]+]], 0($6)
1012 %3 = icmp sgt <4 x i32> %1, %2
1013 %4 = select <4 x i1> %3, <4 x i32> %1, <4 x i32> %2
1014 ; CHECK-DAG: max_s.w [[R3:\$w[0-9]+]], [[R1]], [[R2]]
1015 store <4 x i32> %4, <4 x i32>* %c
1016 ; CHECK-DAG: st.w [[R3]], 0($4)
1019 ; CHECK: .size max_s_v4i32
1022 define void @max_s_v2i64(<2 x i64>* %c, <2 x i64>* %a, <2 x i64>* %b) nounwind {
1023 ; CHECK: max_s_v2i64:
1025 %1 = load <2 x i64>* %a
1026 ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
1027 %2 = load <2 x i64>* %b
1028 ; CHECK-DAG: ld.d [[R2:\$w[0-9]+]], 0($6)
1029 %3 = icmp sgt <2 x i64> %1, %2
1030 %4 = select <2 x i1> %3, <2 x i64> %1, <2 x i64> %2
1031 ; CHECK-DAG: max_s.d [[R3:\$w[0-9]+]], [[R1]], [[R2]]
1032 store <2 x i64> %4, <2 x i64>* %c
1033 ; CHECK-DAG: st.d [[R3]], 0($4)
1036 ; CHECK: .size max_s_v2i64
1039 define void @max_u_v16i8(<16 x i8>* %c, <16 x i8>* %a, <16 x i8>* %b) nounwind {
1040 ; CHECK: max_u_v16i8:
1042 %1 = load <16 x i8>* %a
1043 ; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5)
1044 %2 = load <16 x i8>* %b
1045 ; CHECK-DAG: ld.b [[R2:\$w[0-9]+]], 0($6)
1046 %3 = icmp ugt <16 x i8> %1, %2
1047 %4 = select <16 x i1> %3, <16 x i8> %1, <16 x i8> %2
1048 ; CHECK-DAG: max_u.b [[R3:\$w[0-9]+]], [[R1]], [[R2]]
1049 store <16 x i8> %4, <16 x i8>* %c
1050 ; CHECK-DAG: st.b [[R3]], 0($4)
1053 ; CHECK: .size max_u_v16i8
1056 define void @max_u_v8i16(<8 x i16>* %c, <8 x i16>* %a, <8 x i16>* %b) nounwind {
1057 ; CHECK: max_u_v8i16:
1059 %1 = load <8 x i16>* %a
1060 ; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5)
1061 %2 = load <8 x i16>* %b
1062 ; CHECK-DAG: ld.h [[R2:\$w[0-9]+]], 0($6)
1063 %3 = icmp ugt <8 x i16> %1, %2
1064 %4 = select <8 x i1> %3, <8 x i16> %1, <8 x i16> %2
1065 ; CHECK-DAG: max_u.h [[R3:\$w[0-9]+]], [[R1]], [[R2]]
1066 store <8 x i16> %4, <8 x i16>* %c
1067 ; CHECK-DAG: st.h [[R3]], 0($4)
1070 ; CHECK: .size max_u_v8i16
1073 define void @max_u_v4i32(<4 x i32>* %c, <4 x i32>* %a, <4 x i32>* %b) nounwind {
1074 ; CHECK: max_u_v4i32:
1076 %1 = load <4 x i32>* %a
1077 ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
1078 %2 = load <4 x i32>* %b
1079 ; CHECK-DAG: ld.w [[R2:\$w[0-9]+]], 0($6)
1080 %3 = icmp ugt <4 x i32> %1, %2
1081 %4 = select <4 x i1> %3, <4 x i32> %1, <4 x i32> %2
1082 ; CHECK-DAG: max_u.w [[R3:\$w[0-9]+]], [[R1]], [[R2]]
1083 store <4 x i32> %4, <4 x i32>* %c
1084 ; CHECK-DAG: st.w [[R3]], 0($4)
1087 ; CHECK: .size max_u_v4i32
1090 define void @max_u_v2i64(<2 x i64>* %c, <2 x i64>* %a, <2 x i64>* %b) nounwind {
1091 ; CHECK: max_u_v2i64:
1093 %1 = load <2 x i64>* %a
1094 ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
1095 %2 = load <2 x i64>* %b
1096 ; CHECK-DAG: ld.d [[R2:\$w[0-9]+]], 0($6)
1097 %3 = icmp ugt <2 x i64> %1, %2
1098 %4 = select <2 x i1> %3, <2 x i64> %1, <2 x i64> %2
1099 ; CHECK-DAG: max_u.d [[R3:\$w[0-9]+]], [[R1]], [[R2]]
1100 store <2 x i64> %4, <2 x i64>* %c
1101 ; CHECK-DAG: st.d [[R3]], 0($4)
1104 ; CHECK: .size max_u_v2i64
1107 define void @max_s_eq_v16i8(<16 x i8>* %c, <16 x i8>* %a, <16 x i8>* %b) nounwind {
1108 ; CHECK: max_s_eq_v16i8:
1110 %1 = load <16 x i8>* %a
1111 ; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5)
1112 %2 = load <16 x i8>* %b
1113 ; CHECK-DAG: ld.b [[R2:\$w[0-9]+]], 0($6)
1114 %3 = icmp sge <16 x i8> %1, %2
1115 %4 = select <16 x i1> %3, <16 x i8> %1, <16 x i8> %2
1116 ; CHECK-DAG: max_s.b [[R3:\$w[0-9]+]], [[R1]], [[R2]]
1117 store <16 x i8> %4, <16 x i8>* %c
1118 ; CHECK-DAG: st.b [[R3]], 0($4)
1121 ; CHECK: .size max_s_eq_v16i8
1124 define void @max_s_eq_v8i16(<8 x i16>* %c, <8 x i16>* %a, <8 x i16>* %b) nounwind {
1125 ; CHECK: max_s_eq_v8i16:
1127 %1 = load <8 x i16>* %a
1128 ; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5)
1129 %2 = load <8 x i16>* %b
1130 ; CHECK-DAG: ld.h [[R2:\$w[0-9]+]], 0($6)
1131 %3 = icmp sge <8 x i16> %1, %2
1132 %4 = select <8 x i1> %3, <8 x i16> %1, <8 x i16> %2
1133 ; CHECK-DAG: max_s.h [[R3:\$w[0-9]+]], [[R1]], [[R2]]
1134 store <8 x i16> %4, <8 x i16>* %c
1135 ; CHECK-DAG: st.h [[R3]], 0($4)
1138 ; CHECK: .size max_s_eq_v8i16
1141 define void @max_s_eq_v4i32(<4 x i32>* %c, <4 x i32>* %a, <4 x i32>* %b) nounwind {
1142 ; CHECK: max_s_eq_v4i32:
1144 %1 = load <4 x i32>* %a
1145 ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
1146 %2 = load <4 x i32>* %b
1147 ; CHECK-DAG: ld.w [[R2:\$w[0-9]+]], 0($6)
1148 %3 = icmp sge <4 x i32> %1, %2
1149 %4 = select <4 x i1> %3, <4 x i32> %1, <4 x i32> %2
1150 ; CHECK-DAG: max_s.w [[R3:\$w[0-9]+]], [[R1]], [[R2]]
1151 store <4 x i32> %4, <4 x i32>* %c
1152 ; CHECK-DAG: st.w [[R3]], 0($4)
1155 ; CHECK: .size max_s_eq_v4i32
1158 define void @max_s_eq_v2i64(<2 x i64>* %c, <2 x i64>* %a, <2 x i64>* %b) nounwind {
1159 ; CHECK: max_s_eq_v2i64:
1161 %1 = load <2 x i64>* %a
1162 ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
1163 %2 = load <2 x i64>* %b
1164 ; CHECK-DAG: ld.d [[R2:\$w[0-9]+]], 0($6)
1165 %3 = icmp sge <2 x i64> %1, %2
1166 %4 = select <2 x i1> %3, <2 x i64> %1, <2 x i64> %2
1167 ; CHECK-DAG: max_s.d [[R3:\$w[0-9]+]], [[R1]], [[R2]]
1168 store <2 x i64> %4, <2 x i64>* %c
1169 ; CHECK-DAG: st.d [[R3]], 0($4)
1172 ; CHECK: .size max_s_eq_v2i64
1175 define void @max_u_eq_v16i8(<16 x i8>* %c, <16 x i8>* %a, <16 x i8>* %b) nounwind {
1176 ; CHECK: max_u_eq_v16i8:
1178 %1 = load <16 x i8>* %a
1179 ; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5)
1180 %2 = load <16 x i8>* %b
1181 ; CHECK-DAG: ld.b [[R2:\$w[0-9]+]], 0($6)
1182 %3 = icmp uge <16 x i8> %1, %2
1183 %4 = select <16 x i1> %3, <16 x i8> %1, <16 x i8> %2
1184 ; CHECK-DAG: max_u.b [[R3:\$w[0-9]+]], [[R1]], [[R2]]
1185 store <16 x i8> %4, <16 x i8>* %c
1186 ; CHECK-DAG: st.b [[R3]], 0($4)
1189 ; CHECK: .size max_u_eq_v16i8
1192 define void @max_u_eq_v8i16(<8 x i16>* %c, <8 x i16>* %a, <8 x i16>* %b) nounwind {
1193 ; CHECK: max_u_eq_v8i16:
1195 %1 = load <8 x i16>* %a
1196 ; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5)
1197 %2 = load <8 x i16>* %b
1198 ; CHECK-DAG: ld.h [[R2:\$w[0-9]+]], 0($6)
1199 %3 = icmp uge <8 x i16> %1, %2
1200 %4 = select <8 x i1> %3, <8 x i16> %1, <8 x i16> %2
1201 ; CHECK-DAG: max_u.h [[R3:\$w[0-9]+]], [[R1]], [[R2]]
1202 store <8 x i16> %4, <8 x i16>* %c
1203 ; CHECK-DAG: st.h [[R3]], 0($4)
1206 ; CHECK: .size max_u_eq_v8i16
1209 define void @max_u_eq_v4i32(<4 x i32>* %c, <4 x i32>* %a, <4 x i32>* %b) nounwind {
1210 ; CHECK: max_u_eq_v4i32:
1212 %1 = load <4 x i32>* %a
1213 ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
1214 %2 = load <4 x i32>* %b
1215 ; CHECK-DAG: ld.w [[R2:\$w[0-9]+]], 0($6)
1216 %3 = icmp uge <4 x i32> %1, %2
1217 %4 = select <4 x i1> %3, <4 x i32> %1, <4 x i32> %2
1218 ; CHECK-DAG: max_u.w [[R3:\$w[0-9]+]], [[R1]], [[R2]]
1219 store <4 x i32> %4, <4 x i32>* %c
1220 ; CHECK-DAG: st.w [[R3]], 0($4)
1223 ; CHECK: .size max_u_eq_v4i32
1226 define void @max_u_eq_v2i64(<2 x i64>* %c, <2 x i64>* %a, <2 x i64>* %b) nounwind {
1227 ; CHECK: max_u_eq_v2i64:
1229 %1 = load <2 x i64>* %a
1230 ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
1231 %2 = load <2 x i64>* %b
1232 ; CHECK-DAG: ld.d [[R2:\$w[0-9]+]], 0($6)
1233 %3 = icmp uge <2 x i64> %1, %2
1234 %4 = select <2 x i1> %3, <2 x i64> %1, <2 x i64> %2
1235 ; CHECK-DAG: max_u.d [[R3:\$w[0-9]+]], [[R1]], [[R2]]
1236 store <2 x i64> %4, <2 x i64>* %c
1237 ; CHECK-DAG: st.d [[R3]], 0($4)
1240 ; CHECK: .size max_u_eq_v2i64
1243 define void @maxi_s_v16i8(<16 x i8>* %c, <16 x i8>* %a) nounwind {
1244 ; CHECK: maxi_s_v16i8:
1246 %1 = load <16 x i8>* %a
1247 ; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5)
1248 %2 = icmp sgt <16 x i8> %1, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
1249 %3 = select <16 x i1> %2, <16 x i8> %1, <16 x i8> <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
1250 ; CHECK-DAG: maxi_s.b [[R3:\$w[0-9]+]], [[R1]], 1
1251 store <16 x i8> %3, <16 x i8>* %c
1252 ; CHECK-DAG: st.b [[R3]], 0($4)
1255 ; CHECK: .size maxi_s_v16i8
1258 define void @maxi_s_v8i16(<8 x i16>* %c, <8 x i16>* %a) nounwind {
1259 ; CHECK: maxi_s_v8i16:
1261 %1 = load <8 x i16>* %a
1262 ; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5)
1263 %2 = icmp sgt <8 x i16> %1, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
1264 %3 = select <8 x i1> %2, <8 x i16> %1, <8 x i16> <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
1265 ; CHECK-DAG: maxi_s.h [[R3:\$w[0-9]+]], [[R1]], 1
1266 store <8 x i16> %3, <8 x i16>* %c
1267 ; CHECK-DAG: st.h [[R3]], 0($4)
1270 ; CHECK: .size maxi_s_v8i16
1273 define void @maxi_s_v4i32(<4 x i32>* %c, <4 x i32>* %a) nounwind {
1274 ; CHECK: maxi_s_v4i32:
1276 %1 = load <4 x i32>* %a
1277 ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
1278 %2 = icmp sgt <4 x i32> %1, <i32 1, i32 1, i32 1, i32 1>
1279 %3 = select <4 x i1> %2, <4 x i32> %1, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
1280 ; CHECK-DAG: maxi_s.w [[R3:\$w[0-9]+]], [[R1]], 1
1281 store <4 x i32> %3, <4 x i32>* %c
1282 ; CHECK-DAG: st.w [[R3]], 0($4)
1285 ; CHECK: .size maxi_s_v4i32
1288 define void @maxi_s_v2i64(<2 x i64>* %c, <2 x i64>* %a) nounwind {
1289 ; CHECK: maxi_s_v2i64:
1291 %1 = load <2 x i64>* %a
1292 ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
1293 %2 = icmp sgt <2 x i64> %1, <i64 1, i64 1>
1294 %3 = select <2 x i1> %2, <2 x i64> %1, <2 x i64> <i64 1, i64 1>
1295 ; CHECK-DAG: maxi_s.d [[R3:\$w[0-9]+]], [[R1]], 1
1296 store <2 x i64> %3, <2 x i64>* %c
1297 ; CHECK-DAG: st.d [[R3]], 0($4)
1300 ; CHECK: .size maxi_s_v2i64
1303 define void @maxi_u_v16i8(<16 x i8>* %c, <16 x i8>* %a) nounwind {
1304 ; CHECK: maxi_u_v16i8:
1306 %1 = load <16 x i8>* %a
1307 ; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5)
1308 %2 = icmp ugt <16 x i8> %1, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
1309 %3 = select <16 x i1> %2, <16 x i8> %1, <16 x i8> <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
1310 ; CHECK-DAG: maxi_u.b [[R3:\$w[0-9]+]], [[R1]], 1
1311 store <16 x i8> %3, <16 x i8>* %c
1312 ; CHECK-DAG: st.b [[R3]], 0($4)
1315 ; CHECK: .size maxi_u_v16i8
1318 define void @maxi_u_v8i16(<8 x i16>* %c, <8 x i16>* %a) nounwind {
1319 ; CHECK: maxi_u_v8i16:
1321 %1 = load <8 x i16>* %a
1322 ; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5)
1323 %2 = icmp ugt <8 x i16> %1, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
1324 %3 = select <8 x i1> %2, <8 x i16> %1, <8 x i16> <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
1325 ; CHECK-DAG: maxi_u.h [[R3:\$w[0-9]+]], [[R1]], 1
1326 store <8 x i16> %3, <8 x i16>* %c
1327 ; CHECK-DAG: st.h [[R3]], 0($4)
1330 ; CHECK: .size maxi_u_v8i16
1333 define void @maxi_u_v4i32(<4 x i32>* %c, <4 x i32>* %a) nounwind {
1334 ; CHECK: maxi_u_v4i32:
1336 %1 = load <4 x i32>* %a
1337 ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
1338 %2 = icmp ugt <4 x i32> %1, <i32 1, i32 1, i32 1, i32 1>
1339 %3 = select <4 x i1> %2, <4 x i32> %1, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
1340 ; CHECK-DAG: maxi_u.w [[R3:\$w[0-9]+]], [[R1]], 1
1341 store <4 x i32> %3, <4 x i32>* %c
1342 ; CHECK-DAG: st.w [[R3]], 0($4)
1345 ; CHECK: .size maxi_u_v4i32
1348 define void @maxi_u_v2i64(<2 x i64>* %c, <2 x i64>* %a) nounwind {
1349 ; CHECK: maxi_u_v2i64:
1351 %1 = load <2 x i64>* %a
1352 ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
1353 %2 = icmp ugt <2 x i64> %1, <i64 1, i64 1>
1354 %3 = select <2 x i1> %2, <2 x i64> %1, <2 x i64> <i64 1, i64 1>
1355 ; CHECK-DAG: maxi_u.d [[R3:\$w[0-9]+]], [[R1]], 1
1356 store <2 x i64> %3, <2 x i64>* %c
1357 ; CHECK-DAG: st.d [[R3]], 0($4)
1360 ; CHECK: .size maxi_u_v2i64
1363 define void @maxi_s_eq_v16i8(<16 x i8>* %c, <16 x i8>* %a) nounwind {
1364 ; CHECK: maxi_s_eq_v16i8:
1366 %1 = load <16 x i8>* %a
1367 ; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5)
1368 %2 = icmp sge <16 x i8> %1, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
1369 %3 = select <16 x i1> %2, <16 x i8> %1, <16 x i8> <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
1370 ; CHECK-DAG: maxi_s.b [[R3:\$w[0-9]+]], [[R1]], 1
1371 store <16 x i8> %3, <16 x i8>* %c
1372 ; CHECK-DAG: st.b [[R3]], 0($4)
1375 ; CHECK: .size maxi_s_eq_v16i8
1378 define void @maxi_s_eq_v8i16(<8 x i16>* %c, <8 x i16>* %a) nounwind {
1379 ; CHECK: maxi_s_eq_v8i16:
1381 %1 = load <8 x i16>* %a
1382 ; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5)
1383 %2 = icmp sge <8 x i16> %1, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
1384 %3 = select <8 x i1> %2, <8 x i16> %1, <8 x i16> <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
1385 ; CHECK-DAG: maxi_s.h [[R3:\$w[0-9]+]], [[R1]], 1
1386 store <8 x i16> %3, <8 x i16>* %c
1387 ; CHECK-DAG: st.h [[R3]], 0($4)
1390 ; CHECK: .size maxi_s_eq_v8i16
1393 define void @maxi_s_eq_v4i32(<4 x i32>* %c, <4 x i32>* %a) nounwind {
1394 ; CHECK: maxi_s_eq_v4i32:
1396 %1 = load <4 x i32>* %a
1397 ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
1398 %2 = icmp sge <4 x i32> %1, <i32 1, i32 1, i32 1, i32 1>
1399 %3 = select <4 x i1> %2, <4 x i32> %1, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
1400 ; CHECK-DAG: maxi_s.w [[R3:\$w[0-9]+]], [[R1]], 1
1401 store <4 x i32> %3, <4 x i32>* %c
1402 ; CHECK-DAG: st.w [[R3]], 0($4)
1405 ; CHECK: .size maxi_s_eq_v4i32
1408 define void @maxi_s_eq_v2i64(<2 x i64>* %c, <2 x i64>* %a) nounwind {
1409 ; CHECK: maxi_s_eq_v2i64:
1411 %1 = load <2 x i64>* %a
1412 ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
1413 %2 = icmp sge <2 x i64> %1, <i64 1, i64 1>
1414 %3 = select <2 x i1> %2, <2 x i64> %1, <2 x i64> <i64 1, i64 1>
1415 ; CHECK-DAG: maxi_s.d [[R3:\$w[0-9]+]], [[R1]], 1
1416 store <2 x i64> %3, <2 x i64>* %c
1417 ; CHECK-DAG: st.d [[R3]], 0($4)
1420 ; CHECK: .size maxi_s_eq_v2i64
1423 define void @maxi_u_eq_v16i8(<16 x i8>* %c, <16 x i8>* %a) nounwind {
1424 ; CHECK: maxi_u_eq_v16i8:
1426 %1 = load <16 x i8>* %a
1427 ; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5)
1428 %2 = icmp uge <16 x i8> %1, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
1429 %3 = select <16 x i1> %2, <16 x i8> %1, <16 x i8> <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
1430 ; CHECK-DAG: maxi_u.b [[R3:\$w[0-9]+]], [[R1]], 1
1431 store <16 x i8> %3, <16 x i8>* %c
1432 ; CHECK-DAG: st.b [[R3]], 0($4)
1435 ; CHECK: .size maxi_u_eq_v16i8
1438 define void @maxi_u_eq_v8i16(<8 x i16>* %c, <8 x i16>* %a) nounwind {
1439 ; CHECK: maxi_u_eq_v8i16:
1441 %1 = load <8 x i16>* %a
1442 ; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5)
1443 %2 = icmp uge <8 x i16> %1, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
1444 %3 = select <8 x i1> %2, <8 x i16> %1, <8 x i16> <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
1445 ; CHECK-DAG: maxi_u.h [[R3:\$w[0-9]+]], [[R1]], 1
1446 store <8 x i16> %3, <8 x i16>* %c
1447 ; CHECK-DAG: st.h [[R3]], 0($4)
1450 ; CHECK: .size maxi_u_eq_v8i16
1453 define void @maxi_u_eq_v4i32(<4 x i32>* %c, <4 x i32>* %a) nounwind {
1454 ; CHECK: maxi_u_eq_v4i32:
1456 %1 = load <4 x i32>* %a
1457 ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
1458 %2 = icmp uge <4 x i32> %1, <i32 1, i32 1, i32 1, i32 1>
1459 %3 = select <4 x i1> %2, <4 x i32> %1, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
1460 ; CHECK-DAG: maxi_u.w [[R3:\$w[0-9]+]], [[R1]], 1
1461 store <4 x i32> %3, <4 x i32>* %c
1462 ; CHECK-DAG: st.w [[R3]], 0($4)
1465 ; CHECK: .size maxi_u_eq_v4i32
1468 define void @maxi_u_eq_v2i64(<2 x i64>* %c, <2 x i64>* %a) nounwind {
1469 ; CHECK: maxi_u_eq_v2i64:
1471 %1 = load <2 x i64>* %a
1472 ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
1473 %2 = icmp uge <2 x i64> %1, <i64 1, i64 1>
1474 %3 = select <2 x i1> %2, <2 x i64> %1, <2 x i64> <i64 1, i64 1>
1475 ; CHECK-DAG: maxi_u.d [[R3:\$w[0-9]+]], [[R1]], 1
1476 store <2 x i64> %3, <2 x i64>* %c
1477 ; CHECK-DAG: st.d [[R3]], 0($4)
1480 ; CHECK: .size maxi_u_eq_v2i64
1483 define void @min_s_v16i8(<16 x i8>* %c, <16 x i8>* %a, <16 x i8>* %b) nounwind {
1484 ; CHECK: min_s_v16i8:
1486 %1 = load <16 x i8>* %a
1487 ; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5)
1488 %2 = load <16 x i8>* %b
1489 ; CHECK-DAG: ld.b [[R2:\$w[0-9]+]], 0($6)
1490 %3 = icmp sle <16 x i8> %1, %2
1491 %4 = select <16 x i1> %3, <16 x i8> %1, <16 x i8> %2
1492 ; CHECK-DAG: min_s.b [[R3:\$w[0-9]+]], [[R1]], [[R2]]
1493 store <16 x i8> %4, <16 x i8>* %c
1494 ; CHECK-DAG: st.b [[R3]], 0($4)
1497 ; CHECK: .size min_s_v16i8
1500 define void @min_s_v8i16(<8 x i16>* %c, <8 x i16>* %a, <8 x i16>* %b) nounwind {
1501 ; CHECK: min_s_v8i16:
1503 %1 = load <8 x i16>* %a
1504 ; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5)
1505 %2 = load <8 x i16>* %b
1506 ; CHECK-DAG: ld.h [[R2:\$w[0-9]+]], 0($6)
1507 %3 = icmp slt <8 x i16> %1, %2
1508 %4 = select <8 x i1> %3, <8 x i16> %1, <8 x i16> %2
1509 ; CHECK-DAG: min_s.h [[R3:\$w[0-9]+]], [[R1]], [[R2]]
1510 store <8 x i16> %4, <8 x i16>* %c
1511 ; CHECK-DAG: st.h [[R3]], 0($4)
1514 ; CHECK: .size min_s_v8i16
1517 define void @min_s_v4i32(<4 x i32>* %c, <4 x i32>* %a, <4 x i32>* %b) nounwind {
1518 ; CHECK: min_s_v4i32:
1520 %1 = load <4 x i32>* %a
1521 ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
1522 %2 = load <4 x i32>* %b
1523 ; CHECK-DAG: ld.w [[R2:\$w[0-9]+]], 0($6)
1524 %3 = icmp slt <4 x i32> %1, %2
1525 %4 = select <4 x i1> %3, <4 x i32> %1, <4 x i32> %2
1526 ; CHECK-DAG: min_s.w [[R3:\$w[0-9]+]], [[R1]], [[R2]]
1527 store <4 x i32> %4, <4 x i32>* %c
1528 ; CHECK-DAG: st.w [[R3]], 0($4)
1531 ; CHECK: .size min_s_v4i32
1534 define void @min_s_v2i64(<2 x i64>* %c, <2 x i64>* %a, <2 x i64>* %b) nounwind {
1535 ; CHECK: min_s_v2i64:
1537 %1 = load <2 x i64>* %a
1538 ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
1539 %2 = load <2 x i64>* %b
1540 ; CHECK-DAG: ld.d [[R2:\$w[0-9]+]], 0($6)
1541 %3 = icmp slt <2 x i64> %1, %2
1542 %4 = select <2 x i1> %3, <2 x i64> %1, <2 x i64> %2
1543 ; CHECK-DAG: min_s.d [[R3:\$w[0-9]+]], [[R1]], [[R2]]
1544 store <2 x i64> %4, <2 x i64>* %c
1545 ; CHECK-DAG: st.d [[R3]], 0($4)
1548 ; CHECK: .size min_s_v2i64
1551 define void @min_u_v16i8(<16 x i8>* %c, <16 x i8>* %a, <16 x i8>* %b) nounwind {
1552 ; CHECK: min_u_v16i8:
1554 %1 = load <16 x i8>* %a
1555 ; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5)
1556 %2 = load <16 x i8>* %b
1557 ; CHECK-DAG: ld.b [[R2:\$w[0-9]+]], 0($6)
1558 %3 = icmp ult <16 x i8> %1, %2
1559 %4 = select <16 x i1> %3, <16 x i8> %1, <16 x i8> %2
1560 ; CHECK-DAG: min_u.b [[R3:\$w[0-9]+]], [[R1]], [[R2]]
1561 store <16 x i8> %4, <16 x i8>* %c
1562 ; CHECK-DAG: st.b [[R3]], 0($4)
1565 ; CHECK: .size min_u_v16i8
1568 define void @min_u_v8i16(<8 x i16>* %c, <8 x i16>* %a, <8 x i16>* %b) nounwind {
1569 ; CHECK: min_u_v8i16:
1571 %1 = load <8 x i16>* %a
1572 ; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5)
1573 %2 = load <8 x i16>* %b
1574 ; CHECK-DAG: ld.h [[R2:\$w[0-9]+]], 0($6)
1575 %3 = icmp ult <8 x i16> %1, %2
1576 %4 = select <8 x i1> %3, <8 x i16> %1, <8 x i16> %2
1577 ; CHECK-DAG: min_u.h [[R3:\$w[0-9]+]], [[R1]], [[R2]]
1578 store <8 x i16> %4, <8 x i16>* %c
1579 ; CHECK-DAG: st.h [[R3]], 0($4)
1582 ; CHECK: .size min_u_v8i16
1585 define void @min_u_v4i32(<4 x i32>* %c, <4 x i32>* %a, <4 x i32>* %b) nounwind {
1586 ; CHECK: min_u_v4i32:
1588 %1 = load <4 x i32>* %a
1589 ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
1590 %2 = load <4 x i32>* %b
1591 ; CHECK-DAG: ld.w [[R2:\$w[0-9]+]], 0($6)
1592 %3 = icmp ult <4 x i32> %1, %2
1593 %4 = select <4 x i1> %3, <4 x i32> %1, <4 x i32> %2
1594 ; CHECK-DAG: min_u.w [[R3:\$w[0-9]+]], [[R1]], [[R2]]
1595 store <4 x i32> %4, <4 x i32>* %c
1596 ; CHECK-DAG: st.w [[R3]], 0($4)
1599 ; CHECK: .size min_u_v4i32
1602 define void @min_u_v2i64(<2 x i64>* %c, <2 x i64>* %a, <2 x i64>* %b) nounwind {
1603 ; CHECK: min_u_v2i64:
1605 %1 = load <2 x i64>* %a
1606 ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
1607 %2 = load <2 x i64>* %b
1608 ; CHECK-DAG: ld.d [[R2:\$w[0-9]+]], 0($6)
1609 %3 = icmp ult <2 x i64> %1, %2
1610 %4 = select <2 x i1> %3, <2 x i64> %1, <2 x i64> %2
1611 ; CHECK-DAG: min_u.d [[R3:\$w[0-9]+]], [[R1]], [[R2]]
1612 store <2 x i64> %4, <2 x i64>* %c
1613 ; CHECK-DAG: st.d [[R3]], 0($4)
1616 ; CHECK: .size min_u_v2i64
1619 define void @min_s_eq_v16i8(<16 x i8>* %c, <16 x i8>* %a, <16 x i8>* %b) nounwind {
1620 ; CHECK: min_s_eq_v16i8:
1622 %1 = load <16 x i8>* %a
1623 ; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5)
1624 %2 = load <16 x i8>* %b
1625 ; CHECK-DAG: ld.b [[R2:\$w[0-9]+]], 0($6)
1626 %3 = icmp sle <16 x i8> %1, %2
1627 %4 = select <16 x i1> %3, <16 x i8> %1, <16 x i8> %2
1628 ; CHECK-DAG: min_s.b [[R3:\$w[0-9]+]], [[R1]], [[R2]]
1629 store <16 x i8> %4, <16 x i8>* %c
1630 ; CHECK-DAG: st.b [[R3]], 0($4)
1633 ; CHECK: .size min_s_eq_v16i8
1636 define void @min_s_eq_v8i16(<8 x i16>* %c, <8 x i16>* %a, <8 x i16>* %b) nounwind {
1637 ; CHECK: min_s_eq_v8i16:
1639 %1 = load <8 x i16>* %a
1640 ; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5)
1641 %2 = load <8 x i16>* %b
1642 ; CHECK-DAG: ld.h [[R2:\$w[0-9]+]], 0($6)
1643 %3 = icmp sle <8 x i16> %1, %2
1644 %4 = select <8 x i1> %3, <8 x i16> %1, <8 x i16> %2
1645 ; CHECK-DAG: min_s.h [[R3:\$w[0-9]+]], [[R1]], [[R2]]
1646 store <8 x i16> %4, <8 x i16>* %c
1647 ; CHECK-DAG: st.h [[R3]], 0($4)
1650 ; CHECK: .size min_s_eq_v8i16
1653 define void @min_s_eq_v4i32(<4 x i32>* %c, <4 x i32>* %a, <4 x i32>* %b) nounwind {
1654 ; CHECK: min_s_eq_v4i32:
1656 %1 = load <4 x i32>* %a
1657 ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
1658 %2 = load <4 x i32>* %b
1659 ; CHECK-DAG: ld.w [[R2:\$w[0-9]+]], 0($6)
1660 %3 = icmp sle <4 x i32> %1, %2
1661 %4 = select <4 x i1> %3, <4 x i32> %1, <4 x i32> %2
1662 ; CHECK-DAG: min_s.w [[R3:\$w[0-9]+]], [[R1]], [[R2]]
1663 store <4 x i32> %4, <4 x i32>* %c
1664 ; CHECK-DAG: st.w [[R3]], 0($4)
1667 ; CHECK: .size min_s_eq_v4i32
1670 define void @min_s_eq_v2i64(<2 x i64>* %c, <2 x i64>* %a, <2 x i64>* %b) nounwind {
1671 ; CHECK: min_s_eq_v2i64:
1673 %1 = load <2 x i64>* %a
1674 ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
1675 %2 = load <2 x i64>* %b
1676 ; CHECK-DAG: ld.d [[R2:\$w[0-9]+]], 0($6)
1677 %3 = icmp sle <2 x i64> %1, %2
1678 %4 = select <2 x i1> %3, <2 x i64> %1, <2 x i64> %2
1679 ; CHECK-DAG: min_s.d [[R3:\$w[0-9]+]], [[R1]], [[R2]]
1680 store <2 x i64> %4, <2 x i64>* %c
1681 ; CHECK-DAG: st.d [[R3]], 0($4)
1684 ; CHECK: .size min_s_eq_v2i64
1687 define void @min_u_eq_v16i8(<16 x i8>* %c, <16 x i8>* %a, <16 x i8>* %b) nounwind {
1688 ; CHECK: min_u_eq_v16i8:
1690 %1 = load <16 x i8>* %a
1691 ; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5)
1692 %2 = load <16 x i8>* %b
1693 ; CHECK-DAG: ld.b [[R2:\$w[0-9]+]], 0($6)
1694 %3 = icmp ule <16 x i8> %1, %2
1695 %4 = select <16 x i1> %3, <16 x i8> %1, <16 x i8> %2
1696 ; CHECK-DAG: min_u.b [[R3:\$w[0-9]+]], [[R1]], [[R2]]
1697 store <16 x i8> %4, <16 x i8>* %c
1698 ; CHECK-DAG: st.b [[R3]], 0($4)
1701 ; CHECK: .size min_u_eq_v16i8
1704 define void @min_u_eq_v8i16(<8 x i16>* %c, <8 x i16>* %a, <8 x i16>* %b) nounwind {
1705 ; CHECK: min_u_eq_v8i16:
1707 %1 = load <8 x i16>* %a
1708 ; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5)
1709 %2 = load <8 x i16>* %b
1710 ; CHECK-DAG: ld.h [[R2:\$w[0-9]+]], 0($6)
1711 %3 = icmp ule <8 x i16> %1, %2
1712 %4 = select <8 x i1> %3, <8 x i16> %1, <8 x i16> %2
1713 ; CHECK-DAG: min_u.h [[R3:\$w[0-9]+]], [[R1]], [[R2]]
1714 store <8 x i16> %4, <8 x i16>* %c
1715 ; CHECK-DAG: st.h [[R3]], 0($4)
1718 ; CHECK: .size min_u_eq_v8i16
1721 define void @min_u_eq_v4i32(<4 x i32>* %c, <4 x i32>* %a, <4 x i32>* %b) nounwind {
1722 ; CHECK: min_u_eq_v4i32:
1724 %1 = load <4 x i32>* %a
1725 ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
1726 %2 = load <4 x i32>* %b
1727 ; CHECK-DAG: ld.w [[R2:\$w[0-9]+]], 0($6)
1728 %3 = icmp ule <4 x i32> %1, %2
1729 %4 = select <4 x i1> %3, <4 x i32> %1, <4 x i32> %2
1730 ; CHECK-DAG: min_u.w [[R3:\$w[0-9]+]], [[R1]], [[R2]]
1731 store <4 x i32> %4, <4 x i32>* %c
1732 ; CHECK-DAG: st.w [[R3]], 0($4)
1735 ; CHECK: .size min_u_eq_v4i32
1738 define void @min_u_eq_v2i64(<2 x i64>* %c, <2 x i64>* %a, <2 x i64>* %b) nounwind {
1739 ; CHECK: min_u_eq_v2i64:
1741 %1 = load <2 x i64>* %a
1742 ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
1743 %2 = load <2 x i64>* %b
1744 ; CHECK-DAG: ld.d [[R2:\$w[0-9]+]], 0($6)
1745 %3 = icmp ule <2 x i64> %1, %2
1746 %4 = select <2 x i1> %3, <2 x i64> %1, <2 x i64> %2
1747 ; CHECK-DAG: min_u.d [[R3:\$w[0-9]+]], [[R1]], [[R2]]
1748 store <2 x i64> %4, <2 x i64>* %c
1749 ; CHECK-DAG: st.d [[R3]], 0($4)
1752 ; CHECK: .size min_u_eq_v2i64
1755 define void @mini_s_v16i8(<16 x i8>* %c, <16 x i8>* %a) nounwind {
1756 ; CHECK: mini_s_v16i8:
1758 %1 = load <16 x i8>* %a
1759 ; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5)
1760 %2 = icmp slt <16 x i8> %1, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
1761 %3 = select <16 x i1> %2, <16 x i8> %1, <16 x i8> <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
1762 ; CHECK-DAG: mini_s.b [[R3:\$w[0-9]+]], [[R1]], 1
1763 store <16 x i8> %3, <16 x i8>* %c
1764 ; CHECK-DAG: st.b [[R3]], 0($4)
1767 ; CHECK: .size mini_s_v16i8
1770 define void @mini_s_v8i16(<8 x i16>* %c, <8 x i16>* %a) nounwind {
1771 ; CHECK: mini_s_v8i16:
1773 %1 = load <8 x i16>* %a
1774 ; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5)
1775 %2 = icmp slt <8 x i16> %1, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
1776 %3 = select <8 x i1> %2, <8 x i16> %1, <8 x i16> <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
1777 ; CHECK-DAG: mini_s.h [[R3:\$w[0-9]+]], [[R1]], 1
1778 store <8 x i16> %3, <8 x i16>* %c
1779 ; CHECK-DAG: st.h [[R3]], 0($4)
1782 ; CHECK: .size mini_s_v8i16
1785 define void @mini_s_v4i32(<4 x i32>* %c, <4 x i32>* %a) nounwind {
1786 ; CHECK: mini_s_v4i32:
1788 %1 = load <4 x i32>* %a
1789 ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
1790 %2 = icmp slt <4 x i32> %1, <i32 1, i32 1, i32 1, i32 1>
1791 %3 = select <4 x i1> %2, <4 x i32> %1, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
1792 ; CHECK-DAG: mini_s.w [[R3:\$w[0-9]+]], [[R1]], 1
1793 store <4 x i32> %3, <4 x i32>* %c
1794 ; CHECK-DAG: st.w [[R3]], 0($4)
1797 ; CHECK: .size mini_s_v4i32
1800 define void @mini_s_v2i64(<2 x i64>* %c, <2 x i64>* %a) nounwind {
1801 ; CHECK: mini_s_v2i64:
1803 %1 = load <2 x i64>* %a
1804 ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
1805 %2 = icmp slt <2 x i64> %1, <i64 1, i64 1>
1806 %3 = select <2 x i1> %2, <2 x i64> %1, <2 x i64> <i64 1, i64 1>
1807 ; CHECK-DAG: mini_s.d [[R3:\$w[0-9]+]], [[R1]], 1
1808 store <2 x i64> %3, <2 x i64>* %c
1809 ; CHECK-DAG: st.d [[R3]], 0($4)
1812 ; CHECK: .size mini_s_v2i64
1815 define void @mini_u_v16i8(<16 x i8>* %c, <16 x i8>* %a) nounwind {
1816 ; CHECK: mini_u_v16i8:
1818 %1 = load <16 x i8>* %a
1819 ; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5)
1820 %2 = icmp ult <16 x i8> %1, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
1821 %3 = select <16 x i1> %2, <16 x i8> %1, <16 x i8> <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
1822 ; CHECK-DAG: mini_u.b [[R3:\$w[0-9]+]], [[R1]], 1
1823 store <16 x i8> %3, <16 x i8>* %c
1824 ; CHECK-DAG: st.b [[R3]], 0($4)
1827 ; CHECK: .size mini_u_v16i8
1830 define void @mini_u_v8i16(<8 x i16>* %c, <8 x i16>* %a) nounwind {
1831 ; CHECK: mini_u_v8i16:
1833 %1 = load <8 x i16>* %a
1834 ; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5)
1835 %2 = icmp ult <8 x i16> %1, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
1836 %3 = select <8 x i1> %2, <8 x i16> %1, <8 x i16> <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
1837 ; CHECK-DAG: mini_u.h [[R3:\$w[0-9]+]], [[R1]], 1
1838 store <8 x i16> %3, <8 x i16>* %c
1839 ; CHECK-DAG: st.h [[R3]], 0($4)
1842 ; CHECK: .size mini_u_v8i16
1845 define void @mini_u_v4i32(<4 x i32>* %c, <4 x i32>* %a) nounwind {
1846 ; CHECK: mini_u_v4i32:
1848 %1 = load <4 x i32>* %a
1849 ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
1850 %2 = icmp ult <4 x i32> %1, <i32 1, i32 1, i32 1, i32 1>
1851 %3 = select <4 x i1> %2, <4 x i32> %1, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
1852 ; CHECK-DAG: mini_u.w [[R3:\$w[0-9]+]], [[R1]], 1
1853 store <4 x i32> %3, <4 x i32>* %c
1854 ; CHECK-DAG: st.w [[R3]], 0($4)
1857 ; CHECK: .size mini_u_v4i32
1860 define void @mini_u_v2i64(<2 x i64>* %c, <2 x i64>* %a) nounwind {
1861 ; CHECK: mini_u_v2i64:
1863 %1 = load <2 x i64>* %a
1864 ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
1865 %2 = icmp ult <2 x i64> %1, <i64 1, i64 1>
1866 %3 = select <2 x i1> %2, <2 x i64> %1, <2 x i64> <i64 1, i64 1>
1867 ; CHECK-DAG: mini_u.d [[R3:\$w[0-9]+]], [[R1]], 1
1868 store <2 x i64> %3, <2 x i64>* %c
1869 ; CHECK-DAG: st.d [[R3]], 0($4)
1872 ; CHECK: .size mini_u_v2i64
1875 define void @mini_s_eq_v16i8(<16 x i8>* %c, <16 x i8>* %a) nounwind {
1876 ; CHECK: mini_s_eq_v16i8:
1878 %1 = load <16 x i8>* %a
1879 ; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5)
1880 %2 = icmp sle <16 x i8> %1, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
1881 %3 = select <16 x i1> %2, <16 x i8> %1, <16 x i8> <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
1882 ; CHECK-DAG: mini_s.b [[R3:\$w[0-9]+]], [[R1]], 1
1883 store <16 x i8> %3, <16 x i8>* %c
1884 ; CHECK-DAG: st.b [[R3]], 0($4)
1887 ; CHECK: .size mini_s_eq_v16i8
1890 define void @mini_s_eq_v8i16(<8 x i16>* %c, <8 x i16>* %a) nounwind {
1891 ; CHECK: mini_s_eq_v8i16:
1893 %1 = load <8 x i16>* %a
1894 ; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5)
1895 %2 = icmp sle <8 x i16> %1, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
1896 %3 = select <8 x i1> %2, <8 x i16> %1, <8 x i16> <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
1897 ; CHECK-DAG: mini_s.h [[R3:\$w[0-9]+]], [[R1]], 1
1898 store <8 x i16> %3, <8 x i16>* %c
1899 ; CHECK-DAG: st.h [[R3]], 0($4)
1902 ; CHECK: .size mini_s_eq_v8i16
1905 define void @mini_s_eq_v4i32(<4 x i32>* %c, <4 x i32>* %a) nounwind {
1906 ; CHECK: mini_s_eq_v4i32:
1908 %1 = load <4 x i32>* %a
1909 ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
1910 %2 = icmp sle <4 x i32> %1, <i32 1, i32 1, i32 1, i32 1>
1911 %3 = select <4 x i1> %2, <4 x i32> %1, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
1912 ; CHECK-DAG: mini_s.w [[R3:\$w[0-9]+]], [[R1]], 1
1913 store <4 x i32> %3, <4 x i32>* %c
1914 ; CHECK-DAG: st.w [[R3]], 0($4)
1917 ; CHECK: .size mini_s_eq_v4i32
1920 define void @mini_s_eq_v2i64(<2 x i64>* %c, <2 x i64>* %a) nounwind {
1921 ; CHECK: mini_s_eq_v2i64:
1923 %1 = load <2 x i64>* %a
1924 ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
1925 %2 = icmp sle <2 x i64> %1, <i64 1, i64 1>
1926 %3 = select <2 x i1> %2, <2 x i64> %1, <2 x i64> <i64 1, i64 1>
1927 ; CHECK-DAG: mini_s.d [[R3:\$w[0-9]+]], [[R1]], 1
1928 store <2 x i64> %3, <2 x i64>* %c
1929 ; CHECK-DAG: st.d [[R3]], 0($4)
1932 ; CHECK: .size mini_s_eq_v2i64
1935 define void @mini_u_eq_v16i8(<16 x i8>* %c, <16 x i8>* %a) nounwind {
1936 ; CHECK: mini_u_eq_v16i8:
1938 %1 = load <16 x i8>* %a
1939 ; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5)
1940 %2 = icmp ule <16 x i8> %1, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
1941 %3 = select <16 x i1> %2, <16 x i8> %1, <16 x i8> <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
1942 ; CHECK-DAG: mini_u.b [[R3:\$w[0-9]+]], [[R1]], 1
1943 store <16 x i8> %3, <16 x i8>* %c
1944 ; CHECK-DAG: st.b [[R3]], 0($4)
1947 ; CHECK: .size mini_u_eq_v16i8
1950 define void @mini_u_eq_v8i16(<8 x i16>* %c, <8 x i16>* %a) nounwind {
1951 ; CHECK: mini_u_eq_v8i16:
1953 %1 = load <8 x i16>* %a
1954 ; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5)
1955 %2 = icmp ule <8 x i16> %1, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
1956 %3 = select <8 x i1> %2, <8 x i16> %1, <8 x i16> <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
1957 ; CHECK-DAG: mini_u.h [[R3:\$w[0-9]+]], [[R1]], 1
1958 store <8 x i16> %3, <8 x i16>* %c
1959 ; CHECK-DAG: st.h [[R3]], 0($4)
1962 ; CHECK: .size mini_u_eq_v8i16
1965 define void @mini_u_eq_v4i32(<4 x i32>* %c, <4 x i32>* %a) nounwind {
1966 ; CHECK: mini_u_eq_v4i32:
1968 %1 = load <4 x i32>* %a
1969 ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
1970 %2 = icmp ule <4 x i32> %1, <i32 1, i32 1, i32 1, i32 1>
1971 %3 = select <4 x i1> %2, <4 x i32> %1, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
1972 ; CHECK-DAG: mini_u.w [[R3:\$w[0-9]+]], [[R1]], 1
1973 store <4 x i32> %3, <4 x i32>* %c
1974 ; CHECK-DAG: st.w [[R3]], 0($4)
1977 ; CHECK: .size mini_u_eq_v4i32
1980 define void @mini_u_eq_v2i64(<2 x i64>* %c, <2 x i64>* %a) nounwind {
1981 ; CHECK: mini_u_eq_v2i64:
1983 %1 = load <2 x i64>* %a
1984 ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
1985 %2 = icmp ule <2 x i64> %1, <i64 1, i64 1>
1986 %3 = select <2 x i1> %2, <2 x i64> %1, <2 x i64> <i64 1, i64 1>
1987 ; CHECK-DAG: mini_u.d [[R3:\$w[0-9]+]], [[R1]], 1
1988 store <2 x i64> %3, <2 x i64>* %c
1989 ; CHECK-DAG: st.d [[R3]], 0($4)
1992 ; CHECK: .size mini_u_eq_v2i64