1 ; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s
2 ; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | FileCheck %s
4 define void @ceq_v16i8(<16 x i8>* %c, <16 x i8>* %a, <16 x i8>* %b) nounwind {
7 %1 = load <16 x i8>* %a
8 ; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5)
9 %2 = load <16 x i8>* %b
10 ; CHECK-DAG: ld.b [[R2:\$w[0-9]+]], 0($6)
11 %3 = icmp eq <16 x i8> %1, %2
12 %4 = sext <16 x i1> %3 to <16 x i8>
13 ; CHECK-DAG: ceq.b [[R3:\$w[0-9]+]], [[R1]], [[R2]]
14 store <16 x i8> %4, <16 x i8>* %c
15 ; CHECK-DAG: st.b [[R3]], 0($4)
18 ; CHECK: .size ceq_v16i8
21 define void @ceq_v8i16(<8 x i16>* %c, <8 x i16>* %a, <8 x i16>* %b) nounwind {
24 %1 = load <8 x i16>* %a
25 ; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5)
26 %2 = load <8 x i16>* %b
27 ; CHECK-DAG: ld.h [[R2:\$w[0-9]+]], 0($6)
28 %3 = icmp eq <8 x i16> %1, %2
29 %4 = sext <8 x i1> %3 to <8 x i16>
30 ; CHECK-DAG: ceq.h [[R3:\$w[0-9]+]], [[R1]], [[R2]]
31 store <8 x i16> %4, <8 x i16>* %c
32 ; CHECK-DAG: st.h [[R3]], 0($4)
35 ; CHECK: .size ceq_v8i16
38 define void @ceq_v4i32(<4 x i32>* %c, <4 x i32>* %a, <4 x i32>* %b) nounwind {
41 %1 = load <4 x i32>* %a
42 ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
43 %2 = load <4 x i32>* %b
44 ; CHECK-DAG: ld.w [[R2:\$w[0-9]+]], 0($6)
45 %3 = icmp eq <4 x i32> %1, %2
46 %4 = sext <4 x i1> %3 to <4 x i32>
47 ; CHECK-DAG: ceq.w [[R3:\$w[0-9]+]], [[R1]], [[R2]]
48 store <4 x i32> %4, <4 x i32>* %c
49 ; CHECK-DAG: st.w [[R3]], 0($4)
52 ; CHECK: .size ceq_v4i32
55 define void @ceq_v2i64(<2 x i64>* %c, <2 x i64>* %a, <2 x i64>* %b) nounwind {
58 %1 = load <2 x i64>* %a
59 ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
60 %2 = load <2 x i64>* %b
61 ; CHECK-DAG: ld.d [[R2:\$w[0-9]+]], 0($6)
62 %3 = icmp eq <2 x i64> %1, %2
63 %4 = sext <2 x i1> %3 to <2 x i64>
64 ; CHECK-DAG: ceq.d [[R3:\$w[0-9]+]], [[R1]], [[R2]]
65 store <2 x i64> %4, <2 x i64>* %c
66 ; CHECK-DAG: st.d [[R3]], 0($4)
69 ; CHECK: .size ceq_v2i64
72 define void @cle_s_v16i8(<16 x i8>* %c, <16 x i8>* %a, <16 x i8>* %b) nounwind {
75 %1 = load <16 x i8>* %a
76 ; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5)
77 %2 = load <16 x i8>* %b
78 ; CHECK-DAG: ld.b [[R2:\$w[0-9]+]], 0($6)
79 %3 = icmp sle <16 x i8> %1, %2
80 %4 = sext <16 x i1> %3 to <16 x i8>
81 ; CHECK-DAG: cle_s.b [[R3:\$w[0-9]+]], [[R1]], [[R2]]
82 store <16 x i8> %4, <16 x i8>* %c
83 ; CHECK-DAG: st.b [[R3]], 0($4)
86 ; CHECK: .size cle_s_v16i8
89 define void @cle_s_v8i16(<8 x i16>* %c, <8 x i16>* %a, <8 x i16>* %b) nounwind {
92 %1 = load <8 x i16>* %a
93 ; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5)
94 %2 = load <8 x i16>* %b
95 ; CHECK-DAG: ld.h [[R2:\$w[0-9]+]], 0($6)
96 %3 = icmp sle <8 x i16> %1, %2
97 %4 = sext <8 x i1> %3 to <8 x i16>
98 ; CHECK-DAG: cle_s.h [[R3:\$w[0-9]+]], [[R1]], [[R2]]
99 store <8 x i16> %4, <8 x i16>* %c
100 ; CHECK-DAG: st.h [[R3]], 0($4)
103 ; CHECK: .size cle_s_v8i16
106 define void @cle_s_v4i32(<4 x i32>* %c, <4 x i32>* %a, <4 x i32>* %b) nounwind {
107 ; CHECK: cle_s_v4i32:
109 %1 = load <4 x i32>* %a
110 ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
111 %2 = load <4 x i32>* %b
112 ; CHECK-DAG: ld.w [[R2:\$w[0-9]+]], 0($6)
113 %3 = icmp sle <4 x i32> %1, %2
114 %4 = sext <4 x i1> %3 to <4 x i32>
115 ; CHECK-DAG: cle_s.w [[R3:\$w[0-9]+]], [[R1]], [[R2]]
116 store <4 x i32> %4, <4 x i32>* %c
117 ; CHECK-DAG: st.w [[R3]], 0($4)
120 ; CHECK: .size cle_s_v4i32
123 define void @cle_s_v2i64(<2 x i64>* %c, <2 x i64>* %a, <2 x i64>* %b) nounwind {
124 ; CHECK: cle_s_v2i64:
126 %1 = load <2 x i64>* %a
127 ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
128 %2 = load <2 x i64>* %b
129 ; CHECK-DAG: ld.d [[R2:\$w[0-9]+]], 0($6)
130 %3 = icmp sle <2 x i64> %1, %2
131 %4 = sext <2 x i1> %3 to <2 x i64>
132 ; CHECK-DAG: cle_s.d [[R3:\$w[0-9]+]], [[R1]], [[R2]]
133 store <2 x i64> %4, <2 x i64>* %c
134 ; CHECK-DAG: st.d [[R3]], 0($4)
137 ; CHECK: .size cle_s_v2i64
140 define void @cle_u_v16i8(<16 x i8>* %c, <16 x i8>* %a, <16 x i8>* %b) nounwind {
141 ; CHECK: cle_u_v16i8:
143 %1 = load <16 x i8>* %a
144 ; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5)
145 %2 = load <16 x i8>* %b
146 ; CHECK-DAG: ld.b [[R2:\$w[0-9]+]], 0($6)
147 %3 = icmp ule <16 x i8> %1, %2
148 %4 = sext <16 x i1> %3 to <16 x i8>
149 ; CHECK-DAG: cle_u.b [[R3:\$w[0-9]+]], [[R1]], [[R2]]
150 store <16 x i8> %4, <16 x i8>* %c
151 ; CHECK-DAG: st.b [[R3]], 0($4)
154 ; CHECK: .size cle_u_v16i8
157 define void @cle_u_v8i16(<8 x i16>* %c, <8 x i16>* %a, <8 x i16>* %b) nounwind {
158 ; CHECK: cle_u_v8i16:
160 %1 = load <8 x i16>* %a
161 ; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5)
162 %2 = load <8 x i16>* %b
163 ; CHECK-DAG: ld.h [[R2:\$w[0-9]+]], 0($6)
164 %3 = icmp ule <8 x i16> %1, %2
165 %4 = sext <8 x i1> %3 to <8 x i16>
166 ; CHECK-DAG: cle_u.h [[R3:\$w[0-9]+]], [[R1]], [[R2]]
167 store <8 x i16> %4, <8 x i16>* %c
168 ; CHECK-DAG: st.h [[R3]], 0($4)
171 ; CHECK: .size cle_u_v8i16
174 define void @cle_u_v4i32(<4 x i32>* %c, <4 x i32>* %a, <4 x i32>* %b) nounwind {
175 ; CHECK: cle_u_v4i32:
177 %1 = load <4 x i32>* %a
178 ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
179 %2 = load <4 x i32>* %b
180 ; CHECK-DAG: ld.w [[R2:\$w[0-9]+]], 0($6)
181 %3 = icmp ule <4 x i32> %1, %2
182 %4 = sext <4 x i1> %3 to <4 x i32>
183 ; CHECK-DAG: cle_u.w [[R3:\$w[0-9]+]], [[R1]], [[R2]]
184 store <4 x i32> %4, <4 x i32>* %c
185 ; CHECK-DAG: st.w [[R3]], 0($4)
188 ; CHECK: .size cle_u_v4i32
191 define void @cle_u_v2i64(<2 x i64>* %c, <2 x i64>* %a, <2 x i64>* %b) nounwind {
192 ; CHECK: cle_u_v2i64:
194 %1 = load <2 x i64>* %a
195 ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
196 %2 = load <2 x i64>* %b
197 ; CHECK-DAG: ld.d [[R2:\$w[0-9]+]], 0($6)
198 %3 = icmp ule <2 x i64> %1, %2
199 %4 = sext <2 x i1> %3 to <2 x i64>
200 ; CHECK-DAG: cle_u.d [[R3:\$w[0-9]+]], [[R1]], [[R2]]
201 store <2 x i64> %4, <2 x i64>* %c
202 ; CHECK-DAG: st.d [[R3]], 0($4)
205 ; CHECK: .size cle_u_v2i64
208 define void @clt_s_v16i8(<16 x i8>* %c, <16 x i8>* %a, <16 x i8>* %b) nounwind {
209 ; CHECK: clt_s_v16i8:
211 %1 = load <16 x i8>* %a
212 ; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5)
213 %2 = load <16 x i8>* %b
214 ; CHECK-DAG: ld.b [[R2:\$w[0-9]+]], 0($6)
215 %3 = icmp slt <16 x i8> %1, %2
216 %4 = sext <16 x i1> %3 to <16 x i8>
217 ; CHECK-DAG: clt_s.b [[R3:\$w[0-9]+]], [[R1]], [[R2]]
218 store <16 x i8> %4, <16 x i8>* %c
219 ; CHECK-DAG: st.b [[R3]], 0($4)
222 ; CHECK: .size clt_s_v16i8
225 define void @clt_s_v8i16(<8 x i16>* %c, <8 x i16>* %a, <8 x i16>* %b) nounwind {
226 ; CHECK: clt_s_v8i16:
228 %1 = load <8 x i16>* %a
229 ; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5)
230 %2 = load <8 x i16>* %b
231 ; CHECK-DAG: ld.h [[R2:\$w[0-9]+]], 0($6)
232 %3 = icmp slt <8 x i16> %1, %2
233 %4 = sext <8 x i1> %3 to <8 x i16>
234 ; CHECK-DAG: clt_s.h [[R3:\$w[0-9]+]], [[R1]], [[R2]]
235 store <8 x i16> %4, <8 x i16>* %c
236 ; CHECK-DAG: st.h [[R3]], 0($4)
239 ; CHECK: .size clt_s_v8i16
242 define void @clt_s_v4i32(<4 x i32>* %c, <4 x i32>* %a, <4 x i32>* %b) nounwind {
243 ; CHECK: clt_s_v4i32:
245 %1 = load <4 x i32>* %a
246 ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
247 %2 = load <4 x i32>* %b
248 ; CHECK-DAG: ld.w [[R2:\$w[0-9]+]], 0($6)
249 %3 = icmp slt <4 x i32> %1, %2
250 %4 = sext <4 x i1> %3 to <4 x i32>
251 ; CHECK-DAG: clt_s.w [[R3:\$w[0-9]+]], [[R1]], [[R2]]
252 store <4 x i32> %4, <4 x i32>* %c
253 ; CHECK-DAG: st.w [[R3]], 0($4)
256 ; CHECK: .size clt_s_v4i32
259 define void @clt_s_v2i64(<2 x i64>* %c, <2 x i64>* %a, <2 x i64>* %b) nounwind {
260 ; CHECK: clt_s_v2i64:
262 %1 = load <2 x i64>* %a
263 ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
264 %2 = load <2 x i64>* %b
265 ; CHECK-DAG: ld.d [[R2:\$w[0-9]+]], 0($6)
266 %3 = icmp slt <2 x i64> %1, %2
267 %4 = sext <2 x i1> %3 to <2 x i64>
268 ; CHECK-DAG: clt_s.d [[R3:\$w[0-9]+]], [[R1]], [[R2]]
269 store <2 x i64> %4, <2 x i64>* %c
270 ; CHECK-DAG: st.d [[R3]], 0($4)
273 ; CHECK: .size clt_s_v2i64
276 define void @clt_u_v16i8(<16 x i8>* %c, <16 x i8>* %a, <16 x i8>* %b) nounwind {
277 ; CHECK: clt_u_v16i8:
279 %1 = load <16 x i8>* %a
280 ; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5)
281 %2 = load <16 x i8>* %b
282 ; CHECK-DAG: ld.b [[R2:\$w[0-9]+]], 0($6)
283 %3 = icmp ult <16 x i8> %1, %2
284 %4 = sext <16 x i1> %3 to <16 x i8>
285 ; CHECK-DAG: clt_u.b [[R3:\$w[0-9]+]], [[R1]], [[R2]]
286 store <16 x i8> %4, <16 x i8>* %c
287 ; CHECK-DAG: st.b [[R3]], 0($4)
290 ; CHECK: .size clt_u_v16i8
293 define void @clt_u_v8i16(<8 x i16>* %c, <8 x i16>* %a, <8 x i16>* %b) nounwind {
294 ; CHECK: clt_u_v8i16:
296 %1 = load <8 x i16>* %a
297 ; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5)
298 %2 = load <8 x i16>* %b
299 ; CHECK-DAG: ld.h [[R2:\$w[0-9]+]], 0($6)
300 %3 = icmp ult <8 x i16> %1, %2
301 %4 = sext <8 x i1> %3 to <8 x i16>
302 ; CHECK-DAG: clt_u.h [[R3:\$w[0-9]+]], [[R1]], [[R2]]
303 store <8 x i16> %4, <8 x i16>* %c
304 ; CHECK-DAG: st.h [[R3]], 0($4)
307 ; CHECK: .size clt_u_v8i16
310 define void @clt_u_v4i32(<4 x i32>* %c, <4 x i32>* %a, <4 x i32>* %b) nounwind {
311 ; CHECK: clt_u_v4i32:
313 %1 = load <4 x i32>* %a
314 ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
315 %2 = load <4 x i32>* %b
316 ; CHECK-DAG: ld.w [[R2:\$w[0-9]+]], 0($6)
317 %3 = icmp ult <4 x i32> %1, %2
318 %4 = sext <4 x i1> %3 to <4 x i32>
319 ; CHECK-DAG: clt_u.w [[R3:\$w[0-9]+]], [[R1]], [[R2]]
320 store <4 x i32> %4, <4 x i32>* %c
321 ; CHECK-DAG: st.w [[R3]], 0($4)
324 ; CHECK: .size clt_u_v4i32
327 define void @clt_u_v2i64(<2 x i64>* %c, <2 x i64>* %a, <2 x i64>* %b) nounwind {
328 ; CHECK: clt_u_v2i64:
330 %1 = load <2 x i64>* %a
331 ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
332 %2 = load <2 x i64>* %b
333 ; CHECK-DAG: ld.d [[R2:\$w[0-9]+]], 0($6)
334 %3 = icmp ult <2 x i64> %1, %2
335 %4 = sext <2 x i1> %3 to <2 x i64>
336 ; CHECK-DAG: clt_u.d [[R3:\$w[0-9]+]], [[R1]], [[R2]]
337 store <2 x i64> %4, <2 x i64>* %c
338 ; CHECK-DAG: st.d [[R3]], 0($4)
341 ; CHECK: .size clt_u_v2i64
344 define void @ceqi_v16i8(<16 x i8>* %c, <16 x i8>* %a) nounwind {
347 %1 = load <16 x i8>* %a
348 ; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5)
349 %2 = icmp eq <16 x i8> %1, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
350 %3 = sext <16 x i1> %2 to <16 x i8>
351 ; CHECK-DAG: ceqi.b [[R3:\$w[0-9]+]], [[R1]], 1
352 store <16 x i8> %3, <16 x i8>* %c
353 ; CHECK-DAG: st.b [[R3]], 0($4)
356 ; CHECK: .size ceqi_v16i8
359 define void @ceqi_v8i16(<8 x i16>* %c, <8 x i16>* %a) nounwind {
362 %1 = load <8 x i16>* %a
363 ; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5)
364 %2 = icmp eq <8 x i16> %1, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
365 %3 = sext <8 x i1> %2 to <8 x i16>
366 ; CHECK-DAG: ceqi.h [[R3:\$w[0-9]+]], [[R1]], 1
367 store <8 x i16> %3, <8 x i16>* %c
368 ; CHECK-DAG: st.h [[R3]], 0($4)
371 ; CHECK: .size ceqi_v8i16
374 define void @ceqi_v4i32(<4 x i32>* %c, <4 x i32>* %a) nounwind {
377 %1 = load <4 x i32>* %a
378 ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
379 %2 = icmp eq <4 x i32> %1, <i32 1, i32 1, i32 1, i32 1>
380 %3 = sext <4 x i1> %2 to <4 x i32>
381 ; CHECK-DAG: ceqi.w [[R3:\$w[0-9]+]], [[R1]], 1
382 store <4 x i32> %3, <4 x i32>* %c
383 ; CHECK-DAG: st.w [[R3]], 0($4)
386 ; CHECK: .size ceqi_v4i32
389 define void @ceqi_v2i64(<2 x i64>* %c, <2 x i64>* %a) nounwind {
392 %1 = load <2 x i64>* %a
393 ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
394 %2 = icmp eq <2 x i64> %1, <i64 1, i64 1>
395 %3 = sext <2 x i1> %2 to <2 x i64>
396 ; CHECK-DAG: ceqi.d [[R3:\$w[0-9]+]], [[R1]], 1
397 store <2 x i64> %3, <2 x i64>* %c
398 ; CHECK-DAG: st.d [[R3]], 0($4)
401 ; CHECK: .size ceqi_v2i64
404 define void @clei_s_v16i8(<16 x i8>* %c, <16 x i8>* %a) nounwind {
405 ; CHECK: clei_s_v16i8:
407 %1 = load <16 x i8>* %a
408 ; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5)
409 %2 = icmp sle <16 x i8> %1, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
410 %3 = sext <16 x i1> %2 to <16 x i8>
411 ; CHECK-DAG: clei_s.b [[R3:\$w[0-9]+]], [[R1]], 1
412 store <16 x i8> %3, <16 x i8>* %c
413 ; CHECK-DAG: st.b [[R3]], 0($4)
416 ; CHECK: .size clei_s_v16i8
419 define void @clei_s_v8i16(<8 x i16>* %c, <8 x i16>* %a) nounwind {
420 ; CHECK: clei_s_v8i16:
422 %1 = load <8 x i16>* %a
423 ; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5)
424 %2 = icmp sle <8 x i16> %1, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
425 %3 = sext <8 x i1> %2 to <8 x i16>
426 ; CHECK-DAG: clei_s.h [[R3:\$w[0-9]+]], [[R1]], 1
427 store <8 x i16> %3, <8 x i16>* %c
428 ; CHECK-DAG: st.h [[R3]], 0($4)
431 ; CHECK: .size clei_s_v8i16
434 define void @clei_s_v4i32(<4 x i32>* %c, <4 x i32>* %a) nounwind {
435 ; CHECK: clei_s_v4i32:
437 %1 = load <4 x i32>* %a
438 ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
439 %2 = icmp sle <4 x i32> %1, <i32 1, i32 1, i32 1, i32 1>
440 %3 = sext <4 x i1> %2 to <4 x i32>
441 ; CHECK-DAG: clei_s.w [[R3:\$w[0-9]+]], [[R1]], 1
442 store <4 x i32> %3, <4 x i32>* %c
443 ; CHECK-DAG: st.w [[R3]], 0($4)
446 ; CHECK: .size clei_s_v4i32
449 define void @clei_s_v2i64(<2 x i64>* %c, <2 x i64>* %a) nounwind {
450 ; CHECK: clei_s_v2i64:
452 %1 = load <2 x i64>* %a
453 ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
454 %2 = icmp sle <2 x i64> %1, <i64 1, i64 1>
455 %3 = sext <2 x i1> %2 to <2 x i64>
456 ; CHECK-DAG: clei_s.d [[R3:\$w[0-9]+]], [[R1]], 1
457 store <2 x i64> %3, <2 x i64>* %c
458 ; CHECK-DAG: st.d [[R3]], 0($4)
461 ; CHECK: .size clei_s_v2i64
464 define void @clei_u_v16i8(<16 x i8>* %c, <16 x i8>* %a) nounwind {
465 ; CHECK: clei_u_v16i8:
467 %1 = load <16 x i8>* %a
468 ; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5)
469 %2 = icmp ule <16 x i8> %1, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
470 %3 = sext <16 x i1> %2 to <16 x i8>
471 ; CHECK-DAG: clei_u.b [[R3:\$w[0-9]+]], [[R1]], 1
472 store <16 x i8> %3, <16 x i8>* %c
473 ; CHECK-DAG: st.b [[R3]], 0($4)
476 ; CHECK: .size clei_u_v16i8
479 define void @clei_u_v8i16(<8 x i16>* %c, <8 x i16>* %a) nounwind {
480 ; CHECK: clei_u_v8i16:
482 %1 = load <8 x i16>* %a
483 ; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5)
484 %2 = icmp ule <8 x i16> %1, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
485 %3 = sext <8 x i1> %2 to <8 x i16>
486 ; CHECK-DAG: clei_u.h [[R3:\$w[0-9]+]], [[R1]], 1
487 store <8 x i16> %3, <8 x i16>* %c
488 ; CHECK-DAG: st.h [[R3]], 0($4)
491 ; CHECK: .size clei_u_v8i16
494 define void @clei_u_v4i32(<4 x i32>* %c, <4 x i32>* %a) nounwind {
495 ; CHECK: clei_u_v4i32:
497 %1 = load <4 x i32>* %a
498 ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
499 %2 = icmp ule <4 x i32> %1, <i32 1, i32 1, i32 1, i32 1>
500 %3 = sext <4 x i1> %2 to <4 x i32>
501 ; CHECK-DAG: clei_u.w [[R3:\$w[0-9]+]], [[R1]], 1
502 store <4 x i32> %3, <4 x i32>* %c
503 ; CHECK-DAG: st.w [[R3]], 0($4)
506 ; CHECK: .size clei_u_v4i32
509 define void @clei_u_v2i64(<2 x i64>* %c, <2 x i64>* %a) nounwind {
510 ; CHECK: clei_u_v2i64:
512 %1 = load <2 x i64>* %a
513 ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
514 %2 = icmp ule <2 x i64> %1, <i64 1, i64 1>
515 %3 = sext <2 x i1> %2 to <2 x i64>
516 ; CHECK-DAG: clei_u.d [[R3:\$w[0-9]+]], [[R1]], 1
517 store <2 x i64> %3, <2 x i64>* %c
518 ; CHECK-DAG: st.d [[R3]], 0($4)
521 ; CHECK: .size clei_u_v2i64
524 define void @clti_s_v16i8(<16 x i8>* %c, <16 x i8>* %a) nounwind {
525 ; CHECK: clti_s_v16i8:
527 %1 = load <16 x i8>* %a
528 ; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5)
529 %2 = icmp slt <16 x i8> %1, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
530 %3 = sext <16 x i1> %2 to <16 x i8>
531 ; CHECK-DAG: clti_s.b [[R3:\$w[0-9]+]], [[R1]], 1
532 store <16 x i8> %3, <16 x i8>* %c
533 ; CHECK-DAG: st.b [[R3]], 0($4)
536 ; CHECK: .size clti_s_v16i8
539 define void @clti_s_v8i16(<8 x i16>* %c, <8 x i16>* %a) nounwind {
540 ; CHECK: clti_s_v8i16:
542 %1 = load <8 x i16>* %a
543 ; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5)
544 %2 = icmp slt <8 x i16> %1, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
545 %3 = sext <8 x i1> %2 to <8 x i16>
546 ; CHECK-DAG: clti_s.h [[R3:\$w[0-9]+]], [[R1]], 1
547 store <8 x i16> %3, <8 x i16>* %c
548 ; CHECK-DAG: st.h [[R3]], 0($4)
551 ; CHECK: .size clti_s_v8i16
554 define void @clti_s_v4i32(<4 x i32>* %c, <4 x i32>* %a) nounwind {
555 ; CHECK: clti_s_v4i32:
557 %1 = load <4 x i32>* %a
558 ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
559 %2 = icmp slt <4 x i32> %1, <i32 1, i32 1, i32 1, i32 1>
560 %3 = sext <4 x i1> %2 to <4 x i32>
561 ; CHECK-DAG: clti_s.w [[R3:\$w[0-9]+]], [[R1]], 1
562 store <4 x i32> %3, <4 x i32>* %c
563 ; CHECK-DAG: st.w [[R3]], 0($4)
566 ; CHECK: .size clti_s_v4i32
569 define void @clti_s_v2i64(<2 x i64>* %c, <2 x i64>* %a) nounwind {
570 ; CHECK: clti_s_v2i64:
572 %1 = load <2 x i64>* %a
573 ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
574 %2 = icmp slt <2 x i64> %1, <i64 1, i64 1>
575 %3 = sext <2 x i1> %2 to <2 x i64>
576 ; CHECK-DAG: clti_s.d [[R3:\$w[0-9]+]], [[R1]], 1
577 store <2 x i64> %3, <2 x i64>* %c
578 ; CHECK-DAG: st.d [[R3]], 0($4)
581 ; CHECK: .size clti_s_v2i64
584 define void @clti_u_v16i8(<16 x i8>* %c, <16 x i8>* %a) nounwind {
585 ; CHECK: clti_u_v16i8:
587 %1 = load <16 x i8>* %a
588 ; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5)
589 %2 = icmp ult <16 x i8> %1, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
590 %3 = sext <16 x i1> %2 to <16 x i8>
591 ; CHECK-DAG: clti_u.b [[R3:\$w[0-9]+]], [[R1]], 1
592 store <16 x i8> %3, <16 x i8>* %c
593 ; CHECK-DAG: st.b [[R3]], 0($4)
596 ; CHECK: .size clti_u_v16i8
599 define void @clti_u_v8i16(<8 x i16>* %c, <8 x i16>* %a) nounwind {
600 ; CHECK: clti_u_v8i16:
602 %1 = load <8 x i16>* %a
603 ; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5)
604 %2 = icmp ult <8 x i16> %1, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
605 %3 = sext <8 x i1> %2 to <8 x i16>
606 ; CHECK-DAG: clti_u.h [[R3:\$w[0-9]+]], [[R1]], 1
607 store <8 x i16> %3, <8 x i16>* %c
608 ; CHECK-DAG: st.h [[R3]], 0($4)
611 ; CHECK: .size clti_u_v8i16
614 define void @clti_u_v4i32(<4 x i32>* %c, <4 x i32>* %a) nounwind {
615 ; CHECK: clti_u_v4i32:
617 %1 = load <4 x i32>* %a
618 ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
619 %2 = icmp ult <4 x i32> %1, <i32 1, i32 1, i32 1, i32 1>
620 %3 = sext <4 x i1> %2 to <4 x i32>
621 ; CHECK-DAG: clti_u.w [[R3:\$w[0-9]+]], [[R1]], 1
622 store <4 x i32> %3, <4 x i32>* %c
623 ; CHECK-DAG: st.w [[R3]], 0($4)
626 ; CHECK: .size clti_u_v4i32
629 define void @clti_u_v2i64(<2 x i64>* %c, <2 x i64>* %a) nounwind {
630 ; CHECK: clti_u_v2i64:
632 %1 = load <2 x i64>* %a
633 ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
634 %2 = icmp ult <2 x i64> %1, <i64 1, i64 1>
635 %3 = sext <2 x i1> %2 to <2 x i64>
636 ; CHECK-DAG: clti_u.d [[R3:\$w[0-9]+]], [[R1]], 1
637 store <2 x i64> %3, <2 x i64>* %c
638 ; CHECK-DAG: st.d [[R3]], 0($4)
641 ; CHECK: .size clti_u_v2i64
644 define void @bsel_s_v16i8(<16 x i8>* %d, <16 x i8>* %a, <16 x i8>* %b,
645 <16 x i8>* %c) nounwind {
646 ; CHECK: bsel_s_v16i8:
648 %1 = load <16 x i8>* %a
649 ; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5)
650 %2 = load <16 x i8>* %b
651 ; CHECK-DAG: ld.b [[R2:\$w[0-9]+]], 0($6)
652 %3 = load <16 x i8>* %c
653 ; CHECK-DAG: ld.b [[R3:\$w[0-9]+]], 0($7)
654 %4 = icmp sgt <16 x i8> %1, %2
655 ; CHECK-DAG: clt_s.b [[R4:\$w[0-9]+]], [[R2]], [[R1]]
656 %5 = select <16 x i1> %4, <16 x i8> %1, <16 x i8> %3
657 ; bmnz.v is the same operation
658 ; CHECK-DAG: bmnz.v [[R3]], [[R1]], [[R4]]
659 store <16 x i8> %5, <16 x i8>* %d
660 ; CHECK-DAG: st.b [[R3]], 0($4)
663 ; CHECK: .size bsel_s_v16i8
666 define void @bsel_s_v8i16(<8 x i16>* %d, <8 x i16>* %a, <8 x i16>* %b,
667 <8 x i16>* %c) nounwind {
668 ; CHECK: bsel_s_v8i16:
670 %1 = load <8 x i16>* %a
671 ; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5)
672 %2 = load <8 x i16>* %b
673 ; CHECK-DAG: ld.h [[R2:\$w[0-9]+]], 0($6)
674 %3 = load <8 x i16>* %c
675 ; CHECK-DAG: ld.h [[R3:\$w[0-9]+]], 0($7)
676 %4 = icmp sgt <8 x i16> %1, %2
677 ; CHECK-DAG: clt_s.h [[R4:\$w[0-9]+]], [[R2]], [[R1]]
678 %5 = select <8 x i1> %4, <8 x i16> %1, <8 x i16> %3
679 ; CHECK-DAG: bsel.v [[R4]], [[R1]], [[R3]]
680 store <8 x i16> %5, <8 x i16>* %d
681 ; CHECK-DAG: st.h [[R4]], 0($4)
684 ; CHECK: .size bsel_s_v8i16
687 define void @bsel_s_v4i32(<4 x i32>* %d, <4 x i32>* %a, <4 x i32>* %b,
688 <4 x i32>* %c) nounwind {
689 ; CHECK: bsel_s_v4i32:
691 %1 = load <4 x i32>* %a
692 ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
693 %2 = load <4 x i32>* %b
694 ; CHECK-DAG: ld.w [[R2:\$w[0-9]+]], 0($6)
695 %3 = load <4 x i32>* %c
696 ; CHECK-DAG: ld.w [[R3:\$w[0-9]+]], 0($7)
697 %4 = icmp sgt <4 x i32> %1, %2
698 ; CHECK-DAG: clt_s.w [[R4:\$w[0-9]+]], [[R2]], [[R1]]
699 %5 = select <4 x i1> %4, <4 x i32> %1, <4 x i32> %3
700 ; CHECK-DAG: bsel.v [[R4]], [[R1]], [[R3]]
701 store <4 x i32> %5, <4 x i32>* %d
702 ; CHECK-DAG: st.w [[R4]], 0($4)
705 ; CHECK: .size bsel_s_v4i32
708 define void @bsel_s_v2i64(<2 x i64>* %d, <2 x i64>* %a, <2 x i64>* %b,
709 <2 x i64>* %c) nounwind {
710 ; CHECK: bsel_s_v2i64:
712 %1 = load <2 x i64>* %a
713 ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
714 %2 = load <2 x i64>* %b
715 ; CHECK-DAG: ld.d [[R2:\$w[0-9]+]], 0($6)
716 %3 = load <2 x i64>* %c
717 ; CHECK-DAG: ld.d [[R3:\$w[0-9]+]], 0($7)
718 %4 = icmp sgt <2 x i64> %1, %2
719 ; CHECK-DAG: clt_s.d [[R4:\$w[0-9]+]], [[R2]], [[R1]]
720 %5 = select <2 x i1> %4, <2 x i64> %1, <2 x i64> %3
721 ; CHECK-DAG: bsel.v [[R4]], [[R1]], [[R3]]
722 store <2 x i64> %5, <2 x i64>* %d
723 ; CHECK-DAG: st.d [[R4]], 0($4)
726 ; CHECK: .size bsel_s_v2i64
729 define void @bsel_u_v16i8(<16 x i8>* %d, <16 x i8>* %a, <16 x i8>* %b,
730 <16 x i8>* %c) nounwind {
731 ; CHECK: bsel_u_v16i8:
733 %1 = load <16 x i8>* %a
734 ; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5)
735 %2 = load <16 x i8>* %b
736 ; CHECK-DAG: ld.b [[R2:\$w[0-9]+]], 0($6)
737 %3 = load <16 x i8>* %c
738 ; CHECK-DAG: ld.b [[R3:\$w[0-9]+]], 0($7)
739 %4 = icmp ugt <16 x i8> %1, %2
740 ; CHECK-DAG: clt_u.b [[R4:\$w[0-9]+]], [[R2]], [[R1]]
741 %5 = select <16 x i1> %4, <16 x i8> %1, <16 x i8> %3
742 ; bmnz.v is the same operation
743 ; CHECK-DAG: bmnz.v [[R3]], [[R1]], [[R4]]
744 store <16 x i8> %5, <16 x i8>* %d
745 ; CHECK-DAG: st.b [[R3]], 0($4)
748 ; CHECK: .size bsel_u_v16i8
751 define void @bsel_u_v8i16(<8 x i16>* %d, <8 x i16>* %a, <8 x i16>* %b,
752 <8 x i16>* %c) nounwind {
753 ; CHECK: bsel_u_v8i16:
755 %1 = load <8 x i16>* %a
756 ; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5)
757 %2 = load <8 x i16>* %b
758 ; CHECK-DAG: ld.h [[R2:\$w[0-9]+]], 0($6)
759 %3 = load <8 x i16>* %c
760 ; CHECK-DAG: ld.h [[R3:\$w[0-9]+]], 0($7)
761 %4 = icmp ugt <8 x i16> %1, %2
762 ; CHECK-DAG: clt_u.h [[R4:\$w[0-9]+]], [[R2]], [[R1]]
763 %5 = select <8 x i1> %4, <8 x i16> %1, <8 x i16> %3
764 ; CHECK-DAG: bsel.v [[R4]], [[R1]], [[R3]]
765 store <8 x i16> %5, <8 x i16>* %d
766 ; CHECK-DAG: st.h [[R4]], 0($4)
769 ; CHECK: .size bsel_u_v8i16
772 define void @bsel_u_v4i32(<4 x i32>* %d, <4 x i32>* %a, <4 x i32>* %b,
773 <4 x i32>* %c) nounwind {
774 ; CHECK: bsel_u_v4i32:
776 %1 = load <4 x i32>* %a
777 ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
778 %2 = load <4 x i32>* %b
779 ; CHECK-DAG: ld.w [[R2:\$w[0-9]+]], 0($6)
780 %3 = load <4 x i32>* %c
781 ; CHECK-DAG: ld.w [[R3:\$w[0-9]+]], 0($7)
782 %4 = icmp ugt <4 x i32> %1, %2
783 ; CHECK-DAG: clt_u.w [[R4:\$w[0-9]+]], [[R2]], [[R1]]
784 %5 = select <4 x i1> %4, <4 x i32> %1, <4 x i32> %3
785 ; CHECK-DAG: bsel.v [[R4]], [[R1]], [[R3]]
786 store <4 x i32> %5, <4 x i32>* %d
787 ; CHECK-DAG: st.w [[R4]], 0($4)
790 ; CHECK: .size bsel_u_v4i32
793 define void @bsel_u_v2i64(<2 x i64>* %d, <2 x i64>* %a, <2 x i64>* %b,
794 <2 x i64>* %c) nounwind {
795 ; CHECK: bsel_u_v2i64:
797 %1 = load <2 x i64>* %a
798 ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
799 %2 = load <2 x i64>* %b
800 ; CHECK-DAG: ld.d [[R2:\$w[0-9]+]], 0($6)
801 %3 = load <2 x i64>* %c
802 ; CHECK-DAG: ld.d [[R3:\$w[0-9]+]], 0($7)
803 %4 = icmp ugt <2 x i64> %1, %2
804 ; CHECK-DAG: clt_u.d [[R4:\$w[0-9]+]], [[R2]], [[R1]]
805 %5 = select <2 x i1> %4, <2 x i64> %1, <2 x i64> %3
806 ; CHECK-DAG: bsel.v [[R4]], [[R1]], [[R3]]
807 store <2 x i64> %5, <2 x i64>* %d
808 ; CHECK-DAG: st.d [[R4]], 0($4)
811 ; CHECK: .size bsel_u_v2i64
814 define void @bseli_s_v16i8(<16 x i8>* %d, <16 x i8>* %a, <16 x i8>* %b,
815 <16 x i8>* %c) nounwind {
816 ; CHECK: bseli_s_v16i8:
818 %1 = load <16 x i8>* %a
819 ; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5)
820 %2 = load <16 x i8>* %b
821 ; CHECK-DAG: ld.b [[R2:\$w[0-9]+]], 0($6)
822 %3 = icmp sgt <16 x i8> %1, %2
823 ; CHECK-DAG: clt_s.b [[R4:\$w[0-9]+]], [[R2]], [[R1]]
824 %4 = select <16 x i1> %3, <16 x i8> %1, <16 x i8> <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
825 ; CHECK-DAG: bseli.b [[R4]], [[R1]], 1
826 store <16 x i8> %4, <16 x i8>* %d
827 ; CHECK-DAG: st.b [[R4]], 0($4)
830 ; CHECK: .size bseli_s_v16i8
833 define void @bseli_s_v8i16(<8 x i16>* %d, <8 x i16>* %a, <8 x i16>* %b,
834 <8 x i16>* %c) nounwind {
835 ; CHECK: bseli_s_v8i16:
837 %1 = load <8 x i16>* %a
838 ; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5)
839 %2 = load <8 x i16>* %b
840 ; CHECK-DAG: ld.h [[R2:\$w[0-9]+]], 0($6)
841 %3 = icmp sgt <8 x i16> %1, %2
842 ; CHECK-DAG: clt_s.h [[R4:\$w[0-9]+]], [[R2]], [[R1]]
843 %4 = select <8 x i1> %3, <8 x i16> %1, <8 x i16> <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
844 ; CHECK-DAG: ldi.h [[R3:\$w[0-9]+]], 1
845 ; CHECK-DAG: bsel.v [[R4]], [[R1]], [[R3]]
846 store <8 x i16> %4, <8 x i16>* %d
847 ; CHECK-DAG: st.h [[R4]], 0($4)
850 ; CHECK: .size bseli_s_v8i16
853 define void @bseli_s_v4i32(<4 x i32>* %d, <4 x i32>* %a, <4 x i32>* %b,
854 <4 x i32>* %c) nounwind {
855 ; CHECK: bseli_s_v4i32:
857 %1 = load <4 x i32>* %a
858 ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
859 %2 = load <4 x i32>* %b
860 ; CHECK-DAG: ld.w [[R2:\$w[0-9]+]], 0($6)
861 %3 = icmp sgt <4 x i32> %1, %2
862 ; CHECK-DAG: clt_s.w [[R4:\$w[0-9]+]], [[R2]], [[R1]]
863 %4 = select <4 x i1> %3, <4 x i32> %1, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
864 ; CHECK-DAG: ldi.w [[R3:\$w[0-9]+]], 1
865 ; CHECK-DAG: bsel.v [[R4]], [[R1]], [[R3]]
866 store <4 x i32> %4, <4 x i32>* %d
867 ; CHECK-DAG: st.w [[R4]], 0($4)
870 ; CHECK: .size bseli_s_v4i32
873 define void @bseli_s_v2i64(<2 x i64>* %d, <2 x i64>* %a, <2 x i64>* %b,
874 <2 x i64>* %c) nounwind {
875 ; CHECK: bseli_s_v2i64:
877 %1 = load <2 x i64>* %a
878 ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
879 %2 = load <2 x i64>* %b
880 ; CHECK-DAG: ld.d [[R2:\$w[0-9]+]], 0($6)
881 %3 = icmp sgt <2 x i64> %1, %2
882 ; CHECK-DAG: clt_s.d [[R4:\$w[0-9]+]], [[R2]], [[R1]]
883 %4 = select <2 x i1> %3, <2 x i64> %1, <2 x i64> <i64 1, i64 1>
884 ; CHECK-DAG: ldi.d [[R3:\$w[0-9]+]], 1
885 ; CHECK-DAG: bsel.v [[R4]], [[R1]], [[R3]]
886 store <2 x i64> %4, <2 x i64>* %d
887 ; CHECK-DAG: st.d [[R4]], 0($4)
890 ; CHECK: .size bseli_s_v2i64
893 define void @bseli_u_v16i8(<16 x i8>* %d, <16 x i8>* %a, <16 x i8>* %b,
894 <16 x i8>* %c) nounwind {
895 ; CHECK: bseli_u_v16i8:
897 %1 = load <16 x i8>* %a
898 ; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5)
899 %2 = load <16 x i8>* %b
900 ; CHECK-DAG: ld.b [[R2:\$w[0-9]+]], 0($6)
901 %3 = icmp ugt <16 x i8> %1, %2
902 ; CHECK-DAG: clt_u.b [[R4:\$w[0-9]+]], [[R2]], [[R1]]
903 %4 = select <16 x i1> %3, <16 x i8> %1, <16 x i8> <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
904 ; CHECK-DAG: bseli.b [[R4]], [[R1]], 1
905 store <16 x i8> %4, <16 x i8>* %d
906 ; CHECK-DAG: st.b [[R4]], 0($4)
909 ; CHECK: .size bseli_u_v16i8
912 define void @bseli_u_v8i16(<8 x i16>* %d, <8 x i16>* %a, <8 x i16>* %b,
913 <8 x i16>* %c) nounwind {
914 ; CHECK: bseli_u_v8i16:
916 %1 = load <8 x i16>* %a
917 ; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5)
918 %2 = load <8 x i16>* %b
919 ; CHECK-DAG: ld.h [[R2:\$w[0-9]+]], 0($6)
920 %3 = icmp ugt <8 x i16> %1, %2
921 ; CHECK-DAG: clt_u.h [[R4:\$w[0-9]+]], [[R2]], [[R1]]
922 %4 = select <8 x i1> %3, <8 x i16> %1, <8 x i16> <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
923 ; CHECK-DAG: ldi.h [[R3:\$w[0-9]+]], 1
924 ; CHECK-DAG: bsel.v [[R4]], [[R1]], [[R3]]
925 store <8 x i16> %4, <8 x i16>* %d
926 ; CHECK-DAG: st.h [[R4]], 0($4)
929 ; CHECK: .size bseli_u_v8i16
932 define void @bseli_u_v4i32(<4 x i32>* %d, <4 x i32>* %a, <4 x i32>* %b,
933 <4 x i32>* %c) nounwind {
934 ; CHECK: bseli_u_v4i32:
936 %1 = load <4 x i32>* %a
937 ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
938 %2 = load <4 x i32>* %b
939 ; CHECK-DAG: ld.w [[R2:\$w[0-9]+]], 0($6)
940 %3 = icmp ugt <4 x i32> %1, %2
941 ; CHECK-DAG: clt_u.w [[R4:\$w[0-9]+]], [[R2]], [[R1]]
942 %4 = select <4 x i1> %3, <4 x i32> %1, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
943 ; CHECK-DAG: ldi.w [[R3:\$w[0-9]+]], 1
944 ; CHECK-DAG: bsel.v [[R4]], [[R1]], [[R3]]
945 store <4 x i32> %4, <4 x i32>* %d
946 ; CHECK-DAG: st.w [[R4]], 0($4)
949 ; CHECK: .size bseli_u_v4i32
952 define void @bseli_u_v2i64(<2 x i64>* %d, <2 x i64>* %a, <2 x i64>* %b,
953 <2 x i64>* %c) nounwind {
954 ; CHECK: bseli_u_v2i64:
956 %1 = load <2 x i64>* %a
957 ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
958 %2 = load <2 x i64>* %b
959 ; CHECK-DAG: ld.d [[R2:\$w[0-9]+]], 0($6)
960 %3 = icmp ugt <2 x i64> %1, %2
961 ; CHECK-DAG: clt_u.d [[R4:\$w[0-9]+]], [[R2]], [[R1]]
962 %4 = select <2 x i1> %3, <2 x i64> %1, <2 x i64> <i64 1, i64 1>
963 ; CHECK-DAG: ldi.d [[R3:\$w[0-9]+]], 1
964 ; CHECK-DAG: bsel.v [[R4]], [[R1]], [[R3]]
965 store <2 x i64> %4, <2 x i64>* %d
966 ; CHECK-DAG: st.d [[R4]], 0($4)
969 ; CHECK: .size bseli_u_v2i64
972 define void @max_s_v16i8(<16 x i8>* %c, <16 x i8>* %a, <16 x i8>* %b) nounwind {
973 ; CHECK: max_s_v16i8:
975 %1 = load <16 x i8>* %a
976 ; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5)
977 %2 = load <16 x i8>* %b
978 ; CHECK-DAG: ld.b [[R2:\$w[0-9]+]], 0($6)
979 %3 = icmp sgt <16 x i8> %1, %2
980 %4 = select <16 x i1> %3, <16 x i8> %1, <16 x i8> %2
981 ; CHECK-DAG: max_s.b [[R3:\$w[0-9]+]], [[R1]], [[R2]]
982 store <16 x i8> %4, <16 x i8>* %c
983 ; CHECK-DAG: st.b [[R3]], 0($4)
986 ; CHECK: .size max_s_v16i8
989 define void @max_s_v8i16(<8 x i16>* %c, <8 x i16>* %a, <8 x i16>* %b) nounwind {
990 ; CHECK: max_s_v8i16:
992 %1 = load <8 x i16>* %a
993 ; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5)
994 %2 = load <8 x i16>* %b
995 ; CHECK-DAG: ld.h [[R2:\$w[0-9]+]], 0($6)
996 %3 = icmp sgt <8 x i16> %1, %2
997 %4 = select <8 x i1> %3, <8 x i16> %1, <8 x i16> %2
998 ; CHECK-DAG: max_s.h [[R3:\$w[0-9]+]], [[R1]], [[R2]]
999 store <8 x i16> %4, <8 x i16>* %c
1000 ; CHECK-DAG: st.h [[R3]], 0($4)
1003 ; CHECK: .size max_s_v8i16
1006 define void @max_s_v4i32(<4 x i32>* %c, <4 x i32>* %a, <4 x i32>* %b) nounwind {
1007 ; CHECK: max_s_v4i32:
1009 %1 = load <4 x i32>* %a
1010 ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
1011 %2 = load <4 x i32>* %b
1012 ; CHECK-DAG: ld.w [[R2:\$w[0-9]+]], 0($6)
1013 %3 = icmp sgt <4 x i32> %1, %2
1014 %4 = select <4 x i1> %3, <4 x i32> %1, <4 x i32> %2
1015 ; CHECK-DAG: max_s.w [[R3:\$w[0-9]+]], [[R1]], [[R2]]
1016 store <4 x i32> %4, <4 x i32>* %c
1017 ; CHECK-DAG: st.w [[R3]], 0($4)
1020 ; CHECK: .size max_s_v4i32
1023 define void @max_s_v2i64(<2 x i64>* %c, <2 x i64>* %a, <2 x i64>* %b) nounwind {
1024 ; CHECK: max_s_v2i64:
1026 %1 = load <2 x i64>* %a
1027 ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
1028 %2 = load <2 x i64>* %b
1029 ; CHECK-DAG: ld.d [[R2:\$w[0-9]+]], 0($6)
1030 %3 = icmp sgt <2 x i64> %1, %2
1031 %4 = select <2 x i1> %3, <2 x i64> %1, <2 x i64> %2
1032 ; CHECK-DAG: max_s.d [[R3:\$w[0-9]+]], [[R1]], [[R2]]
1033 store <2 x i64> %4, <2 x i64>* %c
1034 ; CHECK-DAG: st.d [[R3]], 0($4)
1037 ; CHECK: .size max_s_v2i64
1040 define void @max_u_v16i8(<16 x i8>* %c, <16 x i8>* %a, <16 x i8>* %b) nounwind {
1041 ; CHECK: max_u_v16i8:
1043 %1 = load <16 x i8>* %a
1044 ; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5)
1045 %2 = load <16 x i8>* %b
1046 ; CHECK-DAG: ld.b [[R2:\$w[0-9]+]], 0($6)
1047 %3 = icmp ugt <16 x i8> %1, %2
1048 %4 = select <16 x i1> %3, <16 x i8> %1, <16 x i8> %2
1049 ; CHECK-DAG: max_u.b [[R3:\$w[0-9]+]], [[R1]], [[R2]]
1050 store <16 x i8> %4, <16 x i8>* %c
1051 ; CHECK-DAG: st.b [[R3]], 0($4)
1054 ; CHECK: .size max_u_v16i8
1057 define void @max_u_v8i16(<8 x i16>* %c, <8 x i16>* %a, <8 x i16>* %b) nounwind {
1058 ; CHECK: max_u_v8i16:
1060 %1 = load <8 x i16>* %a
1061 ; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5)
1062 %2 = load <8 x i16>* %b
1063 ; CHECK-DAG: ld.h [[R2:\$w[0-9]+]], 0($6)
1064 %3 = icmp ugt <8 x i16> %1, %2
1065 %4 = select <8 x i1> %3, <8 x i16> %1, <8 x i16> %2
1066 ; CHECK-DAG: max_u.h [[R3:\$w[0-9]+]], [[R1]], [[R2]]
1067 store <8 x i16> %4, <8 x i16>* %c
1068 ; CHECK-DAG: st.h [[R3]], 0($4)
1071 ; CHECK: .size max_u_v8i16
1074 define void @max_u_v4i32(<4 x i32>* %c, <4 x i32>* %a, <4 x i32>* %b) nounwind {
1075 ; CHECK: max_u_v4i32:
1077 %1 = load <4 x i32>* %a
1078 ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
1079 %2 = load <4 x i32>* %b
1080 ; CHECK-DAG: ld.w [[R2:\$w[0-9]+]], 0($6)
1081 %3 = icmp ugt <4 x i32> %1, %2
1082 %4 = select <4 x i1> %3, <4 x i32> %1, <4 x i32> %2
1083 ; CHECK-DAG: max_u.w [[R3:\$w[0-9]+]], [[R1]], [[R2]]
1084 store <4 x i32> %4, <4 x i32>* %c
1085 ; CHECK-DAG: st.w [[R3]], 0($4)
1088 ; CHECK: .size max_u_v4i32
1091 define void @max_u_v2i64(<2 x i64>* %c, <2 x i64>* %a, <2 x i64>* %b) nounwind {
1092 ; CHECK: max_u_v2i64:
1094 %1 = load <2 x i64>* %a
1095 ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
1096 %2 = load <2 x i64>* %b
1097 ; CHECK-DAG: ld.d [[R2:\$w[0-9]+]], 0($6)
1098 %3 = icmp ugt <2 x i64> %1, %2
1099 %4 = select <2 x i1> %3, <2 x i64> %1, <2 x i64> %2
1100 ; CHECK-DAG: max_u.d [[R3:\$w[0-9]+]], [[R1]], [[R2]]
1101 store <2 x i64> %4, <2 x i64>* %c
1102 ; CHECK-DAG: st.d [[R3]], 0($4)
1105 ; CHECK: .size max_u_v2i64
1108 define void @max_s_eq_v16i8(<16 x i8>* %c, <16 x i8>* %a, <16 x i8>* %b) nounwind {
1109 ; CHECK: max_s_eq_v16i8:
1111 %1 = load <16 x i8>* %a
1112 ; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5)
1113 %2 = load <16 x i8>* %b
1114 ; CHECK-DAG: ld.b [[R2:\$w[0-9]+]], 0($6)
1115 %3 = icmp sge <16 x i8> %1, %2
1116 %4 = select <16 x i1> %3, <16 x i8> %1, <16 x i8> %2
1117 ; CHECK-DAG: max_s.b [[R3:\$w[0-9]+]], [[R1]], [[R2]]
1118 store <16 x i8> %4, <16 x i8>* %c
1119 ; CHECK-DAG: st.b [[R3]], 0($4)
1122 ; CHECK: .size max_s_eq_v16i8
1125 define void @max_s_eq_v8i16(<8 x i16>* %c, <8 x i16>* %a, <8 x i16>* %b) nounwind {
1126 ; CHECK: max_s_eq_v8i16:
1128 %1 = load <8 x i16>* %a
1129 ; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5)
1130 %2 = load <8 x i16>* %b
1131 ; CHECK-DAG: ld.h [[R2:\$w[0-9]+]], 0($6)
1132 %3 = icmp sge <8 x i16> %1, %2
1133 %4 = select <8 x i1> %3, <8 x i16> %1, <8 x i16> %2
1134 ; CHECK-DAG: max_s.h [[R3:\$w[0-9]+]], [[R1]], [[R2]]
1135 store <8 x i16> %4, <8 x i16>* %c
1136 ; CHECK-DAG: st.h [[R3]], 0($4)
1139 ; CHECK: .size max_s_eq_v8i16
1142 define void @max_s_eq_v4i32(<4 x i32>* %c, <4 x i32>* %a, <4 x i32>* %b) nounwind {
1143 ; CHECK: max_s_eq_v4i32:
1145 %1 = load <4 x i32>* %a
1146 ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
1147 %2 = load <4 x i32>* %b
1148 ; CHECK-DAG: ld.w [[R2:\$w[0-9]+]], 0($6)
1149 %3 = icmp sge <4 x i32> %1, %2
1150 %4 = select <4 x i1> %3, <4 x i32> %1, <4 x i32> %2
1151 ; CHECK-DAG: max_s.w [[R3:\$w[0-9]+]], [[R1]], [[R2]]
1152 store <4 x i32> %4, <4 x i32>* %c
1153 ; CHECK-DAG: st.w [[R3]], 0($4)
1156 ; CHECK: .size max_s_eq_v4i32
1159 define void @max_s_eq_v2i64(<2 x i64>* %c, <2 x i64>* %a, <2 x i64>* %b) nounwind {
1160 ; CHECK: max_s_eq_v2i64:
1162 %1 = load <2 x i64>* %a
1163 ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
1164 %2 = load <2 x i64>* %b
1165 ; CHECK-DAG: ld.d [[R2:\$w[0-9]+]], 0($6)
1166 %3 = icmp sge <2 x i64> %1, %2
1167 %4 = select <2 x i1> %3, <2 x i64> %1, <2 x i64> %2
1168 ; CHECK-DAG: max_s.d [[R3:\$w[0-9]+]], [[R1]], [[R2]]
1169 store <2 x i64> %4, <2 x i64>* %c
1170 ; CHECK-DAG: st.d [[R3]], 0($4)
1173 ; CHECK: .size max_s_eq_v2i64
1176 define void @max_u_eq_v16i8(<16 x i8>* %c, <16 x i8>* %a, <16 x i8>* %b) nounwind {
1177 ; CHECK: max_u_eq_v16i8:
1179 %1 = load <16 x i8>* %a
1180 ; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5)
1181 %2 = load <16 x i8>* %b
1182 ; CHECK-DAG: ld.b [[R2:\$w[0-9]+]], 0($6)
1183 %3 = icmp uge <16 x i8> %1, %2
1184 %4 = select <16 x i1> %3, <16 x i8> %1, <16 x i8> %2
1185 ; CHECK-DAG: max_u.b [[R3:\$w[0-9]+]], [[R1]], [[R2]]
1186 store <16 x i8> %4, <16 x i8>* %c
1187 ; CHECK-DAG: st.b [[R3]], 0($4)
1190 ; CHECK: .size max_u_eq_v16i8
1193 define void @max_u_eq_v8i16(<8 x i16>* %c, <8 x i16>* %a, <8 x i16>* %b) nounwind {
1194 ; CHECK: max_u_eq_v8i16:
1196 %1 = load <8 x i16>* %a
1197 ; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5)
1198 %2 = load <8 x i16>* %b
1199 ; CHECK-DAG: ld.h [[R2:\$w[0-9]+]], 0($6)
1200 %3 = icmp uge <8 x i16> %1, %2
1201 %4 = select <8 x i1> %3, <8 x i16> %1, <8 x i16> %2
1202 ; CHECK-DAG: max_u.h [[R3:\$w[0-9]+]], [[R1]], [[R2]]
1203 store <8 x i16> %4, <8 x i16>* %c
1204 ; CHECK-DAG: st.h [[R3]], 0($4)
1207 ; CHECK: .size max_u_eq_v8i16
1210 define void @max_u_eq_v4i32(<4 x i32>* %c, <4 x i32>* %a, <4 x i32>* %b) nounwind {
1211 ; CHECK: max_u_eq_v4i32:
1213 %1 = load <4 x i32>* %a
1214 ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
1215 %2 = load <4 x i32>* %b
1216 ; CHECK-DAG: ld.w [[R2:\$w[0-9]+]], 0($6)
1217 %3 = icmp uge <4 x i32> %1, %2
1218 %4 = select <4 x i1> %3, <4 x i32> %1, <4 x i32> %2
1219 ; CHECK-DAG: max_u.w [[R3:\$w[0-9]+]], [[R1]], [[R2]]
1220 store <4 x i32> %4, <4 x i32>* %c
1221 ; CHECK-DAG: st.w [[R3]], 0($4)
1224 ; CHECK: .size max_u_eq_v4i32
1227 define void @max_u_eq_v2i64(<2 x i64>* %c, <2 x i64>* %a, <2 x i64>* %b) nounwind {
1228 ; CHECK: max_u_eq_v2i64:
1230 %1 = load <2 x i64>* %a
1231 ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
1232 %2 = load <2 x i64>* %b
1233 ; CHECK-DAG: ld.d [[R2:\$w[0-9]+]], 0($6)
1234 %3 = icmp uge <2 x i64> %1, %2
1235 %4 = select <2 x i1> %3, <2 x i64> %1, <2 x i64> %2
1236 ; CHECK-DAG: max_u.d [[R3:\$w[0-9]+]], [[R1]], [[R2]]
1237 store <2 x i64> %4, <2 x i64>* %c
1238 ; CHECK-DAG: st.d [[R3]], 0($4)
1241 ; CHECK: .size max_u_eq_v2i64
1244 define void @maxi_s_v16i8(<16 x i8>* %c, <16 x i8>* %a) nounwind {
1245 ; CHECK: maxi_s_v16i8:
1247 %1 = load <16 x i8>* %a
1248 ; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5)
1249 %2 = icmp sgt <16 x i8> %1, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
1250 %3 = select <16 x i1> %2, <16 x i8> %1, <16 x i8> <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
1251 ; CHECK-DAG: maxi_s.b [[R3:\$w[0-9]+]], [[R1]], 1
1252 store <16 x i8> %3, <16 x i8>* %c
1253 ; CHECK-DAG: st.b [[R3]], 0($4)
1256 ; CHECK: .size maxi_s_v16i8
1259 define void @maxi_s_v8i16(<8 x i16>* %c, <8 x i16>* %a) nounwind {
1260 ; CHECK: maxi_s_v8i16:
1262 %1 = load <8 x i16>* %a
1263 ; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5)
1264 %2 = icmp sgt <8 x i16> %1, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
1265 %3 = select <8 x i1> %2, <8 x i16> %1, <8 x i16> <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
1266 ; CHECK-DAG: maxi_s.h [[R3:\$w[0-9]+]], [[R1]], 1
1267 store <8 x i16> %3, <8 x i16>* %c
1268 ; CHECK-DAG: st.h [[R3]], 0($4)
1271 ; CHECK: .size maxi_s_v8i16
1274 define void @maxi_s_v4i32(<4 x i32>* %c, <4 x i32>* %a) nounwind {
1275 ; CHECK: maxi_s_v4i32:
1277 %1 = load <4 x i32>* %a
1278 ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
1279 %2 = icmp sgt <4 x i32> %1, <i32 1, i32 1, i32 1, i32 1>
1280 %3 = select <4 x i1> %2, <4 x i32> %1, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
1281 ; CHECK-DAG: maxi_s.w [[R3:\$w[0-9]+]], [[R1]], 1
1282 store <4 x i32> %3, <4 x i32>* %c
1283 ; CHECK-DAG: st.w [[R3]], 0($4)
1286 ; CHECK: .size maxi_s_v4i32
1289 define void @maxi_s_v2i64(<2 x i64>* %c, <2 x i64>* %a) nounwind {
1290 ; CHECK: maxi_s_v2i64:
1292 %1 = load <2 x i64>* %a
1293 ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
1294 %2 = icmp sgt <2 x i64> %1, <i64 1, i64 1>
1295 %3 = select <2 x i1> %2, <2 x i64> %1, <2 x i64> <i64 1, i64 1>
1296 ; CHECK-DAG: maxi_s.d [[R3:\$w[0-9]+]], [[R1]], 1
1297 store <2 x i64> %3, <2 x i64>* %c
1298 ; CHECK-DAG: st.d [[R3]], 0($4)
1301 ; CHECK: .size maxi_s_v2i64
1304 define void @maxi_u_v16i8(<16 x i8>* %c, <16 x i8>* %a) nounwind {
1305 ; CHECK: maxi_u_v16i8:
1307 %1 = load <16 x i8>* %a
1308 ; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5)
1309 %2 = icmp ugt <16 x i8> %1, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
1310 %3 = select <16 x i1> %2, <16 x i8> %1, <16 x i8> <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
1311 ; CHECK-DAG: maxi_u.b [[R3:\$w[0-9]+]], [[R1]], 1
1312 store <16 x i8> %3, <16 x i8>* %c
1313 ; CHECK-DAG: st.b [[R3]], 0($4)
1316 ; CHECK: .size maxi_u_v16i8
1319 define void @maxi_u_v8i16(<8 x i16>* %c, <8 x i16>* %a) nounwind {
1320 ; CHECK: maxi_u_v8i16:
1322 %1 = load <8 x i16>* %a
1323 ; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5)
1324 %2 = icmp ugt <8 x i16> %1, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
1325 %3 = select <8 x i1> %2, <8 x i16> %1, <8 x i16> <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
1326 ; CHECK-DAG: maxi_u.h [[R3:\$w[0-9]+]], [[R1]], 1
1327 store <8 x i16> %3, <8 x i16>* %c
1328 ; CHECK-DAG: st.h [[R3]], 0($4)
1331 ; CHECK: .size maxi_u_v8i16
1334 define void @maxi_u_v4i32(<4 x i32>* %c, <4 x i32>* %a) nounwind {
1335 ; CHECK: maxi_u_v4i32:
1337 %1 = load <4 x i32>* %a
1338 ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
1339 %2 = icmp ugt <4 x i32> %1, <i32 1, i32 1, i32 1, i32 1>
1340 %3 = select <4 x i1> %2, <4 x i32> %1, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
1341 ; CHECK-DAG: maxi_u.w [[R3:\$w[0-9]+]], [[R1]], 1
1342 store <4 x i32> %3, <4 x i32>* %c
1343 ; CHECK-DAG: st.w [[R3]], 0($4)
1346 ; CHECK: .size maxi_u_v4i32
1349 define void @maxi_u_v2i64(<2 x i64>* %c, <2 x i64>* %a) nounwind {
1350 ; CHECK: maxi_u_v2i64:
1352 %1 = load <2 x i64>* %a
1353 ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
1354 %2 = icmp ugt <2 x i64> %1, <i64 1, i64 1>
1355 %3 = select <2 x i1> %2, <2 x i64> %1, <2 x i64> <i64 1, i64 1>
1356 ; CHECK-DAG: maxi_u.d [[R3:\$w[0-9]+]], [[R1]], 1
1357 store <2 x i64> %3, <2 x i64>* %c
1358 ; CHECK-DAG: st.d [[R3]], 0($4)
1361 ; CHECK: .size maxi_u_v2i64
1364 define void @maxi_s_eq_v16i8(<16 x i8>* %c, <16 x i8>* %a) nounwind {
1365 ; CHECK: maxi_s_eq_v16i8:
1367 %1 = load <16 x i8>* %a
1368 ; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5)
1369 %2 = icmp sge <16 x i8> %1, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
1370 %3 = select <16 x i1> %2, <16 x i8> %1, <16 x i8> <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
1371 ; CHECK-DAG: maxi_s.b [[R3:\$w[0-9]+]], [[R1]], 1
1372 store <16 x i8> %3, <16 x i8>* %c
1373 ; CHECK-DAG: st.b [[R3]], 0($4)
1376 ; CHECK: .size maxi_s_eq_v16i8
1379 define void @maxi_s_eq_v8i16(<8 x i16>* %c, <8 x i16>* %a) nounwind {
1380 ; CHECK: maxi_s_eq_v8i16:
1382 %1 = load <8 x i16>* %a
1383 ; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5)
1384 %2 = icmp sge <8 x i16> %1, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
1385 %3 = select <8 x i1> %2, <8 x i16> %1, <8 x i16> <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
1386 ; CHECK-DAG: maxi_s.h [[R3:\$w[0-9]+]], [[R1]], 1
1387 store <8 x i16> %3, <8 x i16>* %c
1388 ; CHECK-DAG: st.h [[R3]], 0($4)
1391 ; CHECK: .size maxi_s_eq_v8i16
1394 define void @maxi_s_eq_v4i32(<4 x i32>* %c, <4 x i32>* %a) nounwind {
1395 ; CHECK: maxi_s_eq_v4i32:
1397 %1 = load <4 x i32>* %a
1398 ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
1399 %2 = icmp sge <4 x i32> %1, <i32 1, i32 1, i32 1, i32 1>
1400 %3 = select <4 x i1> %2, <4 x i32> %1, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
1401 ; CHECK-DAG: maxi_s.w [[R3:\$w[0-9]+]], [[R1]], 1
1402 store <4 x i32> %3, <4 x i32>* %c
1403 ; CHECK-DAG: st.w [[R3]], 0($4)
1406 ; CHECK: .size maxi_s_eq_v4i32
1409 define void @maxi_s_eq_v2i64(<2 x i64>* %c, <2 x i64>* %a) nounwind {
1410 ; CHECK: maxi_s_eq_v2i64:
1412 %1 = load <2 x i64>* %a
1413 ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
1414 %2 = icmp sge <2 x i64> %1, <i64 1, i64 1>
1415 %3 = select <2 x i1> %2, <2 x i64> %1, <2 x i64> <i64 1, i64 1>
1416 ; CHECK-DAG: maxi_s.d [[R3:\$w[0-9]+]], [[R1]], 1
1417 store <2 x i64> %3, <2 x i64>* %c
1418 ; CHECK-DAG: st.d [[R3]], 0($4)
1421 ; CHECK: .size maxi_s_eq_v2i64
1424 define void @maxi_u_eq_v16i8(<16 x i8>* %c, <16 x i8>* %a) nounwind {
1425 ; CHECK: maxi_u_eq_v16i8:
1427 %1 = load <16 x i8>* %a
1428 ; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5)
1429 %2 = icmp uge <16 x i8> %1, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
1430 %3 = select <16 x i1> %2, <16 x i8> %1, <16 x i8> <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
1431 ; CHECK-DAG: maxi_u.b [[R3:\$w[0-9]+]], [[R1]], 1
1432 store <16 x i8> %3, <16 x i8>* %c
1433 ; CHECK-DAG: st.b [[R3]], 0($4)
1436 ; CHECK: .size maxi_u_eq_v16i8
1439 define void @maxi_u_eq_v8i16(<8 x i16>* %c, <8 x i16>* %a) nounwind {
1440 ; CHECK: maxi_u_eq_v8i16:
1442 %1 = load <8 x i16>* %a
1443 ; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5)
1444 %2 = icmp uge <8 x i16> %1, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
1445 %3 = select <8 x i1> %2, <8 x i16> %1, <8 x i16> <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
1446 ; CHECK-DAG: maxi_u.h [[R3:\$w[0-9]+]], [[R1]], 1
1447 store <8 x i16> %3, <8 x i16>* %c
1448 ; CHECK-DAG: st.h [[R3]], 0($4)
1451 ; CHECK: .size maxi_u_eq_v8i16
1454 define void @maxi_u_eq_v4i32(<4 x i32>* %c, <4 x i32>* %a) nounwind {
1455 ; CHECK: maxi_u_eq_v4i32:
1457 %1 = load <4 x i32>* %a
1458 ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
1459 %2 = icmp uge <4 x i32> %1, <i32 1, i32 1, i32 1, i32 1>
1460 %3 = select <4 x i1> %2, <4 x i32> %1, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
1461 ; CHECK-DAG: maxi_u.w [[R3:\$w[0-9]+]], [[R1]], 1
1462 store <4 x i32> %3, <4 x i32>* %c
1463 ; CHECK-DAG: st.w [[R3]], 0($4)
1466 ; CHECK: .size maxi_u_eq_v4i32
1469 define void @maxi_u_eq_v2i64(<2 x i64>* %c, <2 x i64>* %a) nounwind {
1470 ; CHECK: maxi_u_eq_v2i64:
1472 %1 = load <2 x i64>* %a
1473 ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
1474 %2 = icmp uge <2 x i64> %1, <i64 1, i64 1>
1475 %3 = select <2 x i1> %2, <2 x i64> %1, <2 x i64> <i64 1, i64 1>
1476 ; CHECK-DAG: maxi_u.d [[R3:\$w[0-9]+]], [[R1]], 1
1477 store <2 x i64> %3, <2 x i64>* %c
1478 ; CHECK-DAG: st.d [[R3]], 0($4)
1481 ; CHECK: .size maxi_u_eq_v2i64
1484 define void @min_s_v16i8(<16 x i8>* %c, <16 x i8>* %a, <16 x i8>* %b) nounwind {
1485 ; CHECK: min_s_v16i8:
1487 %1 = load <16 x i8>* %a
1488 ; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5)
1489 %2 = load <16 x i8>* %b
1490 ; CHECK-DAG: ld.b [[R2:\$w[0-9]+]], 0($6)
1491 %3 = icmp sle <16 x i8> %1, %2
1492 %4 = select <16 x i1> %3, <16 x i8> %1, <16 x i8> %2
1493 ; CHECK-DAG: min_s.b [[R3:\$w[0-9]+]], [[R1]], [[R2]]
1494 store <16 x i8> %4, <16 x i8>* %c
1495 ; CHECK-DAG: st.b [[R3]], 0($4)
1498 ; CHECK: .size min_s_v16i8
1501 define void @min_s_v8i16(<8 x i16>* %c, <8 x i16>* %a, <8 x i16>* %b) nounwind {
1502 ; CHECK: min_s_v8i16:
1504 %1 = load <8 x i16>* %a
1505 ; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5)
1506 %2 = load <8 x i16>* %b
1507 ; CHECK-DAG: ld.h [[R2:\$w[0-9]+]], 0($6)
1508 %3 = icmp slt <8 x i16> %1, %2
1509 %4 = select <8 x i1> %3, <8 x i16> %1, <8 x i16> %2
1510 ; CHECK-DAG: min_s.h [[R3:\$w[0-9]+]], [[R1]], [[R2]]
1511 store <8 x i16> %4, <8 x i16>* %c
1512 ; CHECK-DAG: st.h [[R3]], 0($4)
1515 ; CHECK: .size min_s_v8i16
1518 define void @min_s_v4i32(<4 x i32>* %c, <4 x i32>* %a, <4 x i32>* %b) nounwind {
1519 ; CHECK: min_s_v4i32:
1521 %1 = load <4 x i32>* %a
1522 ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
1523 %2 = load <4 x i32>* %b
1524 ; CHECK-DAG: ld.w [[R2:\$w[0-9]+]], 0($6)
1525 %3 = icmp slt <4 x i32> %1, %2
1526 %4 = select <4 x i1> %3, <4 x i32> %1, <4 x i32> %2
1527 ; CHECK-DAG: min_s.w [[R3:\$w[0-9]+]], [[R1]], [[R2]]
1528 store <4 x i32> %4, <4 x i32>* %c
1529 ; CHECK-DAG: st.w [[R3]], 0($4)
1532 ; CHECK: .size min_s_v4i32
1535 define void @min_s_v2i64(<2 x i64>* %c, <2 x i64>* %a, <2 x i64>* %b) nounwind {
1536 ; CHECK: min_s_v2i64:
1538 %1 = load <2 x i64>* %a
1539 ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
1540 %2 = load <2 x i64>* %b
1541 ; CHECK-DAG: ld.d [[R2:\$w[0-9]+]], 0($6)
1542 %3 = icmp slt <2 x i64> %1, %2
1543 %4 = select <2 x i1> %3, <2 x i64> %1, <2 x i64> %2
1544 ; CHECK-DAG: min_s.d [[R3:\$w[0-9]+]], [[R1]], [[R2]]
1545 store <2 x i64> %4, <2 x i64>* %c
1546 ; CHECK-DAG: st.d [[R3]], 0($4)
1549 ; CHECK: .size min_s_v2i64
1552 define void @min_u_v16i8(<16 x i8>* %c, <16 x i8>* %a, <16 x i8>* %b) nounwind {
1553 ; CHECK: min_u_v16i8:
1555 %1 = load <16 x i8>* %a
1556 ; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5)
1557 %2 = load <16 x i8>* %b
1558 ; CHECK-DAG: ld.b [[R2:\$w[0-9]+]], 0($6)
1559 %3 = icmp ult <16 x i8> %1, %2
1560 %4 = select <16 x i1> %3, <16 x i8> %1, <16 x i8> %2
1561 ; CHECK-DAG: min_u.b [[R3:\$w[0-9]+]], [[R1]], [[R2]]
1562 store <16 x i8> %4, <16 x i8>* %c
1563 ; CHECK-DAG: st.b [[R3]], 0($4)
1566 ; CHECK: .size min_u_v16i8
1569 define void @min_u_v8i16(<8 x i16>* %c, <8 x i16>* %a, <8 x i16>* %b) nounwind {
1570 ; CHECK: min_u_v8i16:
1572 %1 = load <8 x i16>* %a
1573 ; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5)
1574 %2 = load <8 x i16>* %b
1575 ; CHECK-DAG: ld.h [[R2:\$w[0-9]+]], 0($6)
1576 %3 = icmp ult <8 x i16> %1, %2
1577 %4 = select <8 x i1> %3, <8 x i16> %1, <8 x i16> %2
1578 ; CHECK-DAG: min_u.h [[R3:\$w[0-9]+]], [[R1]], [[R2]]
1579 store <8 x i16> %4, <8 x i16>* %c
1580 ; CHECK-DAG: st.h [[R3]], 0($4)
1583 ; CHECK: .size min_u_v8i16
1586 define void @min_u_v4i32(<4 x i32>* %c, <4 x i32>* %a, <4 x i32>* %b) nounwind {
1587 ; CHECK: min_u_v4i32:
1589 %1 = load <4 x i32>* %a
1590 ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
1591 %2 = load <4 x i32>* %b
1592 ; CHECK-DAG: ld.w [[R2:\$w[0-9]+]], 0($6)
1593 %3 = icmp ult <4 x i32> %1, %2
1594 %4 = select <4 x i1> %3, <4 x i32> %1, <4 x i32> %2
1595 ; CHECK-DAG: min_u.w [[R3:\$w[0-9]+]], [[R1]], [[R2]]
1596 store <4 x i32> %4, <4 x i32>* %c
1597 ; CHECK-DAG: st.w [[R3]], 0($4)
1600 ; CHECK: .size min_u_v4i32
1603 define void @min_u_v2i64(<2 x i64>* %c, <2 x i64>* %a, <2 x i64>* %b) nounwind {
1604 ; CHECK: min_u_v2i64:
1606 %1 = load <2 x i64>* %a
1607 ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
1608 %2 = load <2 x i64>* %b
1609 ; CHECK-DAG: ld.d [[R2:\$w[0-9]+]], 0($6)
1610 %3 = icmp ult <2 x i64> %1, %2
1611 %4 = select <2 x i1> %3, <2 x i64> %1, <2 x i64> %2
1612 ; CHECK-DAG: min_u.d [[R3:\$w[0-9]+]], [[R1]], [[R2]]
1613 store <2 x i64> %4, <2 x i64>* %c
1614 ; CHECK-DAG: st.d [[R3]], 0($4)
1617 ; CHECK: .size min_u_v2i64
1620 define void @min_s_eq_v16i8(<16 x i8>* %c, <16 x i8>* %a, <16 x i8>* %b) nounwind {
1621 ; CHECK: min_s_eq_v16i8:
1623 %1 = load <16 x i8>* %a
1624 ; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5)
1625 %2 = load <16 x i8>* %b
1626 ; CHECK-DAG: ld.b [[R2:\$w[0-9]+]], 0($6)
1627 %3 = icmp sle <16 x i8> %1, %2
1628 %4 = select <16 x i1> %3, <16 x i8> %1, <16 x i8> %2
1629 ; CHECK-DAG: min_s.b [[R3:\$w[0-9]+]], [[R1]], [[R2]]
1630 store <16 x i8> %4, <16 x i8>* %c
1631 ; CHECK-DAG: st.b [[R3]], 0($4)
1634 ; CHECK: .size min_s_eq_v16i8
1637 define void @min_s_eq_v8i16(<8 x i16>* %c, <8 x i16>* %a, <8 x i16>* %b) nounwind {
1638 ; CHECK: min_s_eq_v8i16:
1640 %1 = load <8 x i16>* %a
1641 ; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5)
1642 %2 = load <8 x i16>* %b
1643 ; CHECK-DAG: ld.h [[R2:\$w[0-9]+]], 0($6)
1644 %3 = icmp sle <8 x i16> %1, %2
1645 %4 = select <8 x i1> %3, <8 x i16> %1, <8 x i16> %2
1646 ; CHECK-DAG: min_s.h [[R3:\$w[0-9]+]], [[R1]], [[R2]]
1647 store <8 x i16> %4, <8 x i16>* %c
1648 ; CHECK-DAG: st.h [[R3]], 0($4)
1651 ; CHECK: .size min_s_eq_v8i16
1654 define void @min_s_eq_v4i32(<4 x i32>* %c, <4 x i32>* %a, <4 x i32>* %b) nounwind {
1655 ; CHECK: min_s_eq_v4i32:
1657 %1 = load <4 x i32>* %a
1658 ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
1659 %2 = load <4 x i32>* %b
1660 ; CHECK-DAG: ld.w [[R2:\$w[0-9]+]], 0($6)
1661 %3 = icmp sle <4 x i32> %1, %2
1662 %4 = select <4 x i1> %3, <4 x i32> %1, <4 x i32> %2
1663 ; CHECK-DAG: min_s.w [[R3:\$w[0-9]+]], [[R1]], [[R2]]
1664 store <4 x i32> %4, <4 x i32>* %c
1665 ; CHECK-DAG: st.w [[R3]], 0($4)
1668 ; CHECK: .size min_s_eq_v4i32
1671 define void @min_s_eq_v2i64(<2 x i64>* %c, <2 x i64>* %a, <2 x i64>* %b) nounwind {
1672 ; CHECK: min_s_eq_v2i64:
1674 %1 = load <2 x i64>* %a
1675 ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
1676 %2 = load <2 x i64>* %b
1677 ; CHECK-DAG: ld.d [[R2:\$w[0-9]+]], 0($6)
1678 %3 = icmp sle <2 x i64> %1, %2
1679 %4 = select <2 x i1> %3, <2 x i64> %1, <2 x i64> %2
1680 ; CHECK-DAG: min_s.d [[R3:\$w[0-9]+]], [[R1]], [[R2]]
1681 store <2 x i64> %4, <2 x i64>* %c
1682 ; CHECK-DAG: st.d [[R3]], 0($4)
1685 ; CHECK: .size min_s_eq_v2i64
1688 define void @min_u_eq_v16i8(<16 x i8>* %c, <16 x i8>* %a, <16 x i8>* %b) nounwind {
1689 ; CHECK: min_u_eq_v16i8:
1691 %1 = load <16 x i8>* %a
1692 ; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5)
1693 %2 = load <16 x i8>* %b
1694 ; CHECK-DAG: ld.b [[R2:\$w[0-9]+]], 0($6)
1695 %3 = icmp ule <16 x i8> %1, %2
1696 %4 = select <16 x i1> %3, <16 x i8> %1, <16 x i8> %2
1697 ; CHECK-DAG: min_u.b [[R3:\$w[0-9]+]], [[R1]], [[R2]]
1698 store <16 x i8> %4, <16 x i8>* %c
1699 ; CHECK-DAG: st.b [[R3]], 0($4)
1702 ; CHECK: .size min_u_eq_v16i8
1705 define void @min_u_eq_v8i16(<8 x i16>* %c, <8 x i16>* %a, <8 x i16>* %b) nounwind {
1706 ; CHECK: min_u_eq_v8i16:
1708 %1 = load <8 x i16>* %a
1709 ; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5)
1710 %2 = load <8 x i16>* %b
1711 ; CHECK-DAG: ld.h [[R2:\$w[0-9]+]], 0($6)
1712 %3 = icmp ule <8 x i16> %1, %2
1713 %4 = select <8 x i1> %3, <8 x i16> %1, <8 x i16> %2
1714 ; CHECK-DAG: min_u.h [[R3:\$w[0-9]+]], [[R1]], [[R2]]
1715 store <8 x i16> %4, <8 x i16>* %c
1716 ; CHECK-DAG: st.h [[R3]], 0($4)
1719 ; CHECK: .size min_u_eq_v8i16
1722 define void @min_u_eq_v4i32(<4 x i32>* %c, <4 x i32>* %a, <4 x i32>* %b) nounwind {
1723 ; CHECK: min_u_eq_v4i32:
1725 %1 = load <4 x i32>* %a
1726 ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
1727 %2 = load <4 x i32>* %b
1728 ; CHECK-DAG: ld.w [[R2:\$w[0-9]+]], 0($6)
1729 %3 = icmp ule <4 x i32> %1, %2
1730 %4 = select <4 x i1> %3, <4 x i32> %1, <4 x i32> %2
1731 ; CHECK-DAG: min_u.w [[R3:\$w[0-9]+]], [[R1]], [[R2]]
1732 store <4 x i32> %4, <4 x i32>* %c
1733 ; CHECK-DAG: st.w [[R3]], 0($4)
1736 ; CHECK: .size min_u_eq_v4i32
1739 define void @min_u_eq_v2i64(<2 x i64>* %c, <2 x i64>* %a, <2 x i64>* %b) nounwind {
1740 ; CHECK: min_u_eq_v2i64:
1742 %1 = load <2 x i64>* %a
1743 ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
1744 %2 = load <2 x i64>* %b
1745 ; CHECK-DAG: ld.d [[R2:\$w[0-9]+]], 0($6)
1746 %3 = icmp ule <2 x i64> %1, %2
1747 %4 = select <2 x i1> %3, <2 x i64> %1, <2 x i64> %2
1748 ; CHECK-DAG: min_u.d [[R3:\$w[0-9]+]], [[R1]], [[R2]]
1749 store <2 x i64> %4, <2 x i64>* %c
1750 ; CHECK-DAG: st.d [[R3]], 0($4)
1753 ; CHECK: .size min_u_eq_v2i64
1756 define void @mini_s_v16i8(<16 x i8>* %c, <16 x i8>* %a) nounwind {
1757 ; CHECK: mini_s_v16i8:
1759 %1 = load <16 x i8>* %a
1760 ; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5)
1761 %2 = icmp slt <16 x i8> %1, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
1762 %3 = select <16 x i1> %2, <16 x i8> %1, <16 x i8> <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
1763 ; CHECK-DAG: mini_s.b [[R3:\$w[0-9]+]], [[R1]], 1
1764 store <16 x i8> %3, <16 x i8>* %c
1765 ; CHECK-DAG: st.b [[R3]], 0($4)
1768 ; CHECK: .size mini_s_v16i8
1771 define void @mini_s_v8i16(<8 x i16>* %c, <8 x i16>* %a) nounwind {
1772 ; CHECK: mini_s_v8i16:
1774 %1 = load <8 x i16>* %a
1775 ; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5)
1776 %2 = icmp slt <8 x i16> %1, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
1777 %3 = select <8 x i1> %2, <8 x i16> %1, <8 x i16> <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
1778 ; CHECK-DAG: mini_s.h [[R3:\$w[0-9]+]], [[R1]], 1
1779 store <8 x i16> %3, <8 x i16>* %c
1780 ; CHECK-DAG: st.h [[R3]], 0($4)
1783 ; CHECK: .size mini_s_v8i16
1786 define void @mini_s_v4i32(<4 x i32>* %c, <4 x i32>* %a) nounwind {
1787 ; CHECK: mini_s_v4i32:
1789 %1 = load <4 x i32>* %a
1790 ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
1791 %2 = icmp slt <4 x i32> %1, <i32 1, i32 1, i32 1, i32 1>
1792 %3 = select <4 x i1> %2, <4 x i32> %1, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
1793 ; CHECK-DAG: mini_s.w [[R3:\$w[0-9]+]], [[R1]], 1
1794 store <4 x i32> %3, <4 x i32>* %c
1795 ; CHECK-DAG: st.w [[R3]], 0($4)
1798 ; CHECK: .size mini_s_v4i32
1801 define void @mini_s_v2i64(<2 x i64>* %c, <2 x i64>* %a) nounwind {
1802 ; CHECK: mini_s_v2i64:
1804 %1 = load <2 x i64>* %a
1805 ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
1806 %2 = icmp slt <2 x i64> %1, <i64 1, i64 1>
1807 %3 = select <2 x i1> %2, <2 x i64> %1, <2 x i64> <i64 1, i64 1>
1808 ; CHECK-DAG: mini_s.d [[R3:\$w[0-9]+]], [[R1]], 1
1809 store <2 x i64> %3, <2 x i64>* %c
1810 ; CHECK-DAG: st.d [[R3]], 0($4)
1813 ; CHECK: .size mini_s_v2i64
1816 define void @mini_u_v16i8(<16 x i8>* %c, <16 x i8>* %a) nounwind {
1817 ; CHECK: mini_u_v16i8:
1819 %1 = load <16 x i8>* %a
1820 ; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5)
1821 %2 = icmp ult <16 x i8> %1, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
1822 %3 = select <16 x i1> %2, <16 x i8> %1, <16 x i8> <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
1823 ; CHECK-DAG: mini_u.b [[R3:\$w[0-9]+]], [[R1]], 1
1824 store <16 x i8> %3, <16 x i8>* %c
1825 ; CHECK-DAG: st.b [[R3]], 0($4)
1828 ; CHECK: .size mini_u_v16i8
1831 define void @mini_u_v8i16(<8 x i16>* %c, <8 x i16>* %a) nounwind {
1832 ; CHECK: mini_u_v8i16:
1834 %1 = load <8 x i16>* %a
1835 ; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5)
1836 %2 = icmp ult <8 x i16> %1, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
1837 %3 = select <8 x i1> %2, <8 x i16> %1, <8 x i16> <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
1838 ; CHECK-DAG: mini_u.h [[R3:\$w[0-9]+]], [[R1]], 1
1839 store <8 x i16> %3, <8 x i16>* %c
1840 ; CHECK-DAG: st.h [[R3]], 0($4)
1843 ; CHECK: .size mini_u_v8i16
1846 define void @mini_u_v4i32(<4 x i32>* %c, <4 x i32>* %a) nounwind {
1847 ; CHECK: mini_u_v4i32:
1849 %1 = load <4 x i32>* %a
1850 ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
1851 %2 = icmp ult <4 x i32> %1, <i32 1, i32 1, i32 1, i32 1>
1852 %3 = select <4 x i1> %2, <4 x i32> %1, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
1853 ; CHECK-DAG: mini_u.w [[R3:\$w[0-9]+]], [[R1]], 1
1854 store <4 x i32> %3, <4 x i32>* %c
1855 ; CHECK-DAG: st.w [[R3]], 0($4)
1858 ; CHECK: .size mini_u_v4i32
1861 define void @mini_u_v2i64(<2 x i64>* %c, <2 x i64>* %a) nounwind {
1862 ; CHECK: mini_u_v2i64:
1864 %1 = load <2 x i64>* %a
1865 ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
1866 %2 = icmp ult <2 x i64> %1, <i64 1, i64 1>
1867 %3 = select <2 x i1> %2, <2 x i64> %1, <2 x i64> <i64 1, i64 1>
1868 ; CHECK-DAG: mini_u.d [[R3:\$w[0-9]+]], [[R1]], 1
1869 store <2 x i64> %3, <2 x i64>* %c
1870 ; CHECK-DAG: st.d [[R3]], 0($4)
1873 ; CHECK: .size mini_u_v2i64
1876 define void @mini_s_eq_v16i8(<16 x i8>* %c, <16 x i8>* %a) nounwind {
1877 ; CHECK: mini_s_eq_v16i8:
1879 %1 = load <16 x i8>* %a
1880 ; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5)
1881 %2 = icmp sle <16 x i8> %1, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
1882 %3 = select <16 x i1> %2, <16 x i8> %1, <16 x i8> <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
1883 ; CHECK-DAG: mini_s.b [[R3:\$w[0-9]+]], [[R1]], 1
1884 store <16 x i8> %3, <16 x i8>* %c
1885 ; CHECK-DAG: st.b [[R3]], 0($4)
1888 ; CHECK: .size mini_s_eq_v16i8
1891 define void @mini_s_eq_v8i16(<8 x i16>* %c, <8 x i16>* %a) nounwind {
1892 ; CHECK: mini_s_eq_v8i16:
1894 %1 = load <8 x i16>* %a
1895 ; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5)
1896 %2 = icmp sle <8 x i16> %1, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
1897 %3 = select <8 x i1> %2, <8 x i16> %1, <8 x i16> <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
1898 ; CHECK-DAG: mini_s.h [[R3:\$w[0-9]+]], [[R1]], 1
1899 store <8 x i16> %3, <8 x i16>* %c
1900 ; CHECK-DAG: st.h [[R3]], 0($4)
1903 ; CHECK: .size mini_s_eq_v8i16
1906 define void @mini_s_eq_v4i32(<4 x i32>* %c, <4 x i32>* %a) nounwind {
1907 ; CHECK: mini_s_eq_v4i32:
1909 %1 = load <4 x i32>* %a
1910 ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
1911 %2 = icmp sle <4 x i32> %1, <i32 1, i32 1, i32 1, i32 1>
1912 %3 = select <4 x i1> %2, <4 x i32> %1, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
1913 ; CHECK-DAG: mini_s.w [[R3:\$w[0-9]+]], [[R1]], 1
1914 store <4 x i32> %3, <4 x i32>* %c
1915 ; CHECK-DAG: st.w [[R3]], 0($4)
1918 ; CHECK: .size mini_s_eq_v4i32
1921 define void @mini_s_eq_v2i64(<2 x i64>* %c, <2 x i64>* %a) nounwind {
1922 ; CHECK: mini_s_eq_v2i64:
1924 %1 = load <2 x i64>* %a
1925 ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
1926 %2 = icmp sle <2 x i64> %1, <i64 1, i64 1>
1927 %3 = select <2 x i1> %2, <2 x i64> %1, <2 x i64> <i64 1, i64 1>
1928 ; CHECK-DAG: mini_s.d [[R3:\$w[0-9]+]], [[R1]], 1
1929 store <2 x i64> %3, <2 x i64>* %c
1930 ; CHECK-DAG: st.d [[R3]], 0($4)
1933 ; CHECK: .size mini_s_eq_v2i64
1936 define void @mini_u_eq_v16i8(<16 x i8>* %c, <16 x i8>* %a) nounwind {
1937 ; CHECK: mini_u_eq_v16i8:
1939 %1 = load <16 x i8>* %a
1940 ; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5)
1941 %2 = icmp ule <16 x i8> %1, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
1942 %3 = select <16 x i1> %2, <16 x i8> %1, <16 x i8> <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
1943 ; CHECK-DAG: mini_u.b [[R3:\$w[0-9]+]], [[R1]], 1
1944 store <16 x i8> %3, <16 x i8>* %c
1945 ; CHECK-DAG: st.b [[R3]], 0($4)
1948 ; CHECK: .size mini_u_eq_v16i8
1951 define void @mini_u_eq_v8i16(<8 x i16>* %c, <8 x i16>* %a) nounwind {
1952 ; CHECK: mini_u_eq_v8i16:
1954 %1 = load <8 x i16>* %a
1955 ; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5)
1956 %2 = icmp ule <8 x i16> %1, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
1957 %3 = select <8 x i1> %2, <8 x i16> %1, <8 x i16> <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
1958 ; CHECK-DAG: mini_u.h [[R3:\$w[0-9]+]], [[R1]], 1
1959 store <8 x i16> %3, <8 x i16>* %c
1960 ; CHECK-DAG: st.h [[R3]], 0($4)
1963 ; CHECK: .size mini_u_eq_v8i16
1966 define void @mini_u_eq_v4i32(<4 x i32>* %c, <4 x i32>* %a) nounwind {
1967 ; CHECK: mini_u_eq_v4i32:
1969 %1 = load <4 x i32>* %a
1970 ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
1971 %2 = icmp ule <4 x i32> %1, <i32 1, i32 1, i32 1, i32 1>
1972 %3 = select <4 x i1> %2, <4 x i32> %1, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
1973 ; CHECK-DAG: mini_u.w [[R3:\$w[0-9]+]], [[R1]], 1
1974 store <4 x i32> %3, <4 x i32>* %c
1975 ; CHECK-DAG: st.w [[R3]], 0($4)
1978 ; CHECK: .size mini_u_eq_v4i32
1981 define void @mini_u_eq_v2i64(<2 x i64>* %c, <2 x i64>* %a) nounwind {
1982 ; CHECK: mini_u_eq_v2i64:
1984 %1 = load <2 x i64>* %a
1985 ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
1986 %2 = icmp ule <2 x i64> %1, <i64 1, i64 1>
1987 %3 = select <2 x i1> %2, <2 x i64> %1, <2 x i64> <i64 1, i64 1>
1988 ; CHECK-DAG: mini_u.d [[R3:\$w[0-9]+]], [[R1]], 1
1989 store <2 x i64> %3, <2 x i64>* %c
1990 ; CHECK-DAG: st.d [[R3]], 0($4)
1993 ; CHECK: .size mini_u_eq_v2i64