1 ; Test the MSA intrinsics that are encoded with the I5 instruction format.
2 ; There are lots of these so this covers those beginning with 'b'
4 ; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s
6 @llvm_mips_bclri_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
7 @llvm_mips_bclri_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16
9 define void @llvm_mips_bclri_b_test() nounwind {
11 %0 = load <16 x i8>* @llvm_mips_bclri_b_ARG1
12 %1 = tail call <16 x i8> @llvm.mips.bclri.b(<16 x i8> %0, i32 7)
13 store <16 x i8> %1, <16 x i8>* @llvm_mips_bclri_b_RES
17 declare <16 x i8> @llvm.mips.bclri.b(<16 x i8>, i32) nounwind
19 ; CHECK: llvm_mips_bclri_b_test:
23 ; CHECK: .size llvm_mips_bclri_b_test
25 @llvm_mips_bclri_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16
26 @llvm_mips_bclri_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16
28 define void @llvm_mips_bclri_h_test() nounwind {
30 %0 = load <8 x i16>* @llvm_mips_bclri_h_ARG1
31 %1 = tail call <8 x i16> @llvm.mips.bclri.h(<8 x i16> %0, i32 7)
32 store <8 x i16> %1, <8 x i16>* @llvm_mips_bclri_h_RES
36 declare <8 x i16> @llvm.mips.bclri.h(<8 x i16>, i32) nounwind
38 ; CHECK: llvm_mips_bclri_h_test:
42 ; CHECK: .size llvm_mips_bclri_h_test
44 @llvm_mips_bclri_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16
45 @llvm_mips_bclri_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16
47 define void @llvm_mips_bclri_w_test() nounwind {
49 %0 = load <4 x i32>* @llvm_mips_bclri_w_ARG1
50 %1 = tail call <4 x i32> @llvm.mips.bclri.w(<4 x i32> %0, i32 7)
51 store <4 x i32> %1, <4 x i32>* @llvm_mips_bclri_w_RES
55 declare <4 x i32> @llvm.mips.bclri.w(<4 x i32>, i32) nounwind
57 ; CHECK: llvm_mips_bclri_w_test:
61 ; CHECK: .size llvm_mips_bclri_w_test
63 @llvm_mips_bclri_d_ARG1 = global <2 x i64> <i64 0, i64 1>, align 16
64 @llvm_mips_bclri_d_RES = global <2 x i64> <i64 0, i64 0>, align 16
66 define void @llvm_mips_bclri_d_test() nounwind {
68 %0 = load <2 x i64>* @llvm_mips_bclri_d_ARG1
69 %1 = tail call <2 x i64> @llvm.mips.bclri.d(<2 x i64> %0, i32 7)
70 store <2 x i64> %1, <2 x i64>* @llvm_mips_bclri_d_RES
74 declare <2 x i64> @llvm.mips.bclri.d(<2 x i64>, i32) nounwind
76 ; CHECK: llvm_mips_bclri_d_test:
80 ; CHECK: .size llvm_mips_bclri_d_test
82 @llvm_mips_binsli_b_ARG1 = global <16 x i8> zeroinitializer, align 16
83 @llvm_mips_binsli_b_ARG2 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
84 @llvm_mips_binsli_b_RES = global <16 x i8> zeroinitializer, align 16
86 define void @llvm_mips_binsli_b_test() nounwind {
88 %0 = load <16 x i8>* @llvm_mips_binsli_b_ARG1
89 %1 = load <16 x i8>* @llvm_mips_binsli_b_ARG2
90 %2 = tail call <16 x i8> @llvm.mips.binsli.b(<16 x i8> %0, <16 x i8> %1, i32 7)
91 store <16 x i8> %2, <16 x i8>* @llvm_mips_binsli_b_RES
95 declare <16 x i8> @llvm.mips.binsli.b(<16 x i8>, <16 x i8>, i32) nounwind
97 ; CHECK: llvm_mips_binsli_b_test:
98 ; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_binsli_b_ARG1)(
99 ; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_binsli_b_ARG2)(
100 ; CHECK-DAG: ld.b [[R3:\$w[0-9]+]], 0([[R1]])
101 ; CHECK-DAG: ld.b [[R4:\$w[0-9]+]], 0([[R2]])
102 ; CHECK-DAG: binsli.b [[R3]], [[R4]], 7
103 ; CHECK-DAG: lw [[R5:\$[0-9]+]], %got(llvm_mips_binsli_b_RES)(
104 ; CHECK-DAG: st.b [[R3]], 0([[R5]])
105 ; CHECK: .size llvm_mips_binsli_b_test
107 @llvm_mips_binsli_h_ARG1 = global <8 x i16> zeroinitializer, align 16
108 @llvm_mips_binsli_h_ARG2 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16
109 @llvm_mips_binsli_h_RES = global <8 x i16> zeroinitializer, align 16
111 define void @llvm_mips_binsli_h_test() nounwind {
113 %0 = load <8 x i16>* @llvm_mips_binsli_h_ARG1
114 %1 = load <8 x i16>* @llvm_mips_binsli_h_ARG2
115 %2 = tail call <8 x i16> @llvm.mips.binsli.h(<8 x i16> %0, <8 x i16> %1, i32 7)
116 store <8 x i16> %2, <8 x i16>* @llvm_mips_binsli_h_RES
120 declare <8 x i16> @llvm.mips.binsli.h(<8 x i16>, <8 x i16>, i32) nounwind
122 ; CHECK: llvm_mips_binsli_h_test:
123 ; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_binsli_h_ARG1)(
124 ; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_binsli_h_ARG2)(
125 ; CHECK-DAG: ld.h [[R3:\$w[0-9]+]], 0([[R1]])
126 ; CHECK-DAG: ld.h [[R4:\$w[0-9]+]], 0([[R2]])
127 ; CHECK-DAG: binsli.h [[R3]], [[R4]], 7
128 ; CHECK-DAG: lw [[R5:\$[0-9]+]], %got(llvm_mips_binsli_h_RES)(
129 ; CHECK-DAG: st.h [[R3]], 0([[R5]])
130 ; CHECK: .size llvm_mips_binsli_h_test
132 @llvm_mips_binsli_w_ARG1 = global <4 x i32> zeroinitializer, align 16
133 @llvm_mips_binsli_w_ARG2 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16
134 @llvm_mips_binsli_w_RES = global <4 x i32> zeroinitializer, align 16
136 define void @llvm_mips_binsli_w_test() nounwind {
138 %0 = load <4 x i32>* @llvm_mips_binsli_w_ARG1
139 %1 = load <4 x i32>* @llvm_mips_binsli_w_ARG2
140 %2 = tail call <4 x i32> @llvm.mips.binsli.w(<4 x i32> %0, <4 x i32> %1, i32 7)
141 store <4 x i32> %2, <4 x i32>* @llvm_mips_binsli_w_RES
145 declare <4 x i32> @llvm.mips.binsli.w(<4 x i32>, <4 x i32>, i32) nounwind
147 ; CHECK: llvm_mips_binsli_w_test:
148 ; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_binsli_w_ARG1)(
149 ; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_binsli_w_ARG2)(
150 ; CHECK-DAG: ld.w [[R3:\$w[0-9]+]], 0([[R1]])
151 ; CHECK-DAG: ld.w [[R4:\$w[0-9]+]], 0([[R2]])
152 ; CHECK-DAG: binsli.w [[R3]], [[R4]], 7
153 ; CHECK-DAG: lw [[R5:\$[0-9]+]], %got(llvm_mips_binsli_w_RES)(
154 ; CHECK-DAG: st.w [[R3]], 0([[R5]])
155 ; CHECK: .size llvm_mips_binsli_w_test
157 @llvm_mips_binsli_d_ARG1 = global <2 x i64> zeroinitializer, align 16
158 @llvm_mips_binsli_d_ARG2 = global <2 x i64> <i64 0, i64 1>, align 16
159 @llvm_mips_binsli_d_RES = global <2 x i64> zeroinitializer, align 16
161 define void @llvm_mips_binsli_d_test() nounwind {
163 %0 = load <2 x i64>* @llvm_mips_binsli_d_ARG1
164 %1 = load <2 x i64>* @llvm_mips_binsli_d_ARG2
165 ; TODO: We use a particularly wide mask here to work around a legalization
166 ; issue. If the mask doesn't fit within a 10-bit immediate, it gets
167 ; legalized into a constant pool. We should add a test to cover the
168 ; other cases once they correctly select binsli.d.
169 %2 = tail call <2 x i64> @llvm.mips.binsli.d(<2 x i64> %0, <2 x i64> %1, i32 61)
170 store <2 x i64> %2, <2 x i64>* @llvm_mips_binsli_d_RES
174 declare <2 x i64> @llvm.mips.binsli.d(<2 x i64>, <2 x i64>, i32) nounwind
176 ; CHECK: llvm_mips_binsli_d_test:
177 ; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_binsli_d_ARG1)(
178 ; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_binsli_d_ARG2)(
179 ; CHECK-DAG: ld.d [[R3:\$w[0-9]+]], 0([[R1]])
180 ; CHECK-DAG: ld.d [[R4:\$w[0-9]+]], 0([[R2]])
181 ; CHECK-DAG: binsli.d [[R3]], [[R4]], 61
182 ; CHECK-DAG: lw [[R5:\$[0-9]+]], %got(llvm_mips_binsli_d_RES)(
183 ; CHECK-DAG: st.d [[R3]], 0([[R5]])
184 ; CHECK: .size llvm_mips_binsli_d_test
186 @llvm_mips_binsri_b_ARG1 = global <16 x i8> zeroinitializer, align 16
187 @llvm_mips_binsri_b_ARG2 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
188 @llvm_mips_binsri_b_RES = global <16 x i8> zeroinitializer, align 16
190 define void @llvm_mips_binsri_b_test() nounwind {
192 %0 = load <16 x i8>* @llvm_mips_binsri_b_ARG1
193 %1 = load <16 x i8>* @llvm_mips_binsri_b_ARG2
194 %2 = tail call <16 x i8> @llvm.mips.binsri.b(<16 x i8> %0, <16 x i8> %1, i32 7)
195 store <16 x i8> %2, <16 x i8>* @llvm_mips_binsri_b_RES
199 declare <16 x i8> @llvm.mips.binsri.b(<16 x i8>, <16 x i8>, i32) nounwind
201 ; CHECK: llvm_mips_binsri_b_test:
202 ; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_binsri_b_ARG1)(
203 ; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_binsri_b_ARG2)(
204 ; CHECK-DAG: ld.b [[R3:\$w[0-9]+]], 0([[R1]])
205 ; CHECK-DAG: ld.b [[R4:\$w[0-9]+]], 0([[R2]])
206 ; CHECK-DAG: binsri.b [[R3]], [[R4]], 7
207 ; CHECK-DAG: lw [[R5:\$[0-9]+]], %got(llvm_mips_binsri_b_RES)(
208 ; CHECK-DAG: st.b [[R3]], 0([[R5]])
209 ; CHECK: .size llvm_mips_binsri_b_test
211 @llvm_mips_binsri_h_ARG1 = global <8 x i16> zeroinitializer, align 16
212 @llvm_mips_binsri_h_ARG2 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16
213 @llvm_mips_binsri_h_RES = global <8 x i16> zeroinitializer, align 16
215 define void @llvm_mips_binsri_h_test() nounwind {
217 %0 = load <8 x i16>* @llvm_mips_binsri_h_ARG1
218 %1 = load <8 x i16>* @llvm_mips_binsri_h_ARG2
219 %2 = tail call <8 x i16> @llvm.mips.binsri.h(<8 x i16> %0, <8 x i16> %1, i32 7)
220 store <8 x i16> %2, <8 x i16>* @llvm_mips_binsri_h_RES
224 declare <8 x i16> @llvm.mips.binsri.h(<8 x i16>, <8 x i16>, i32) nounwind
226 ; CHECK: llvm_mips_binsri_h_test:
227 ; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_binsri_h_ARG1)(
228 ; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_binsri_h_ARG2)(
229 ; CHECK-DAG: ld.h [[R3:\$w[0-9]+]], 0([[R1]])
230 ; CHECK-DAG: ld.h [[R4:\$w[0-9]+]], 0([[R2]])
231 ; CHECK-DAG: binsri.h [[R3]], [[R4]], 7
232 ; CHECK-DAG: lw [[R5:\$[0-9]+]], %got(llvm_mips_binsri_h_RES)(
233 ; CHECK-DAG: st.h [[R3]], 0([[R5]])
234 ; CHECK: .size llvm_mips_binsri_h_test
236 @llvm_mips_binsri_w_ARG1 = global <4 x i32> zeroinitializer, align 16
237 @llvm_mips_binsri_w_ARG2 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16
238 @llvm_mips_binsri_w_RES = global <4 x i32> zeroinitializer, align 16
240 define void @llvm_mips_binsri_w_test() nounwind {
242 %0 = load <4 x i32>* @llvm_mips_binsri_w_ARG1
243 %1 = load <4 x i32>* @llvm_mips_binsri_w_ARG2
244 %2 = tail call <4 x i32> @llvm.mips.binsri.w(<4 x i32> %0, <4 x i32> %1, i32 7)
245 store <4 x i32> %2, <4 x i32>* @llvm_mips_binsri_w_RES
249 declare <4 x i32> @llvm.mips.binsri.w(<4 x i32>, <4 x i32>, i32) nounwind
251 ; CHECK: llvm_mips_binsri_w_test:
252 ; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_binsri_w_ARG1)(
253 ; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_binsri_w_ARG2)(
254 ; CHECK-DAG: ld.w [[R3:\$w[0-9]+]], 0([[R1]])
255 ; CHECK-DAG: ld.w [[R4:\$w[0-9]+]], 0([[R2]])
256 ; CHECK-DAG: binsri.w [[R3]], [[R4]], 7
257 ; CHECK-DAG: lw [[R5:\$[0-9]+]], %got(llvm_mips_binsri_w_RES)(
258 ; CHECK-DAG: st.w [[R3]], 0([[R5]])
259 ; CHECK: .size llvm_mips_binsri_w_test
261 @llvm_mips_binsri_d_ARG1 = global <2 x i64> zeroinitializer, align 16
262 @llvm_mips_binsri_d_ARG2 = global <2 x i64> <i64 0, i64 1>, align 16
263 @llvm_mips_binsri_d_RES = global <2 x i64> zeroinitializer, align 16
265 define void @llvm_mips_binsri_d_test() nounwind {
267 %0 = load <2 x i64>* @llvm_mips_binsri_d_ARG1
268 %1 = load <2 x i64>* @llvm_mips_binsri_d_ARG2
269 %2 = tail call <2 x i64> @llvm.mips.binsri.d(<2 x i64> %0, <2 x i64> %1, i32 7)
270 store <2 x i64> %2, <2 x i64>* @llvm_mips_binsri_d_RES
274 declare <2 x i64> @llvm.mips.binsri.d(<2 x i64>, <2 x i64>, i32) nounwind
276 ; CHECK: llvm_mips_binsri_d_test:
277 ; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_binsri_d_ARG1)(
278 ; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_binsri_d_ARG2)(
279 ; CHECK-DAG: ld.d [[R3:\$w[0-9]+]], 0([[R1]])
280 ; CHECK-DAG: ld.d [[R4:\$w[0-9]+]], 0([[R2]])
281 ; CHECK-DAG: binsri.d [[R3]], [[R4]], 7
282 ; CHECK-DAG: lw [[R5:\$[0-9]+]], %got(llvm_mips_binsri_d_RES)(
283 ; CHECK-DAG: st.d [[R3]], 0([[R5]])
284 ; CHECK: .size llvm_mips_binsri_d_test
286 @llvm_mips_bnegi_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
287 @llvm_mips_bnegi_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16
289 define void @llvm_mips_bnegi_b_test() nounwind {
291 %0 = load <16 x i8>* @llvm_mips_bnegi_b_ARG1
292 %1 = tail call <16 x i8> @llvm.mips.bnegi.b(<16 x i8> %0, i32 7)
293 store <16 x i8> %1, <16 x i8>* @llvm_mips_bnegi_b_RES
297 declare <16 x i8> @llvm.mips.bnegi.b(<16 x i8>, i32) nounwind
299 ; CHECK: llvm_mips_bnegi_b_test:
303 ; CHECK: .size llvm_mips_bnegi_b_test
305 @llvm_mips_bnegi_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16
306 @llvm_mips_bnegi_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16
308 define void @llvm_mips_bnegi_h_test() nounwind {
310 %0 = load <8 x i16>* @llvm_mips_bnegi_h_ARG1
311 %1 = tail call <8 x i16> @llvm.mips.bnegi.h(<8 x i16> %0, i32 7)
312 store <8 x i16> %1, <8 x i16>* @llvm_mips_bnegi_h_RES
316 declare <8 x i16> @llvm.mips.bnegi.h(<8 x i16>, i32) nounwind
318 ; CHECK: llvm_mips_bnegi_h_test:
322 ; CHECK: .size llvm_mips_bnegi_h_test
324 @llvm_mips_bnegi_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16
325 @llvm_mips_bnegi_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16
327 define void @llvm_mips_bnegi_w_test() nounwind {
329 %0 = load <4 x i32>* @llvm_mips_bnegi_w_ARG1
330 %1 = tail call <4 x i32> @llvm.mips.bnegi.w(<4 x i32> %0, i32 7)
331 store <4 x i32> %1, <4 x i32>* @llvm_mips_bnegi_w_RES
335 declare <4 x i32> @llvm.mips.bnegi.w(<4 x i32>, i32) nounwind
337 ; CHECK: llvm_mips_bnegi_w_test:
341 ; CHECK: .size llvm_mips_bnegi_w_test
343 @llvm_mips_bnegi_d_ARG1 = global <2 x i64> <i64 0, i64 1>, align 16
344 @llvm_mips_bnegi_d_RES = global <2 x i64> <i64 0, i64 0>, align 16
346 define void @llvm_mips_bnegi_d_test() nounwind {
348 %0 = load <2 x i64>* @llvm_mips_bnegi_d_ARG1
349 %1 = tail call <2 x i64> @llvm.mips.bnegi.d(<2 x i64> %0, i32 7)
350 store <2 x i64> %1, <2 x i64>* @llvm_mips_bnegi_d_RES
354 declare <2 x i64> @llvm.mips.bnegi.d(<2 x i64>, i32) nounwind
356 ; CHECK: llvm_mips_bnegi_d_test:
360 ; CHECK: .size llvm_mips_bnegi_d_test
362 @llvm_mips_bseti_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
363 @llvm_mips_bseti_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16
365 define void @llvm_mips_bseti_b_test() nounwind {
367 %0 = load <16 x i8>* @llvm_mips_bseti_b_ARG1
368 %1 = tail call <16 x i8> @llvm.mips.bseti.b(<16 x i8> %0, i32 7)
369 store <16 x i8> %1, <16 x i8>* @llvm_mips_bseti_b_RES
373 declare <16 x i8> @llvm.mips.bseti.b(<16 x i8>, i32) nounwind
375 ; CHECK: llvm_mips_bseti_b_test:
379 ; CHECK: .size llvm_mips_bseti_b_test
381 @llvm_mips_bseti_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16
382 @llvm_mips_bseti_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16
384 define void @llvm_mips_bseti_h_test() nounwind {
386 %0 = load <8 x i16>* @llvm_mips_bseti_h_ARG1
387 %1 = tail call <8 x i16> @llvm.mips.bseti.h(<8 x i16> %0, i32 7)
388 store <8 x i16> %1, <8 x i16>* @llvm_mips_bseti_h_RES
392 declare <8 x i16> @llvm.mips.bseti.h(<8 x i16>, i32) nounwind
394 ; CHECK: llvm_mips_bseti_h_test:
398 ; CHECK: .size llvm_mips_bseti_h_test
400 @llvm_mips_bseti_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16
401 @llvm_mips_bseti_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16
403 define void @llvm_mips_bseti_w_test() nounwind {
405 %0 = load <4 x i32>* @llvm_mips_bseti_w_ARG1
406 %1 = tail call <4 x i32> @llvm.mips.bseti.w(<4 x i32> %0, i32 7)
407 store <4 x i32> %1, <4 x i32>* @llvm_mips_bseti_w_RES
411 declare <4 x i32> @llvm.mips.bseti.w(<4 x i32>, i32) nounwind
413 ; CHECK: llvm_mips_bseti_w_test:
417 ; CHECK: .size llvm_mips_bseti_w_test
419 @llvm_mips_bseti_d_ARG1 = global <2 x i64> <i64 0, i64 1>, align 16
420 @llvm_mips_bseti_d_RES = global <2 x i64> <i64 0, i64 0>, align 16
422 define void @llvm_mips_bseti_d_test() nounwind {
424 %0 = load <2 x i64>* @llvm_mips_bseti_d_ARG1
425 %1 = tail call <2 x i64> @llvm.mips.bseti.d(<2 x i64> %0, i32 7)
426 store <2 x i64> %1, <2 x i64>* @llvm_mips_bseti_d_RES
430 declare <2 x i64> @llvm.mips.bseti.d(<2 x i64>, i32) nounwind
432 ; CHECK: llvm_mips_bseti_d_test:
436 ; CHECK: .size llvm_mips_bseti_d_test