1 ; Test the MSA intrinsics that are encoded with the I5 instruction format.
2 ; There are lots of these so this covers those beginning with 'c'
4 ; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s
5 ; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | FileCheck %s
7 @llvm_mips_ceqi_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
8 @llvm_mips_ceqi_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16
10 define void @llvm_mips_ceqi_b_test() nounwind {
12 %0 = load <16 x i8>* @llvm_mips_ceqi_b_ARG1
13 %1 = tail call <16 x i8> @llvm.mips.ceqi.b(<16 x i8> %0, i32 14)
14 store <16 x i8> %1, <16 x i8>* @llvm_mips_ceqi_b_RES
18 declare <16 x i8> @llvm.mips.ceqi.b(<16 x i8>, i32) nounwind
20 ; CHECK: llvm_mips_ceqi_b_test:
24 ; CHECK: .size llvm_mips_ceqi_b_test
26 @llvm_mips_ceqi_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16
27 @llvm_mips_ceqi_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16
29 define void @llvm_mips_ceqi_h_test() nounwind {
31 %0 = load <8 x i16>* @llvm_mips_ceqi_h_ARG1
32 %1 = tail call <8 x i16> @llvm.mips.ceqi.h(<8 x i16> %0, i32 14)
33 store <8 x i16> %1, <8 x i16>* @llvm_mips_ceqi_h_RES
37 declare <8 x i16> @llvm.mips.ceqi.h(<8 x i16>, i32) nounwind
39 ; CHECK: llvm_mips_ceqi_h_test:
43 ; CHECK: .size llvm_mips_ceqi_h_test
45 @llvm_mips_ceqi_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16
46 @llvm_mips_ceqi_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16
48 define void @llvm_mips_ceqi_w_test() nounwind {
50 %0 = load <4 x i32>* @llvm_mips_ceqi_w_ARG1
51 %1 = tail call <4 x i32> @llvm.mips.ceqi.w(<4 x i32> %0, i32 14)
52 store <4 x i32> %1, <4 x i32>* @llvm_mips_ceqi_w_RES
56 declare <4 x i32> @llvm.mips.ceqi.w(<4 x i32>, i32) nounwind
58 ; CHECK: llvm_mips_ceqi_w_test:
62 ; CHECK: .size llvm_mips_ceqi_w_test
64 @llvm_mips_ceqi_d_ARG1 = global <2 x i64> <i64 0, i64 1>, align 16
65 @llvm_mips_ceqi_d_RES = global <2 x i64> <i64 0, i64 0>, align 16
67 define void @llvm_mips_ceqi_d_test() nounwind {
69 %0 = load <2 x i64>* @llvm_mips_ceqi_d_ARG1
70 %1 = tail call <2 x i64> @llvm.mips.ceqi.d(<2 x i64> %0, i32 14)
71 store <2 x i64> %1, <2 x i64>* @llvm_mips_ceqi_d_RES
75 declare <2 x i64> @llvm.mips.ceqi.d(<2 x i64>, i32) nounwind
77 ; CHECK: llvm_mips_ceqi_d_test:
81 ; CHECK: .size llvm_mips_ceqi_d_test
83 @llvm_mips_clei_s_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
84 @llvm_mips_clei_s_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16
86 define void @llvm_mips_clei_s_b_test() nounwind {
88 %0 = load <16 x i8>* @llvm_mips_clei_s_b_ARG1
89 %1 = tail call <16 x i8> @llvm.mips.clei.s.b(<16 x i8> %0, i32 14)
90 store <16 x i8> %1, <16 x i8>* @llvm_mips_clei_s_b_RES
94 declare <16 x i8> @llvm.mips.clei.s.b(<16 x i8>, i32) nounwind
96 ; CHECK: llvm_mips_clei_s_b_test:
100 ; CHECK: .size llvm_mips_clei_s_b_test
102 @llvm_mips_clei_s_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16
103 @llvm_mips_clei_s_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16
105 define void @llvm_mips_clei_s_h_test() nounwind {
107 %0 = load <8 x i16>* @llvm_mips_clei_s_h_ARG1
108 %1 = tail call <8 x i16> @llvm.mips.clei.s.h(<8 x i16> %0, i32 14)
109 store <8 x i16> %1, <8 x i16>* @llvm_mips_clei_s_h_RES
113 declare <8 x i16> @llvm.mips.clei.s.h(<8 x i16>, i32) nounwind
115 ; CHECK: llvm_mips_clei_s_h_test:
119 ; CHECK: .size llvm_mips_clei_s_h_test
121 @llvm_mips_clei_s_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16
122 @llvm_mips_clei_s_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16
124 define void @llvm_mips_clei_s_w_test() nounwind {
126 %0 = load <4 x i32>* @llvm_mips_clei_s_w_ARG1
127 %1 = tail call <4 x i32> @llvm.mips.clei.s.w(<4 x i32> %0, i32 14)
128 store <4 x i32> %1, <4 x i32>* @llvm_mips_clei_s_w_RES
132 declare <4 x i32> @llvm.mips.clei.s.w(<4 x i32>, i32) nounwind
134 ; CHECK: llvm_mips_clei_s_w_test:
138 ; CHECK: .size llvm_mips_clei_s_w_test
140 @llvm_mips_clei_s_d_ARG1 = global <2 x i64> <i64 0, i64 1>, align 16
141 @llvm_mips_clei_s_d_RES = global <2 x i64> <i64 0, i64 0>, align 16
143 define void @llvm_mips_clei_s_d_test() nounwind {
145 %0 = load <2 x i64>* @llvm_mips_clei_s_d_ARG1
146 %1 = tail call <2 x i64> @llvm.mips.clei.s.d(<2 x i64> %0, i32 14)
147 store <2 x i64> %1, <2 x i64>* @llvm_mips_clei_s_d_RES
151 declare <2 x i64> @llvm.mips.clei.s.d(<2 x i64>, i32) nounwind
153 ; CHECK: llvm_mips_clei_s_d_test:
157 ; CHECK: .size llvm_mips_clei_s_d_test
159 @llvm_mips_clei_u_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
160 @llvm_mips_clei_u_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16
162 define void @llvm_mips_clei_u_b_test() nounwind {
164 %0 = load <16 x i8>* @llvm_mips_clei_u_b_ARG1
165 %1 = tail call <16 x i8> @llvm.mips.clei.u.b(<16 x i8> %0, i32 14)
166 store <16 x i8> %1, <16 x i8>* @llvm_mips_clei_u_b_RES
170 declare <16 x i8> @llvm.mips.clei.u.b(<16 x i8>, i32) nounwind
172 ; CHECK: llvm_mips_clei_u_b_test:
176 ; CHECK: .size llvm_mips_clei_u_b_test
178 @llvm_mips_clei_u_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16
179 @llvm_mips_clei_u_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16
181 define void @llvm_mips_clei_u_h_test() nounwind {
183 %0 = load <8 x i16>* @llvm_mips_clei_u_h_ARG1
184 %1 = tail call <8 x i16> @llvm.mips.clei.u.h(<8 x i16> %0, i32 14)
185 store <8 x i16> %1, <8 x i16>* @llvm_mips_clei_u_h_RES
189 declare <8 x i16> @llvm.mips.clei.u.h(<8 x i16>, i32) nounwind
191 ; CHECK: llvm_mips_clei_u_h_test:
195 ; CHECK: .size llvm_mips_clei_u_h_test
197 @llvm_mips_clei_u_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16
198 @llvm_mips_clei_u_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16
200 define void @llvm_mips_clei_u_w_test() nounwind {
202 %0 = load <4 x i32>* @llvm_mips_clei_u_w_ARG1
203 %1 = tail call <4 x i32> @llvm.mips.clei.u.w(<4 x i32> %0, i32 14)
204 store <4 x i32> %1, <4 x i32>* @llvm_mips_clei_u_w_RES
208 declare <4 x i32> @llvm.mips.clei.u.w(<4 x i32>, i32) nounwind
210 ; CHECK: llvm_mips_clei_u_w_test:
214 ; CHECK: .size llvm_mips_clei_u_w_test
216 @llvm_mips_clei_u_d_ARG1 = global <2 x i64> <i64 0, i64 1>, align 16
217 @llvm_mips_clei_u_d_RES = global <2 x i64> <i64 0, i64 0>, align 16
219 define void @llvm_mips_clei_u_d_test() nounwind {
221 %0 = load <2 x i64>* @llvm_mips_clei_u_d_ARG1
222 %1 = tail call <2 x i64> @llvm.mips.clei.u.d(<2 x i64> %0, i32 14)
223 store <2 x i64> %1, <2 x i64>* @llvm_mips_clei_u_d_RES
227 declare <2 x i64> @llvm.mips.clei.u.d(<2 x i64>, i32) nounwind
229 ; CHECK: llvm_mips_clei_u_d_test:
233 ; CHECK: .size llvm_mips_clei_u_d_test
235 @llvm_mips_clti_s_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
236 @llvm_mips_clti_s_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16
238 define void @llvm_mips_clti_s_b_test() nounwind {
240 %0 = load <16 x i8>* @llvm_mips_clti_s_b_ARG1
241 %1 = tail call <16 x i8> @llvm.mips.clti.s.b(<16 x i8> %0, i32 14)
242 store <16 x i8> %1, <16 x i8>* @llvm_mips_clti_s_b_RES
246 declare <16 x i8> @llvm.mips.clti.s.b(<16 x i8>, i32) nounwind
248 ; CHECK: llvm_mips_clti_s_b_test:
252 ; CHECK: .size llvm_mips_clti_s_b_test
254 @llvm_mips_clti_s_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16
255 @llvm_mips_clti_s_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16
257 define void @llvm_mips_clti_s_h_test() nounwind {
259 %0 = load <8 x i16>* @llvm_mips_clti_s_h_ARG1
260 %1 = tail call <8 x i16> @llvm.mips.clti.s.h(<8 x i16> %0, i32 14)
261 store <8 x i16> %1, <8 x i16>* @llvm_mips_clti_s_h_RES
265 declare <8 x i16> @llvm.mips.clti.s.h(<8 x i16>, i32) nounwind
267 ; CHECK: llvm_mips_clti_s_h_test:
271 ; CHECK: .size llvm_mips_clti_s_h_test
273 @llvm_mips_clti_s_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16
274 @llvm_mips_clti_s_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16
276 define void @llvm_mips_clti_s_w_test() nounwind {
278 %0 = load <4 x i32>* @llvm_mips_clti_s_w_ARG1
279 %1 = tail call <4 x i32> @llvm.mips.clti.s.w(<4 x i32> %0, i32 14)
280 store <4 x i32> %1, <4 x i32>* @llvm_mips_clti_s_w_RES
284 declare <4 x i32> @llvm.mips.clti.s.w(<4 x i32>, i32) nounwind
286 ; CHECK: llvm_mips_clti_s_w_test:
290 ; CHECK: .size llvm_mips_clti_s_w_test
292 @llvm_mips_clti_s_d_ARG1 = global <2 x i64> <i64 0, i64 1>, align 16
293 @llvm_mips_clti_s_d_RES = global <2 x i64> <i64 0, i64 0>, align 16
295 define void @llvm_mips_clti_s_d_test() nounwind {
297 %0 = load <2 x i64>* @llvm_mips_clti_s_d_ARG1
298 %1 = tail call <2 x i64> @llvm.mips.clti.s.d(<2 x i64> %0, i32 14)
299 store <2 x i64> %1, <2 x i64>* @llvm_mips_clti_s_d_RES
303 declare <2 x i64> @llvm.mips.clti.s.d(<2 x i64>, i32) nounwind
305 ; CHECK: llvm_mips_clti_s_d_test:
309 ; CHECK: .size llvm_mips_clti_s_d_test
311 @llvm_mips_clti_u_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
312 @llvm_mips_clti_u_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16
314 define void @llvm_mips_clti_u_b_test() nounwind {
316 %0 = load <16 x i8>* @llvm_mips_clti_u_b_ARG1
317 %1 = tail call <16 x i8> @llvm.mips.clti.u.b(<16 x i8> %0, i32 14)
318 store <16 x i8> %1, <16 x i8>* @llvm_mips_clti_u_b_RES
322 declare <16 x i8> @llvm.mips.clti.u.b(<16 x i8>, i32) nounwind
324 ; CHECK: llvm_mips_clti_u_b_test:
328 ; CHECK: .size llvm_mips_clti_u_b_test
330 @llvm_mips_clti_u_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16
331 @llvm_mips_clti_u_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16
333 define void @llvm_mips_clti_u_h_test() nounwind {
335 %0 = load <8 x i16>* @llvm_mips_clti_u_h_ARG1
336 %1 = tail call <8 x i16> @llvm.mips.clti.u.h(<8 x i16> %0, i32 14)
337 store <8 x i16> %1, <8 x i16>* @llvm_mips_clti_u_h_RES
341 declare <8 x i16> @llvm.mips.clti.u.h(<8 x i16>, i32) nounwind
343 ; CHECK: llvm_mips_clti_u_h_test:
347 ; CHECK: .size llvm_mips_clti_u_h_test
349 @llvm_mips_clti_u_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16
350 @llvm_mips_clti_u_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16
352 define void @llvm_mips_clti_u_w_test() nounwind {
354 %0 = load <4 x i32>* @llvm_mips_clti_u_w_ARG1
355 %1 = tail call <4 x i32> @llvm.mips.clti.u.w(<4 x i32> %0, i32 14)
356 store <4 x i32> %1, <4 x i32>* @llvm_mips_clti_u_w_RES
360 declare <4 x i32> @llvm.mips.clti.u.w(<4 x i32>, i32) nounwind
362 ; CHECK: llvm_mips_clti_u_w_test:
366 ; CHECK: .size llvm_mips_clti_u_w_test
368 @llvm_mips_clti_u_d_ARG1 = global <2 x i64> <i64 0, i64 1>, align 16
369 @llvm_mips_clti_u_d_RES = global <2 x i64> <i64 0, i64 0>, align 16
371 define void @llvm_mips_clti_u_d_test() nounwind {
373 %0 = load <2 x i64>* @llvm_mips_clti_u_d_ARG1
374 %1 = tail call <2 x i64> @llvm.mips.clti.u.d(<2 x i64> %0, i32 14)
375 store <2 x i64> %1, <2 x i64>* @llvm_mips_clti_u_d_RES
379 declare <2 x i64> @llvm.mips.clti.u.d(<2 x i64>, i32) nounwind
381 ; CHECK: llvm_mips_clti_u_d_test:
385 ; CHECK: .size llvm_mips_clti_u_d_test