1 ; Test the MSA intrinsics that are encoded with the I5 instruction format.
2 ; There are lots of these so this covers those beginning with 'm'
4 ; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s
6 @llvm_mips_maxi_s_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
7 @llvm_mips_maxi_s_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16
9 define void @llvm_mips_maxi_s_b_test() nounwind {
11 %0 = load <16 x i8>* @llvm_mips_maxi_s_b_ARG1
12 %1 = tail call <16 x i8> @llvm.mips.maxi.s.b(<16 x i8> %0, i32 14)
13 store <16 x i8> %1, <16 x i8>* @llvm_mips_maxi_s_b_RES
17 declare <16 x i8> @llvm.mips.maxi.s.b(<16 x i8>, i32) nounwind
19 ; CHECK: llvm_mips_maxi_s_b_test:
23 ; CHECK: .size llvm_mips_maxi_s_b_test
25 @llvm_mips_maxi_s_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16
26 @llvm_mips_maxi_s_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16
28 define void @llvm_mips_maxi_s_h_test() nounwind {
30 %0 = load <8 x i16>* @llvm_mips_maxi_s_h_ARG1
31 %1 = tail call <8 x i16> @llvm.mips.maxi.s.h(<8 x i16> %0, i32 14)
32 store <8 x i16> %1, <8 x i16>* @llvm_mips_maxi_s_h_RES
36 declare <8 x i16> @llvm.mips.maxi.s.h(<8 x i16>, i32) nounwind
38 ; CHECK: llvm_mips_maxi_s_h_test:
42 ; CHECK: .size llvm_mips_maxi_s_h_test
44 @llvm_mips_maxi_s_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16
45 @llvm_mips_maxi_s_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16
47 define void @llvm_mips_maxi_s_w_test() nounwind {
49 %0 = load <4 x i32>* @llvm_mips_maxi_s_w_ARG1
50 %1 = tail call <4 x i32> @llvm.mips.maxi.s.w(<4 x i32> %0, i32 14)
51 store <4 x i32> %1, <4 x i32>* @llvm_mips_maxi_s_w_RES
55 declare <4 x i32> @llvm.mips.maxi.s.w(<4 x i32>, i32) nounwind
57 ; CHECK: llvm_mips_maxi_s_w_test:
61 ; CHECK: .size llvm_mips_maxi_s_w_test
63 @llvm_mips_maxi_s_d_ARG1 = global <2 x i64> <i64 0, i64 1>, align 16
64 @llvm_mips_maxi_s_d_RES = global <2 x i64> <i64 0, i64 0>, align 16
66 define void @llvm_mips_maxi_s_d_test() nounwind {
68 %0 = load <2 x i64>* @llvm_mips_maxi_s_d_ARG1
69 %1 = tail call <2 x i64> @llvm.mips.maxi.s.d(<2 x i64> %0, i32 14)
70 store <2 x i64> %1, <2 x i64>* @llvm_mips_maxi_s_d_RES
74 declare <2 x i64> @llvm.mips.maxi.s.d(<2 x i64>, i32) nounwind
76 ; CHECK: llvm_mips_maxi_s_d_test:
80 ; CHECK: .size llvm_mips_maxi_s_d_test
82 @llvm_mips_maxi_u_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
83 @llvm_mips_maxi_u_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16
85 define void @llvm_mips_maxi_u_b_test() nounwind {
87 %0 = load <16 x i8>* @llvm_mips_maxi_u_b_ARG1
88 %1 = tail call <16 x i8> @llvm.mips.maxi.u.b(<16 x i8> %0, i32 14)
89 store <16 x i8> %1, <16 x i8>* @llvm_mips_maxi_u_b_RES
93 declare <16 x i8> @llvm.mips.maxi.u.b(<16 x i8>, i32) nounwind
95 ; CHECK: llvm_mips_maxi_u_b_test:
99 ; CHECK: .size llvm_mips_maxi_u_b_test
101 @llvm_mips_maxi_u_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16
102 @llvm_mips_maxi_u_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16
104 define void @llvm_mips_maxi_u_h_test() nounwind {
106 %0 = load <8 x i16>* @llvm_mips_maxi_u_h_ARG1
107 %1 = tail call <8 x i16> @llvm.mips.maxi.u.h(<8 x i16> %0, i32 14)
108 store <8 x i16> %1, <8 x i16>* @llvm_mips_maxi_u_h_RES
112 declare <8 x i16> @llvm.mips.maxi.u.h(<8 x i16>, i32) nounwind
114 ; CHECK: llvm_mips_maxi_u_h_test:
118 ; CHECK: .size llvm_mips_maxi_u_h_test
120 @llvm_mips_maxi_u_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16
121 @llvm_mips_maxi_u_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16
123 define void @llvm_mips_maxi_u_w_test() nounwind {
125 %0 = load <4 x i32>* @llvm_mips_maxi_u_w_ARG1
126 %1 = tail call <4 x i32> @llvm.mips.maxi.u.w(<4 x i32> %0, i32 14)
127 store <4 x i32> %1, <4 x i32>* @llvm_mips_maxi_u_w_RES
131 declare <4 x i32> @llvm.mips.maxi.u.w(<4 x i32>, i32) nounwind
133 ; CHECK: llvm_mips_maxi_u_w_test:
137 ; CHECK: .size llvm_mips_maxi_u_w_test
139 @llvm_mips_maxi_u_d_ARG1 = global <2 x i64> <i64 0, i64 1>, align 16
140 @llvm_mips_maxi_u_d_RES = global <2 x i64> <i64 0, i64 0>, align 16
142 define void @llvm_mips_maxi_u_d_test() nounwind {
144 %0 = load <2 x i64>* @llvm_mips_maxi_u_d_ARG1
145 %1 = tail call <2 x i64> @llvm.mips.maxi.u.d(<2 x i64> %0, i32 14)
146 store <2 x i64> %1, <2 x i64>* @llvm_mips_maxi_u_d_RES
150 declare <2 x i64> @llvm.mips.maxi.u.d(<2 x i64>, i32) nounwind
152 ; CHECK: llvm_mips_maxi_u_d_test:
156 ; CHECK: .size llvm_mips_maxi_u_d_test
158 @llvm_mips_mini_s_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
159 @llvm_mips_mini_s_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16
161 define void @llvm_mips_mini_s_b_test() nounwind {
163 %0 = load <16 x i8>* @llvm_mips_mini_s_b_ARG1
164 %1 = tail call <16 x i8> @llvm.mips.mini.s.b(<16 x i8> %0, i32 14)
165 store <16 x i8> %1, <16 x i8>* @llvm_mips_mini_s_b_RES
169 declare <16 x i8> @llvm.mips.mini.s.b(<16 x i8>, i32) nounwind
171 ; CHECK: llvm_mips_mini_s_b_test:
175 ; CHECK: .size llvm_mips_mini_s_b_test
177 @llvm_mips_mini_s_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16
178 @llvm_mips_mini_s_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16
180 define void @llvm_mips_mini_s_h_test() nounwind {
182 %0 = load <8 x i16>* @llvm_mips_mini_s_h_ARG1
183 %1 = tail call <8 x i16> @llvm.mips.mini.s.h(<8 x i16> %0, i32 14)
184 store <8 x i16> %1, <8 x i16>* @llvm_mips_mini_s_h_RES
188 declare <8 x i16> @llvm.mips.mini.s.h(<8 x i16>, i32) nounwind
190 ; CHECK: llvm_mips_mini_s_h_test:
194 ; CHECK: .size llvm_mips_mini_s_h_test
196 @llvm_mips_mini_s_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16
197 @llvm_mips_mini_s_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16
199 define void @llvm_mips_mini_s_w_test() nounwind {
201 %0 = load <4 x i32>* @llvm_mips_mini_s_w_ARG1
202 %1 = tail call <4 x i32> @llvm.mips.mini.s.w(<4 x i32> %0, i32 14)
203 store <4 x i32> %1, <4 x i32>* @llvm_mips_mini_s_w_RES
207 declare <4 x i32> @llvm.mips.mini.s.w(<4 x i32>, i32) nounwind
209 ; CHECK: llvm_mips_mini_s_w_test:
213 ; CHECK: .size llvm_mips_mini_s_w_test
215 @llvm_mips_mini_s_d_ARG1 = global <2 x i64> <i64 0, i64 1>, align 16
216 @llvm_mips_mini_s_d_RES = global <2 x i64> <i64 0, i64 0>, align 16
218 define void @llvm_mips_mini_s_d_test() nounwind {
220 %0 = load <2 x i64>* @llvm_mips_mini_s_d_ARG1
221 %1 = tail call <2 x i64> @llvm.mips.mini.s.d(<2 x i64> %0, i32 14)
222 store <2 x i64> %1, <2 x i64>* @llvm_mips_mini_s_d_RES
226 declare <2 x i64> @llvm.mips.mini.s.d(<2 x i64>, i32) nounwind
228 ; CHECK: llvm_mips_mini_s_d_test:
232 ; CHECK: .size llvm_mips_mini_s_d_test
234 @llvm_mips_mini_u_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
235 @llvm_mips_mini_u_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16
237 define void @llvm_mips_mini_u_b_test() nounwind {
239 %0 = load <16 x i8>* @llvm_mips_mini_u_b_ARG1
240 %1 = tail call <16 x i8> @llvm.mips.mini.u.b(<16 x i8> %0, i32 14)
241 store <16 x i8> %1, <16 x i8>* @llvm_mips_mini_u_b_RES
245 declare <16 x i8> @llvm.mips.mini.u.b(<16 x i8>, i32) nounwind
247 ; CHECK: llvm_mips_mini_u_b_test:
251 ; CHECK: .size llvm_mips_mini_u_b_test
253 @llvm_mips_mini_u_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16
254 @llvm_mips_mini_u_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16
256 define void @llvm_mips_mini_u_h_test() nounwind {
258 %0 = load <8 x i16>* @llvm_mips_mini_u_h_ARG1
259 %1 = tail call <8 x i16> @llvm.mips.mini.u.h(<8 x i16> %0, i32 14)
260 store <8 x i16> %1, <8 x i16>* @llvm_mips_mini_u_h_RES
264 declare <8 x i16> @llvm.mips.mini.u.h(<8 x i16>, i32) nounwind
266 ; CHECK: llvm_mips_mini_u_h_test:
270 ; CHECK: .size llvm_mips_mini_u_h_test
272 @llvm_mips_mini_u_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16
273 @llvm_mips_mini_u_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16
275 define void @llvm_mips_mini_u_w_test() nounwind {
277 %0 = load <4 x i32>* @llvm_mips_mini_u_w_ARG1
278 %1 = tail call <4 x i32> @llvm.mips.mini.u.w(<4 x i32> %0, i32 14)
279 store <4 x i32> %1, <4 x i32>* @llvm_mips_mini_u_w_RES
283 declare <4 x i32> @llvm.mips.mini.u.w(<4 x i32>, i32) nounwind
285 ; CHECK: llvm_mips_mini_u_w_test:
289 ; CHECK: .size llvm_mips_mini_u_w_test
291 @llvm_mips_mini_u_d_ARG1 = global <2 x i64> <i64 0, i64 1>, align 16
292 @llvm_mips_mini_u_d_RES = global <2 x i64> <i64 0, i64 0>, align 16
294 define void @llvm_mips_mini_u_d_test() nounwind {
296 %0 = load <2 x i64>* @llvm_mips_mini_u_d_ARG1
297 %1 = tail call <2 x i64> @llvm.mips.mini.u.d(<2 x i64> %0, i32 14)
298 store <2 x i64> %1, <2 x i64>* @llvm_mips_mini_u_d_RES
302 declare <2 x i64> @llvm.mips.mini.u.d(<2 x i64>, i32) nounwind
304 ; CHECK: llvm_mips_mini_u_d_test:
308 ; CHECK: .size llvm_mips_mini_u_d_test