1 ; Test the MSA intrinsics that are encoded with the I5 instruction format and
4 ; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s
5 ; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | FileCheck %s
7 @llvm_mips_ld_b_ARG = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
8 @llvm_mips_ld_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16
10 define void @llvm_mips_ld_b_test() nounwind {
12 %0 = bitcast <16 x i8>* @llvm_mips_ld_b_ARG to i8*
13 %1 = tail call <16 x i8> @llvm.mips.ld.b(i8* %0, i32 16)
14 store <16 x i8> %1, <16 x i8>* @llvm_mips_ld_b_RES
18 declare <16 x i8> @llvm.mips.ld.b(i8*, i32) nounwind
20 ; CHECK: llvm_mips_ld_b_test:
21 ; CHECK: ld.b [[R1:\$w[0-9]+]], 16(
23 ; CHECK: .size llvm_mips_ld_b_test
25 @llvm_mips_ld_h_ARG = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16
26 @llvm_mips_ld_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16
28 define void @llvm_mips_ld_h_test() nounwind {
30 %0 = bitcast <8 x i16>* @llvm_mips_ld_h_ARG to i8*
31 %1 = tail call <8 x i16> @llvm.mips.ld.h(i8* %0, i32 16)
32 store <8 x i16> %1, <8 x i16>* @llvm_mips_ld_h_RES
36 declare <8 x i16> @llvm.mips.ld.h(i8*, i32) nounwind
38 ; CHECK: llvm_mips_ld_h_test:
39 ; CHECK: ld.h [[R1:\$w[0-9]+]], 16(
41 ; CHECK: .size llvm_mips_ld_h_test
43 @llvm_mips_ld_w_ARG = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16
44 @llvm_mips_ld_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16
46 define void @llvm_mips_ld_w_test() nounwind {
48 %0 = bitcast <4 x i32>* @llvm_mips_ld_w_ARG to i8*
49 %1 = tail call <4 x i32> @llvm.mips.ld.w(i8* %0, i32 16)
50 store <4 x i32> %1, <4 x i32>* @llvm_mips_ld_w_RES
54 declare <4 x i32> @llvm.mips.ld.w(i8*, i32) nounwind
56 ; CHECK: llvm_mips_ld_w_test:
57 ; CHECK: ld.w [[R1:\$w[0-9]+]], 16(
59 ; CHECK: .size llvm_mips_ld_w_test
61 @llvm_mips_ld_d_ARG = global <2 x i64> <i64 0, i64 1>, align 16
62 @llvm_mips_ld_d_RES = global <2 x i64> <i64 0, i64 0>, align 16
64 define void @llvm_mips_ld_d_test() nounwind {
66 %0 = bitcast <2 x i64>* @llvm_mips_ld_d_ARG to i8*
67 %1 = tail call <2 x i64> @llvm.mips.ld.d(i8* %0, i32 16)
68 store <2 x i64> %1, <2 x i64>* @llvm_mips_ld_d_RES
72 declare <2 x i64> @llvm.mips.ld.d(i8*, i32) nounwind
74 ; CHECK: llvm_mips_ld_d_test:
75 ; CHECK: ld.d [[R1:\$w[0-9]+]], 16(
77 ; CHECK: .size llvm_mips_ld_d_test
79 @llvm_mips_st_b_ARG = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
80 @llvm_mips_st_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16
82 define void @llvm_mips_st_b_test() nounwind {
84 %0 = load <16 x i8>* @llvm_mips_st_b_ARG
85 %1 = bitcast <16 x i8>* @llvm_mips_st_b_RES to i8*
86 tail call void @llvm.mips.st.b(<16 x i8> %0, i8* %1, i32 16)
90 declare void @llvm.mips.st.b(<16 x i8>, i8*, i32) nounwind
92 ; CHECK: llvm_mips_st_b_test:
94 ; CHECK: st.b [[R1:\$w[0-9]+]], 16(
95 ; CHECK: .size llvm_mips_st_b_test
97 @llvm_mips_st_h_ARG = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16
98 @llvm_mips_st_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16
100 define void @llvm_mips_st_h_test() nounwind {
102 %0 = load <8 x i16>* @llvm_mips_st_h_ARG
103 %1 = bitcast <8 x i16>* @llvm_mips_st_h_RES to i8*
104 tail call void @llvm.mips.st.h(<8 x i16> %0, i8* %1, i32 16)
108 declare void @llvm.mips.st.h(<8 x i16>, i8*, i32) nounwind
110 ; CHECK: llvm_mips_st_h_test:
112 ; CHECK: st.h [[R1:\$w[0-9]+]], 16(
113 ; CHECK: .size llvm_mips_st_h_test
115 @llvm_mips_st_w_ARG = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16
116 @llvm_mips_st_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16
118 define void @llvm_mips_st_w_test() nounwind {
120 %0 = load <4 x i32>* @llvm_mips_st_w_ARG
121 %1 = bitcast <4 x i32>* @llvm_mips_st_w_RES to i8*
122 tail call void @llvm.mips.st.w(<4 x i32> %0, i8* %1, i32 16)
126 declare void @llvm.mips.st.w(<4 x i32>, i8*, i32) nounwind
128 ; CHECK: llvm_mips_st_w_test:
130 ; CHECK: st.w [[R1:\$w[0-9]+]], 16(
131 ; CHECK: .size llvm_mips_st_w_test
133 @llvm_mips_st_d_ARG = global <2 x i64> <i64 0, i64 1>, align 16
134 @llvm_mips_st_d_RES = global <2 x i64> <i64 0, i64 0>, align 16
136 define void @llvm_mips_st_d_test() nounwind {
138 %0 = load <2 x i64>* @llvm_mips_st_d_ARG
139 %1 = bitcast <2 x i64>* @llvm_mips_st_d_RES to i8*
140 tail call void @llvm.mips.st.d(<2 x i64> %0, i8* %1, i32 16)
144 declare void @llvm.mips.st.d(<2 x i64>, i8*, i32) nounwind
146 ; CHECK: llvm_mips_st_d_test:
148 ; CHECK: st.d [[R1:\$w[0-9]+]], 16(
149 ; CHECK: .size llvm_mips_st_d_test