1 ; Test the MSA intrinsics that are encoded with the I8 instruction format.
3 ; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s
5 @llvm_mips_andi_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
6 @llvm_mips_andi_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16
8 define void @llvm_mips_andi_b_test() nounwind {
10 %0 = load <16 x i8>* @llvm_mips_andi_b_ARG1
11 %1 = tail call <16 x i8> @llvm.mips.andi.b(<16 x i8> %0, i32 25)
12 store <16 x i8> %1, <16 x i8>* @llvm_mips_andi_b_RES
16 declare <16 x i8> @llvm.mips.andi.b(<16 x i8>, i32) nounwind
18 ; CHECK: llvm_mips_andi_b_test:
22 ; CHECK: .size llvm_mips_andi_b_test
24 @llvm_mips_bmnzi_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
25 @llvm_mips_bmnzi_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16
27 define void @llvm_mips_bmnzi_b_test() nounwind {
29 %0 = load <16 x i8>* @llvm_mips_bmnzi_b_ARG1
30 %1 = tail call <16 x i8> @llvm.mips.bmnzi.b(<16 x i8> %0, i32 25)
31 store <16 x i8> %1, <16 x i8>* @llvm_mips_bmnzi_b_RES
35 declare <16 x i8> @llvm.mips.bmnzi.b(<16 x i8>, i32) nounwind
37 ; CHECK: llvm_mips_bmnzi_b_test:
41 ; CHECK: .size llvm_mips_bmnzi_b_test
43 @llvm_mips_bmzi_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
44 @llvm_mips_bmzi_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16
46 define void @llvm_mips_bmzi_b_test() nounwind {
48 %0 = load <16 x i8>* @llvm_mips_bmzi_b_ARG1
49 %1 = tail call <16 x i8> @llvm.mips.bmzi.b(<16 x i8> %0, i32 25)
50 store <16 x i8> %1, <16 x i8>* @llvm_mips_bmzi_b_RES
54 declare <16 x i8> @llvm.mips.bmzi.b(<16 x i8>, i32) nounwind
56 ; CHECK: llvm_mips_bmzi_b_test:
60 ; CHECK: .size llvm_mips_bmzi_b_test
62 @llvm_mips_bseli_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
63 @llvm_mips_bseli_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16
65 define void @llvm_mips_bseli_b_test() nounwind {
67 %0 = load <16 x i8>* @llvm_mips_bseli_b_ARG1
68 %1 = tail call <16 x i8> @llvm.mips.bseli.b(<16 x i8> %0, <16 x i8> %0, i32 25)
69 store <16 x i8> %1, <16 x i8>* @llvm_mips_bseli_b_RES
73 declare <16 x i8> @llvm.mips.bseli.b(<16 x i8>, <16 x i8>, i32) nounwind
75 ; CHECK: llvm_mips_bseli_b_test:
79 ; CHECK: .size llvm_mips_bseli_b_test
81 @llvm_mips_nori_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
82 @llvm_mips_nori_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16
84 define void @llvm_mips_nori_b_test() nounwind {
86 %0 = load <16 x i8>* @llvm_mips_nori_b_ARG1
87 %1 = tail call <16 x i8> @llvm.mips.nori.b(<16 x i8> %0, i32 25)
88 store <16 x i8> %1, <16 x i8>* @llvm_mips_nori_b_RES
92 declare <16 x i8> @llvm.mips.nori.b(<16 x i8>, i32) nounwind
94 ; CHECK: llvm_mips_nori_b_test:
98 ; CHECK: .size llvm_mips_nori_b_test
100 @llvm_mips_ori_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
101 @llvm_mips_ori_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16
103 define void @llvm_mips_ori_b_test() nounwind {
105 %0 = load <16 x i8>* @llvm_mips_ori_b_ARG1
106 %1 = tail call <16 x i8> @llvm.mips.ori.b(<16 x i8> %0, i32 25)
107 store <16 x i8> %1, <16 x i8>* @llvm_mips_ori_b_RES
111 declare <16 x i8> @llvm.mips.ori.b(<16 x i8>, i32) nounwind
113 ; CHECK: llvm_mips_ori_b_test:
117 ; CHECK: .size llvm_mips_ori_b_test
119 @llvm_mips_shf_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
120 @llvm_mips_shf_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16
122 define void @llvm_mips_shf_b_test() nounwind {
124 %0 = load <16 x i8>* @llvm_mips_shf_b_ARG1
125 %1 = tail call <16 x i8> @llvm.mips.shf.b(<16 x i8> %0, i32 25)
126 store <16 x i8> %1, <16 x i8>* @llvm_mips_shf_b_RES
130 declare <16 x i8> @llvm.mips.shf.b(<16 x i8>, i32) nounwind
132 ; CHECK: llvm_mips_shf_b_test:
136 ; CHECK: .size llvm_mips_shf_b_test
138 @llvm_mips_shf_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16
139 @llvm_mips_shf_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16
141 define void @llvm_mips_shf_h_test() nounwind {
143 %0 = load <8 x i16>* @llvm_mips_shf_h_ARG1
144 %1 = tail call <8 x i16> @llvm.mips.shf.h(<8 x i16> %0, i32 25)
145 store <8 x i16> %1, <8 x i16>* @llvm_mips_shf_h_RES
149 declare <8 x i16> @llvm.mips.shf.h(<8 x i16>, i32) nounwind
151 ; CHECK: llvm_mips_shf_h_test:
155 ; CHECK: .size llvm_mips_shf_h_test
157 @llvm_mips_shf_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16
158 @llvm_mips_shf_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16
160 define void @llvm_mips_shf_w_test() nounwind {
162 %0 = load <4 x i32>* @llvm_mips_shf_w_ARG1
163 %1 = tail call <4 x i32> @llvm.mips.shf.w(<4 x i32> %0, i32 25)
164 store <4 x i32> %1, <4 x i32>* @llvm_mips_shf_w_RES
168 declare <4 x i32> @llvm.mips.shf.w(<4 x i32>, i32) nounwind
170 ; CHECK: llvm_mips_shf_w_test:
174 ; CHECK: .size llvm_mips_shf_w_test
176 @llvm_mips_xori_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
177 @llvm_mips_xori_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16
179 define void @llvm_mips_xori_b_test() nounwind {
181 %0 = load <16 x i8>* @llvm_mips_xori_b_ARG1
182 %1 = tail call <16 x i8> @llvm.mips.xori.b(<16 x i8> %0, i32 25)
183 store <16 x i8> %1, <16 x i8>* @llvm_mips_xori_b_RES
187 declare <16 x i8> @llvm.mips.xori.b(<16 x i8>, i32) nounwind
189 ; CHECK: llvm_mips_xori_b_test:
193 ; CHECK: .size llvm_mips_xori_b_test