1 ; Test the MSA intrinsics that are encoded with the VECS10 instruction format.
3 ; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s
5 @llvm_mips_bnz_v_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
7 define i32 @llvm_mips_bnz_v_test() nounwind {
9 %0 = load <16 x i8>* @llvm_mips_bnz_v_ARG1
10 %1 = tail call i32 @llvm.mips.bnz.v(<16 x i8> %0)
11 %2 = icmp eq i32 %1, 0
12 br i1 %2, label %true, label %false
19 declare i32 @llvm.mips.bnz.v(<16 x i8>) nounwind
21 ; CHECK: llvm_mips_bnz_v_test:
22 ; CHECK-DAG: ld.b [[R0:\$w[0-9]+]]
23 ; CHECK-DAG: bnz.v [[R0]]
24 ; CHECK: .size llvm_mips_bnz_v_test
26 @llvm_mips_bz_v_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
28 define i32 @llvm_mips_bz_v_test() nounwind {
30 %0 = load <16 x i8>* @llvm_mips_bz_v_ARG1
31 %1 = tail call i32 @llvm.mips.bz.v(<16 x i8> %0)
32 %2 = icmp eq i32 %1, 0
33 br i1 %2, label %true, label %false
40 declare i32 @llvm.mips.bz.v(<16 x i8>) nounwind
42 ; CHECK: llvm_mips_bz_v_test:
43 ; CHECK-DAG: ld.b [[R0:\$w[0-9]+]]
44 ; CHECK-DAG: bz.v [[R0]]
45 ; CHECK: .size llvm_mips_bz_v_test