1 ; RUN: llc < %s -march=mipsel -mcpu=mips32 | FileCheck %s -check-prefix=ALL -check-prefix=32
2 ; RUN: llc < %s -march=mipsel -mcpu=mips32r2 | FileCheck %s -check-prefix=ALL -check-prefix=32R2
3 ; RUN: llc < %s -march=mipsel -mcpu=mips32r6 | FileCheck %s -check-prefix=ALL -check-prefix=32R6
4 ; RUN: llc < %s -march=mips64el -mcpu=mips64 | FileCheck %s -check-prefix=ALL -check-prefix=64
5 ; RUN: llc < %s -march=mips64el -mcpu=mips64r2 | FileCheck %s -check-prefix=ALL -check-prefix=64R2
6 ; RUN: llc < %s -march=mips64el -mcpu=mips64r6 | FileCheck %s -check-prefix=ALL -check-prefix=64R6
8 @d2 = external global double
9 @d3 = external global double
11 define i32 @i32_icmp_ne_i32_val(i32 %s, i32 %f0, i32 %f1) nounwind readnone {
13 ; ALL-LABEL: i32_icmp_ne_i32_val:
18 ; 32R2: movn $5, $6, $4
21 ; 32R6-DAG: selnez $[[T0:[0-9]+]], $5, $4
22 ; 32R6-DAG: seleqz $[[T1:[0-9]+]], $6, $4
23 ; 32R6: or $2, $[[T0]], $[[T1]]
28 ; 64R2: movn $5, $6, $4
31 ; 64R6-DAG: selnez $[[T0:[0-9]+]], $5, $4
32 ; 64R6-DAG: seleqz $[[T1:[0-9]+]], $6, $4
33 ; 64R6: or $2, $[[T0]], $[[T1]]
35 %tobool = icmp ne i32 %s, 0
36 %cond = select i1 %tobool, i32 %f1, i32 %f0
40 define i64 @i32_icmp_ne_i64_val(i32 %s, i64 %f0, i64 %f1) nounwind readnone {
42 ; ALL-LABEL: i32_icmp_ne_i64_val:
44 ; 32-DAG: lw $[[F1:[0-9]+]], 16($sp)
45 ; 32-DAG: movn $6, $[[F1]], $4
46 ; 32-DAG: lw $[[F1H:[0-9]+]], 20($sp)
47 ; 32: movn $7, $[[F1H]], $4
51 ; 32R2-DAG: lw $[[F1:[0-9]+]], 16($sp)
52 ; 32R2-DAG: movn $6, $[[F1]], $4
53 ; 32R2-DAG: lw $[[F1H:[0-9]+]], 20($sp)
54 ; 32R2: movn $7, $[[F1H]], $4
58 ; 32R6-DAG: lw $[[F1:[0-9]+]], 16($sp)
59 ; 32R6-DAG: selnez $[[T0:[0-9]+]], $6, $4
60 ; 32R6-DAG: seleqz $[[T1:[0-9]+]], $[[F1]], $4
61 ; 32R6: or $2, $[[T0]], $[[T1]]
62 ; 32R6-DAG: lw $[[F1H:[0-9]+]], 20($sp)
63 ; 32R6-DAG: selnez $[[T0:[0-9]+]], $7, $4
64 ; 32R6-DAG: seleqz $[[T1:[0-9]+]], $[[F1H]], $4
65 ; 32R6: or $3, $[[T0]], $[[T1]]
70 ; 64R2: movn $5, $6, $4
73 ; FIXME: This sll works around an implementation detail in the code generator
74 ; (setcc's result is i32 so bits 32-63 are undefined). It's not really
76 ; 64R6-DAG: sll $[[CC:[0-9]+]], $4, 0
77 ; 64R6-DAG: selnez $[[T0:[0-9]+]], $5, $[[CC]]
78 ; 64R6-DAG: seleqz $[[T1:[0-9]+]], $6, $[[CC]]
79 ; 64R6: or $2, $[[T0]], $[[T1]]
81 %tobool = icmp ne i32 %s, 0
82 %cond = select i1 %tobool, i64 %f1, i64 %f0
86 define i64 @i64_icmp_ne_i64_val(i64 %s, i64 %f0, i64 %f1) nounwind readnone {
88 ; ALL-LABEL: i64_icmp_ne_i64_val:
90 ; 32-DAG: or $[[CC:[0-9]+]], $4
91 ; 32-DAG: lw $[[F1:[0-9]+]], 16($sp)
92 ; 32-DAG: movn $6, $[[F1]], $[[CC]]
93 ; 32-DAG: lw $[[F1H:[0-9]+]], 20($sp)
94 ; 32: movn $7, $[[F1H]], $[[CC]]
98 ; 32R2-DAG: or $[[CC:[0-9]+]], $4
99 ; 32R2-DAG: lw $[[F1:[0-9]+]], 16($sp)
100 ; 32R2-DAG: movn $6, $[[F1]], $[[CC]]
101 ; 32R2-DAG: lw $[[F1H:[0-9]+]], 20($sp)
102 ; 32R2: movn $7, $[[F1H]], $[[CC]]
106 ; 32R6-DAG: lw $[[F1:[0-9]+]], 16($sp)
107 ; 32R6-DAG: or $[[T2:[0-9]+]], $4, $5
108 ; 32R6-DAG: selnez $[[T0:[0-9]+]], $6, $[[T2]]
109 ; 32R6-DAG: seleqz $[[T1:[0-9]+]], $[[F1]], $[[T2]]
110 ; 32R6: or $2, $[[T0]], $[[T1]]
111 ; 32R6-DAG: lw $[[F1H:[0-9]+]], 20($sp)
112 ; 32R6-DAG: selnez $[[T0:[0-9]+]], $7, $[[T2]]
113 ; 32R6-DAG: seleqz $[[T1:[0-9]+]], $[[F1H]], $[[T2]]
114 ; 32R6: or $3, $[[T0]], $[[T1]]
116 ; 64: movn $5, $6, $4
119 ; 64R2: movn $5, $6, $4
122 ; 64R6-DAG: selnez $[[T0:[0-9]+]], $5, $4
123 ; 64R6-DAG: seleqz $[[T1:[0-9]+]], $6, $4
124 ; 64R6: or $2, $[[T0]], $[[T1]]
126 %tobool = icmp ne i64 %s, 0
127 %cond = select i1 %tobool, i64 %f1, i64 %f0
131 define float @i32_icmp_ne_f32_val(i32 %s, float %f0, float %f1) nounwind readnone {
133 ; ALL-LABEL: i32_icmp_ne_f32_val:
135 ; 32-DAG: mtc1 $5, $[[F0:f[0-9]+]]
136 ; 32-DAG: mtc1 $6, $[[F1:f0]]
137 ; 32: movn.s $[[F1]], $[[F0]], $4
139 ; 32R2-DAG: mtc1 $5, $[[F0:f[0-9]+]]
140 ; 32R2-DAG: mtc1 $6, $[[F1:f0]]
141 ; 32R2: movn.s $[[F1]], $[[F0]], $4
143 ; 32R6-DAG: mtc1 $5, $[[F0:f[0-9]+]]
144 ; 32R6-DAG: mtc1 $6, $[[F1:f[0-9]+]]
145 ; 32R6: sltu $[[T0:[0-9]+]], $zero, $4
146 ; 32R6: mtc1 $[[T0]], $[[CC:f0]]
147 ; 32R6: sel.s $[[CC]], $[[F1]], $[[F0]]
149 ; 64: movn.s $f14, $f13, $4
150 ; 64: mov.s $f0, $f14
152 ; 64R2: movn.s $f14, $f13, $4
153 ; 64R2: mov.s $f0, $f14
155 ; 64R6: sltu $[[T0:[0-9]+]], $zero, $4
156 ; 64R6: mtc1 $[[T0]], $[[CC:f0]]
157 ; 64R6: sel.s $[[CC]], $f14, $f13
159 %tobool = icmp ne i32 %s, 0
160 %cond = select i1 %tobool, float %f0, float %f1
164 define double @i32_icmp_ne_f64_val(i32 %s, double %f0, double %f1) nounwind readnone {
166 ; ALL-LABEL: i32_icmp_ne_f64_val:
168 ; 32-DAG: mtc1 $6, $[[F0:f[1-3]*[02468]+]]
169 ; 32-DAG: mtc1 $7, $[[F0H:f[1-3]*[13579]+]]
170 ; 32-DAG: ldc1 $[[F1:f0]], 16($sp)
171 ; 32: movn.d $[[F1]], $[[F0]], $4
173 ; 32R2-DAG: mtc1 $6, $[[F0:f[0-9]+]]
174 ; 32R2-DAG: mthc1 $7, $[[F0]]
175 ; 32R2-DAG: ldc1 $[[F1:f0]], 16($sp)
176 ; 32R2: movn.d $[[F1]], $[[F0]], $4
178 ; 32R6-DAG: mtc1 $6, $[[F0:f[0-9]+]]
179 ; 32R6-DAG: mthc1 $7, $[[F0]]
180 ; 32R6-DAG: sltu $[[T0:[0-9]+]], $zero, $4
181 ; 32R6-DAG: mtc1 $[[T0]], $[[CC:f0]]
182 ; 32R6-DAG: ldc1 $[[F1:f[0-9]+]], 16($sp)
183 ; 32R6: sel.d $[[CC]], $[[F1]], $[[F0]]
185 ; 64: movn.d $f14, $f13, $4
186 ; 64: mov.d $f0, $f14
188 ; 64R2: movn.d $f14, $f13, $4
189 ; 64R2: mov.d $f0, $f14
191 ; 64R6-DAG: sltu $[[T0:[0-9]+]], $zero, $4
192 ; 64R6-DAG: mtc1 $[[T0]], $[[CC:f0]]
193 ; 64R6: sel.d $[[CC]], $f14, $f13
195 %tobool = icmp ne i32 %s, 0
196 %cond = select i1 %tobool, double %f0, double %f1
200 define float @f32_fcmp_oeq_f32_val(float %f0, float %f1, float %f2, float %f3) nounwind readnone {
202 ; ALL-LABEL: f32_fcmp_oeq_f32_val:
204 ; 32-DAG: mtc1 $6, $[[F2:f[0-9]+]]
205 ; 32-DAG: mtc1 $7, $[[F3:f[0-9]+]]
206 ; 32: c.eq.s $[[F2]], $[[F3]]
207 ; 32: movt.s $f14, $f12, $fcc0
208 ; 32: mov.s $f0, $f14
210 ; 32R2-DAG: mtc1 $6, $[[F2:f[0-9]+]]
211 ; 32R2-DAG: mtc1 $7, $[[F3:f[0-9]+]]
212 ; 32R2: c.eq.s $[[F2]], $[[F3]]
213 ; 32R2: movt.s $f14, $f12, $fcc0
214 ; 32R2: mov.s $f0, $f14
216 ; 32R6-DAG: mtc1 $6, $[[F2:f[0-9]+]]
217 ; 32R6-DAG: mtc1 $7, $[[F3:f[0-9]+]]
218 ; 32R6: cmp.eq.s $[[CC:f0]], $[[F2]], $[[F3]]
219 ; 32R6: sel.s $[[CC]], $f14, $f12
221 ; 64: c.eq.s $f14, $f15
222 ; 64: movt.s $f13, $f12, $fcc0
223 ; 64: mov.s $f0, $f13
225 ; 64R2: c.eq.s $f14, $f15
226 ; 64R2: movt.s $f13, $f12, $fcc0
227 ; 64R2: mov.s $f0, $f13
229 ; 64R6: cmp.eq.s $[[CC:f0]], $f14, $f15
230 ; 64R6: sel.s $[[CC]], $f13, $f12
232 %cmp = fcmp oeq float %f2, %f3
233 %cond = select i1 %cmp, float %f0, float %f1
237 define float @f32_fcmp_olt_f32_val(float %f0, float %f1, float %f2, float %f3) nounwind readnone {
239 ; ALL-LABEL: f32_fcmp_olt_f32_val:
241 ; 32-DAG: mtc1 $6, $[[F2:f[0-9]+]]
242 ; 32-DAG: mtc1 $7, $[[F3:f[0-9]+]]
243 ; 32: c.olt.s $[[F2]], $[[F3]]
244 ; 32: movt.s $f14, $f12, $fcc0
245 ; 32: mov.s $f0, $f14
247 ; 32R2-DAG: mtc1 $6, $[[F2:f[0-9]+]]
248 ; 32R2-DAG: mtc1 $7, $[[F3:f[0-9]+]]
249 ; 32R2: c.olt.s $[[F2]], $[[F3]]
250 ; 32R2: movt.s $f14, $f12, $fcc0
251 ; 32R2: mov.s $f0, $f14
253 ; 32R6-DAG: mtc1 $6, $[[F2:f[0-9]+]]
254 ; 32R6-DAG: mtc1 $7, $[[F3:f[0-9]+]]
255 ; 32R6: cmp.lt.s $[[CC:f0]], $[[F2]], $[[F3]]
256 ; 32R6: sel.s $[[CC]], $f14, $f12
258 ; 64: c.olt.s $f14, $f15
259 ; 64: movt.s $f13, $f12, $fcc0
260 ; 64: mov.s $f0, $f13
262 ; 64R2: c.olt.s $f14, $f15
263 ; 64R2: movt.s $f13, $f12, $fcc0
264 ; 64R2: mov.s $f0, $f13
266 ; 64R6: cmp.lt.s $[[CC:f0]], $f14, $f15
267 ; 64R6: sel.s $[[CC]], $f13, $f12
269 %cmp = fcmp olt float %f2, %f3
270 %cond = select i1 %cmp, float %f0, float %f1
274 define float @f32_fcmp_ogt_f32_val(float %f0, float %f1, float %f2, float %f3) nounwind readnone {
276 ; ALL-LABEL: f32_fcmp_ogt_f32_val:
278 ; 32-DAG: mtc1 $6, $[[F2:f[0-9]+]]
279 ; 32-DAG: mtc1 $7, $[[F3:f[0-9]+]]
280 ; 32: c.ule.s $[[F2]], $[[F3]]
281 ; 32: movf.s $f14, $f12, $fcc0
282 ; 32: mov.s $f0, $f14
284 ; 32R2-DAG: mtc1 $6, $[[F2:f[0-9]+]]
285 ; 32R2-DAG: mtc1 $7, $[[F3:f[0-9]+]]
286 ; 32R2: c.ule.s $[[F2]], $[[F3]]
287 ; 32R2: movf.s $f14, $f12, $fcc0
288 ; 32R2: mov.s $f0, $f14
290 ; 32R6-DAG: mtc1 $6, $[[F2:f[0-9]+]]
291 ; 32R6-DAG: mtc1 $7, $[[F3:f[0-9]+]]
292 ; 32R6: cmp.lt.s $[[CC:f0]], $[[F3]], $[[F2]]
293 ; 32R6: sel.s $[[CC]], $f14, $f12
295 ; 64: c.ule.s $f14, $f15
296 ; 64: movf.s $f13, $f12, $fcc0
297 ; 64: mov.s $f0, $f13
299 ; 64R2: c.ule.s $f14, $f15
300 ; 64R2: movf.s $f13, $f12, $fcc0
301 ; 64R2: mov.s $f0, $f13
303 ; 64R6: cmp.lt.s $[[CC:f0]], $f15, $f14
304 ; 64R6: sel.s $[[CC]], $f13, $f12
306 %cmp = fcmp ogt float %f2, %f3
307 %cond = select i1 %cmp, float %f0, float %f1
311 define double @f32_fcmp_ogt_f64_val(double %f0, double %f1, float %f2, float %f3) nounwind readnone {
313 ; ALL-LABEL: f32_fcmp_ogt_f64_val:
315 ; 32-DAG: lwc1 $[[F2:f[0-9]+]], 16($sp)
316 ; 32-DAG: lwc1 $[[F3:f[0-9]+]], 20($sp)
317 ; 32: c.ule.s $[[F2]], $[[F3]]
318 ; 32: movf.d $f14, $f12, $fcc0
319 ; 32: mov.d $f0, $f14
321 ; 32R2-DAG: lwc1 $[[F2:f[0-9]+]], 16($sp)
322 ; 32R2-DAG: lwc1 $[[F3:f[0-9]+]], 20($sp)
323 ; 32R2: c.ule.s $[[F2]], $[[F3]]
324 ; 32R2: movf.d $f14, $f12, $fcc0
325 ; 32R2: mov.d $f0, $f14
327 ; 32R6-DAG: lwc1 $[[F2:f[0-9]+]], 16($sp)
328 ; 32R6-DAG: lwc1 $[[F3:f[0-9]+]], 20($sp)
329 ; 32R6: cmp.lt.s $[[CC:f0]], $[[F3]], $[[F2]]
330 ; 32R6: sel.d $[[CC]], $f14, $f12
332 ; 64: c.ule.s $f14, $f15
333 ; 64: movf.d $f13, $f12, $fcc0
334 ; 64: mov.d $f0, $f13
336 ; 64R2: c.ule.s $f14, $f15
337 ; 64R2: movf.d $f13, $f12, $fcc0
338 ; 64R2: mov.d $f0, $f13
340 ; 64R6: cmp.lt.s $[[CC:f0]], $f15, $f14
341 ; 64R6: sel.d $[[CC]], $f13, $f12
343 %cmp = fcmp ogt float %f2, %f3
344 %cond = select i1 %cmp, double %f0, double %f1
348 define double @f64_fcmp_oeq_f64_val(double %f0, double %f1, double %f2, double %f3) nounwind readnone {
350 ; ALL-LABEL: f64_fcmp_oeq_f64_val:
352 ; 32-DAG: ldc1 $[[F2:f[0-9]+]], 16($sp)
353 ; 32-DAG: ldc1 $[[F3:f[0-9]+]], 24($sp)
354 ; 32: c.eq.d $[[F2]], $[[F3]]
355 ; 32: movt.d $f14, $f12, $fcc0
356 ; 32: mov.d $f0, $f14
358 ; 32R2-DAG: ldc1 $[[F2:f[0-9]+]], 16($sp)
359 ; 32R2-DAG: ldc1 $[[F3:f[0-9]+]], 24($sp)
360 ; 32R2: c.eq.d $[[F2]], $[[F3]]
361 ; 32R2: movt.d $f14, $f12, $fcc0
362 ; 32R2: mov.d $f0, $f14
364 ; 32R6-DAG: ldc1 $[[F2:f[0-9]+]], 16($sp)
365 ; 32R6-DAG: ldc1 $[[F3:f[0-9]+]], 24($sp)
366 ; 32R6: cmp.eq.d $[[CC:f0]], $[[F2]], $[[F3]]
367 ; 32R6: sel.d $[[CC]], $f14, $f12
369 ; 64: c.eq.d $f14, $f15
370 ; 64: movt.d $f13, $f12, $fcc0
371 ; 64: mov.d $f0, $f13
373 ; 64R2: c.eq.d $f14, $f15
374 ; 64R2: movt.d $f13, $f12, $fcc0
375 ; 64R2: mov.d $f0, $f13
377 ; 64R6: cmp.eq.d $[[CC:f0]], $f14, $f15
378 ; 64R6: sel.d $[[CC]], $f13, $f12
380 %cmp = fcmp oeq double %f2, %f3
381 %cond = select i1 %cmp, double %f0, double %f1
385 define double @f64_fcmp_olt_f64_val(double %f0, double %f1, double %f2, double %f3) nounwind readnone {
387 ; ALL-LABEL: f64_fcmp_olt_f64_val:
389 ; 32-DAG: ldc1 $[[F2:f[0-9]+]], 16($sp)
390 ; 32-DAG: ldc1 $[[F3:f[0-9]+]], 24($sp)
391 ; 32: c.olt.d $[[F2]], $[[F3]]
392 ; 32: movt.d $f14, $f12, $fcc0
393 ; 32: mov.d $f0, $f14
395 ; 32R2-DAG: ldc1 $[[F2:f[0-9]+]], 16($sp)
396 ; 32R2-DAG: ldc1 $[[F3:f[0-9]+]], 24($sp)
397 ; 32R2: c.olt.d $[[F2]], $[[F3]]
398 ; 32R2: movt.d $f14, $f12, $fcc0
399 ; 32R2: mov.d $f0, $f14
401 ; 32R6-DAG: ldc1 $[[F2:f[0-9]+]], 16($sp)
402 ; 32R6-DAG: ldc1 $[[F3:f[0-9]+]], 24($sp)
403 ; 32R6: cmp.lt.d $[[CC:f0]], $[[F2]], $[[F3]]
404 ; 32R6: sel.d $[[CC]], $f14, $f12
406 ; 64: c.olt.d $f14, $f15
407 ; 64: movt.d $f13, $f12, $fcc0
408 ; 64: mov.d $f0, $f13
410 ; 64R2: c.olt.d $f14, $f15
411 ; 64R2: movt.d $f13, $f12, $fcc0
412 ; 64R2: mov.d $f0, $f13
414 ; 64R6: cmp.lt.d $[[CC:f0]], $f14, $f15
415 ; 64R6: sel.d $[[CC]], $f13, $f12
417 %cmp = fcmp olt double %f2, %f3
418 %cond = select i1 %cmp, double %f0, double %f1
422 define double @f64_fcmp_ogt_f64_val(double %f0, double %f1, double %f2, double %f3) nounwind readnone {
424 ; ALL-LABEL: f64_fcmp_ogt_f64_val:
426 ; 32-DAG: ldc1 $[[F2:f[0-9]+]], 16($sp)
427 ; 32-DAG: ldc1 $[[F3:f[0-9]+]], 24($sp)
428 ; 32: c.ule.d $[[F2]], $[[F3]]
429 ; 32: movf.d $f14, $f12, $fcc0
430 ; 32: mov.d $f0, $f14
432 ; 32R2-DAG: ldc1 $[[F2:f[0-9]+]], 16($sp)
433 ; 32R2-DAG: ldc1 $[[F3:f[0-9]+]], 24($sp)
434 ; 32R2: c.ule.d $[[F2]], $[[F3]]
435 ; 32R2: movf.d $f14, $f12, $fcc0
436 ; 32R2: mov.d $f0, $f14
438 ; 32R6-DAG: ldc1 $[[F2:f[0-9]+]], 16($sp)
439 ; 32R6-DAG: ldc1 $[[F3:f[0-9]+]], 24($sp)
440 ; 32R6: cmp.lt.d $[[CC:f0]], $[[F3]], $[[F2]]
441 ; 32R6: sel.d $[[CC]], $f14, $f12
443 ; 64: c.ule.d $f14, $f15
444 ; 64: movf.d $f13, $f12, $fcc0
445 ; 64: mov.d $f0, $f13
447 ; 64R2: c.ule.d $f14, $f15
448 ; 64R2: movf.d $f13, $f12, $fcc0
449 ; 64R2: mov.d $f0, $f13
451 ; 64R6: cmp.lt.d $[[CC:f0]], $f15, $f14
452 ; 64R6: sel.d $[[CC]], $f13, $f12
454 %cmp = fcmp ogt double %f2, %f3
455 %cond = select i1 %cmp, double %f0, double %f1
459 define float @f64_fcmp_ogt_f32_val(float %f0, float %f1, double %f2, double %f3) nounwind readnone {
461 ; ALL-LABEL: f64_fcmp_ogt_f32_val:
463 ; 32-DAG: mtc1 $6, $[[F2:f[1-3]*[02468]+]]
464 ; 32-DAG: mtc1 $7, $[[F2H:f[1-3]*[13579]+]]
465 ; 32-DAG: ldc1 $[[F3:f[0-9]+]], 16($sp)
466 ; 32: c.ule.d $[[F2]], $[[F3]]
467 ; 32: movf.s $f14, $f12, $fcc0
468 ; 32: mov.s $f0, $f14
470 ; 32R2-DAG: mtc1 $6, $[[F2:f[0-9]+]]
471 ; 32R2-DAG: mthc1 $7, $[[F2]]
472 ; 32R2-DAG: ldc1 $[[F3:f[0-9]+]], 16($sp)
473 ; 32R2: c.ule.d $[[F2]], $[[F3]]
474 ; 32R2: movf.s $f14, $f12, $fcc0
475 ; 32R2: mov.s $f0, $f14
477 ; 32R6-DAG: mtc1 $6, $[[F2:f[0-9]+]]
478 ; 32R6-DAG: mthc1 $7, $[[F2]]
479 ; 32R6-DAG: ldc1 $[[F3:f[0-9]+]], 16($sp)
480 ; 32R6: cmp.lt.d $[[CC:f0]], $[[F3]], $[[F2]]
481 ; 32R6: sel.s $[[CC]], $f14, $f12
483 ; 64: c.ule.d $f14, $f15
484 ; 64: movf.s $f13, $f12, $fcc0
485 ; 64: mov.s $f0, $f13
487 ; 64R2: c.ule.d $f14, $f15
488 ; 64R2: movf.s $f13, $f12, $fcc0
489 ; 64R2: mov.s $f0, $f13
491 ; 64R6: cmp.lt.d $[[CC:f0]], $f15, $f14
492 ; 64R6: sel.s $[[CC]], $f13, $f12
494 %cmp = fcmp ogt double %f2, %f3
495 %cond = select i1 %cmp, float %f0, float %f1
499 define i32 @f32_fcmp_oeq_i32_val(i32 %f0, i32 %f1, float %f2, float %f3) nounwind readnone {
501 ; ALL-LABEL: f32_fcmp_oeq_i32_val:
503 ; 32-DAG: mtc1 $6, $[[F2:f[0-9]+]]
504 ; 32-DAG: mtc1 $7, $[[F3:f[0-9]+]]
505 ; 32: c.eq.s $[[F2]], $[[F3]]
506 ; 32: movt $5, $4, $fcc0
509 ; 32R2-DAG: mtc1 $6, $[[F2:f[0-9]+]]
510 ; 32R2-DAG: mtc1 $7, $[[F3:f[0-9]+]]
511 ; 32R2: c.eq.s $[[F2]], $[[F3]]
512 ; 32R2: movt $5, $4, $fcc0
515 ; 32R6-DAG: mtc1 $6, $[[F2:f[0-9]+]]
516 ; 32R6-DAG: mtc1 $7, $[[F3:f[0-9]+]]
517 ; 32R6: cmp.eq.s $[[CC:f[0-9]+]], $[[F2]], $[[F3]]
518 ; 32R6: mfc1 $[[CCGPR:[0-9]+]], $[[CC]]
519 ; 32R6: seleqz $[[EQ:[0-9]+]], $5, $[[CCGPR]]
520 ; FIXME: This move is redundant
521 ; 32R6: mfc1 $[[CCGPR:[0-9]+]], $[[CC]]
522 ; 32R6: selnez $[[NE:[0-9]+]], $4, $[[CCGPR]]
523 ; 32R6: or $2, $[[NE]], $[[EQ]]
525 ; 64: c.eq.s $f14, $f15
526 ; 64: movt $5, $4, $fcc0
529 ; 64R2: c.eq.s $f14, $f15
530 ; 64R2: movt $5, $4, $fcc0
533 ; 64R6: cmp.eq.s $[[CC:f[0-9]+]], $f14, $f15
534 ; 64R6: mfc1 $[[CCGPR:[0-9]+]], $[[CC]]
535 ; 64R6: seleqz $[[EQ:[0-9]+]], $5, $[[CCGPR]]
536 ; FIXME: This move is redundant
537 ; 64R6: mfc1 $[[CCGPR:[0-9]+]], $[[CC]]
538 ; 64R6: selnez $[[NE:[0-9]+]], $4, $[[CCGPR]]
539 ; 64R6: or $2, $[[NE]], $[[EQ]]
541 %cmp = fcmp oeq float %f2, %f3
542 %cond = select i1 %cmp, i32 %f0, i32 %f1
546 define i32 @f32_fcmp_olt_i32_val(i32 %f0, i32 %f1, float %f2, float %f3) nounwind readnone {
548 ; ALL-LABEL: f32_fcmp_olt_i32_val:
550 ; 32-DAG: mtc1 $6, $[[F2:f[0-9]+]]
551 ; 32-DAG: mtc1 $7, $[[F3:f[0-9]+]]
552 ; 32: c.olt.s $[[F2]], $[[F3]]
553 ; 32: movt $5, $4, $fcc0
556 ; 32R2-DAG: mtc1 $6, $[[F2:f[0-9]+]]
557 ; 32R2-DAG: mtc1 $7, $[[F3:f[0-9]+]]
558 ; 32R2: c.olt.s $[[F2]], $[[F3]]
559 ; 32R2: movt $5, $4, $fcc0
562 ; 32R6-DAG: mtc1 $6, $[[F2:f[0-9]+]]
563 ; 32R6-DAG: mtc1 $7, $[[F3:f[0-9]+]]
564 ; 32R6: cmp.lt.s $[[CC:f[0-9]+]], $[[F2]], $[[F3]]
565 ; 32R6: mfc1 $[[CCGPR:[0-9]+]], $[[CC]]
566 ; 32R6: seleqz $[[EQ:[0-9]+]], $5, $[[CCGPR]]
567 ; FIXME: This move is redundant
568 ; 32R6: mfc1 $[[CCGPR:[0-9]+]], $[[CC]]
569 ; 32R6: selnez $[[NE:[0-9]+]], $4, $[[CCGPR]]
570 ; 32R6: or $2, $[[NE]], $[[EQ]]
572 ; 64: c.olt.s $f14, $f15
573 ; 64: movt $5, $4, $fcc0
576 ; 64R2: c.olt.s $f14, $f15
577 ; 64R2: movt $5, $4, $fcc0
580 ; 64R6: cmp.lt.s $[[CC:f[0-9]+]], $f14, $f15
581 ; 64R6: mfc1 $[[CCGPR:[0-9]+]], $[[CC]]
582 ; 64R6: seleqz $[[EQ:[0-9]+]], $5, $[[CCGPR]]
583 ; FIXME: This move is redundant
584 ; 64R6: mfc1 $[[CCGPR:[0-9]+]], $[[CC]]
585 ; 64R6: selnez $[[NE:[0-9]+]], $4, $[[CCGPR]]
586 ; 64R6: or $2, $[[NE]], $[[EQ]]
587 %cmp = fcmp olt float %f2, %f3
588 %cond = select i1 %cmp, i32 %f0, i32 %f1
592 define i32 @f32_fcmp_ogt_i32_val(i32 %f0, i32 %f1, float %f2, float %f3) nounwind readnone {
594 ; ALL-LABEL: f32_fcmp_ogt_i32_val:
596 ; 32-DAG: mtc1 $6, $[[F2:f[0-9]+]]
597 ; 32-DAG: mtc1 $7, $[[F3:f[0-9]+]]
598 ; 32: c.ule.s $[[F2]], $[[F3]]
599 ; 32: movf $5, $4, $fcc0
602 ; 32R2-DAG: mtc1 $6, $[[F2:f[0-9]+]]
603 ; 32R2-DAG: mtc1 $7, $[[F3:f[0-9]+]]
604 ; 32R2: c.ule.s $[[F2]], $[[F3]]
605 ; 32R2: movf $5, $4, $fcc0
608 ; 32R6-DAG: mtc1 $6, $[[F2:f[0-9]+]]
609 ; 32R6-DAG: mtc1 $7, $[[F3:f[0-9]+]]
610 ; 32R6: cmp.lt.s $[[CC:f[0-9]+]], $[[F3]], $[[F2]]
611 ; 32R6: mfc1 $[[CCGPR:[0-9]+]], $[[CC]]
612 ; 32R6: seleqz $[[EQ:[0-9]+]], $5, $[[CCGPR]]
613 ; FIXME: This move is redundant
614 ; 32R6: mfc1 $[[CCGPR:[0-9]+]], $[[CC]]
615 ; 32R6: selnez $[[NE:[0-9]+]], $4, $[[CCGPR]]
616 ; 32R6: or $2, $[[NE]], $[[EQ]]
618 ; 64: c.ule.s $f14, $f15
619 ; 64: movf $5, $4, $fcc0
622 ; 64R2: c.ule.s $f14, $f15
623 ; 64R2: movf $5, $4, $fcc0
626 ; 64R6: cmp.lt.s $[[CC:f[0-9]+]], $f15, $f14
627 ; 64R6: mfc1 $[[CCGPR:[0-9]+]], $[[CC]]
628 ; 64R6: seleqz $[[EQ:[0-9]+]], $5, $[[CCGPR]]
629 ; FIXME: This move is redundant
630 ; 64R6: mfc1 $[[CCGPR:[0-9]+]], $[[CC]]
631 ; 64R6: selnez $[[NE:[0-9]+]], $4, $[[CCGPR]]
632 ; 64R6: or $2, $[[NE]], $[[EQ]]
634 %cmp = fcmp ogt float %f2, %f3
635 %cond = select i1 %cmp, i32 %f0, i32 %f1
639 define i32 @f64_fcmp_oeq_i32_val(i32 %f0, i32 %f1) nounwind readonly {
641 ; ALL-LABEL: f64_fcmp_oeq_i32_val:
643 ; 32-DAG: addiu $[[T0:[0-9]+]], ${{[0-9]+}}, %lo(_gp_disp)
644 ; 32-DAG: addu $[[GOT:[0-9]+]], $[[T0]], $25
645 ; 32-DAG: lw $[[D2:[0-9]+]], %got(d2)($1)
646 ; 32-DAG: ldc1 $[[TMP:f[0-9]+]], 0($[[D2]])
647 ; 32-DAG: lw $[[D3:[0-9]+]], %got(d3)($1)
648 ; 32-DAG: ldc1 $[[TMP1:f[0-9]+]], 0($[[D3]])
649 ; 32: c.eq.d $[[TMP]], $[[TMP1]]
650 ; 32: movt $5, $4, $fcc0
653 ; 32R2-DAG: addiu $[[T0:[0-9]+]], ${{[0-9]+}}, %lo(_gp_disp)
654 ; 32R2-DAG: addu $[[GOT:[0-9]+]], $[[T0]], $25
655 ; 32R2-DAG: lw $[[D2:[0-9]+]], %got(d2)($1)
656 ; 32R2-DAG: ldc1 $[[TMP:f[0-9]+]], 0($[[D2]])
657 ; 32R2-DAG: lw $[[D3:[0-9]+]], %got(d3)($1)
658 ; 32R2-DAG: ldc1 $[[TMP1:f[0-9]+]], 0($[[D3]])
659 ; 32R2: c.eq.d $[[TMP]], $[[TMP1]]
660 ; 32R2: movt $5, $4, $fcc0
663 ; 32R6-DAG: addiu $[[T0:[0-9]+]], ${{[0-9]+}}, %lo(_gp_disp)
664 ; 32R6-DAG: addu $[[GOT:[0-9]+]], $[[T0]], $25
665 ; 32R6-DAG: lw $[[D2:[0-9]+]], %got(d2)($1)
666 ; 32R6-DAG: ldc1 $[[TMP:f[0-9]+]], 0($[[D2]])
667 ; 32R6-DAG: lw $[[D3:[0-9]+]], %got(d3)($1)
668 ; 32R6-DAG: ldc1 $[[TMP1:f[0-9]+]], 0($[[D3]])
669 ; 32R6: cmp.eq.d $[[CC:f[0-9]+]], $[[TMP]], $[[TMP1]]
670 ; 32R6: mfc1 $[[CCGPR:[0-9]+]], $[[CC]]
671 ; 32R6: seleqz $[[EQ:[0-9]+]], $5, $[[CCGPR]]
672 ; FIXME: This move is redundant
673 ; 32R6: mfc1 $[[CCGPR:[0-9]+]], $[[CC]]
674 ; 32R6: selnez $[[NE:[0-9]+]], $4, $[[CCGPR]]
675 ; 32R6: or $2, $[[NE]], $[[EQ]]
677 ; 64-DAG: daddiu $[[T0:[0-9]+]], ${{[0-9]+}}, %lo(%neg(%gp_rel(f64_fcmp_oeq_i32_val)))
678 ; 64-DAG: daddu $[[GOT:[0-9]+]], $[[T0]], $25
679 ; 64-DAG: ld $[[D2:[0-9]+]], %got_disp(d2)($1)
680 ; 64-DAG: ldc1 $[[TMP:f[0-9]+]], 0($[[D2]])
681 ; 64-DAG: ld $[[D3:[0-9]+]], %got_disp(d3)($1)
682 ; 64-DAG: ldc1 $[[TMP1:f[0-9]+]], 0($[[D3]])
683 ; 64: c.eq.d $[[TMP]], $[[TMP1]]
684 ; 64: movt $5, $4, $fcc0
687 ; 64R2-DAG: daddiu $[[T0:[0-9]+]], ${{[0-9]+}}, %lo(%neg(%gp_rel(f64_fcmp_oeq_i32_val)))
688 ; 64R2-DAG: daddu $[[GOT:[0-9]+]], $[[T0]], $25
689 ; 64R2-DAG: ld $[[D2:[0-9]+]], %got_disp(d2)($1)
690 ; 64R2-DAG: ldc1 $[[TMP:f[0-9]+]], 0($[[D2]])
691 ; 64R2-DAG: ld $[[D3:[0-9]+]], %got_disp(d3)($1)
692 ; 64R2-DAG: ldc1 $[[TMP1:f[0-9]+]], 0($[[D3]])
693 ; 64R2: c.eq.d $[[TMP]], $[[TMP1]]
694 ; 64R2: movt $5, $4, $fcc0
697 ; 64R6-DAG: daddiu $[[T0:[0-9]+]], ${{[0-9]+}}, %lo(%neg(%gp_rel(f64_fcmp_oeq_i32_val)))
698 ; 64R6-DAG: daddu $[[GOT:[0-9]+]], $[[T0]], $25
699 ; 64R6-DAG: ld $[[D2:[0-9]+]], %got_disp(d2)($1)
700 ; 64R6-DAG: ldc1 $[[TMP:f[0-9]+]], 0($[[D2]])
701 ; 64R6-DAG: ld $[[D3:[0-9]+]], %got_disp(d3)($1)
702 ; 64R6-DAG: ldc1 $[[TMP1:f[0-9]+]], 0($[[D3]])
703 ; 64R6: cmp.eq.d $[[CC:f[0-9]+]], $[[TMP]], $[[TMP1]]
704 ; 64R6: mfc1 $[[CCGPR:[0-9]+]], $[[CC]]
705 ; 64R6: seleqz $[[EQ:[0-9]+]], $5, $[[CCGPR]]
706 ; FIXME: This move is redundant
707 ; 64R6: mfc1 $[[CCGPR:[0-9]+]], $[[CC]]
708 ; 64R6: selnez $[[NE:[0-9]+]], $4, $[[CCGPR]]
709 ; 64R6: or $2, $[[NE]], $[[EQ]]
711 %tmp = load double* @d2, align 8
712 %tmp1 = load double* @d3, align 8
713 %cmp = fcmp oeq double %tmp, %tmp1
714 %cond = select i1 %cmp, i32 %f0, i32 %f1
718 define i32 @f64_fcmp_olt_i32_val(i32 %f0, i32 %f1) nounwind readonly {
720 ; ALL-LABEL: f64_fcmp_olt_i32_val:
722 ; 32-DAG: addiu $[[T0:[0-9]+]], ${{[0-9]+}}, %lo(_gp_disp)
723 ; 32-DAG: addu $[[GOT:[0-9]+]], $[[T0]], $25
724 ; 32-DAG: lw $[[D2:[0-9]+]], %got(d2)($1)
725 ; 32-DAG: ldc1 $[[TMP:f[0-9]+]], 0($[[D2]])
726 ; 32-DAG: lw $[[D3:[0-9]+]], %got(d3)($1)
727 ; 32-DAG: ldc1 $[[TMP1:f[0-9]+]], 0($[[D3]])
728 ; 32: c.olt.d $[[TMP]], $[[TMP1]]
729 ; 32: movt $5, $4, $fcc0
732 ; 32R2-DAG: addiu $[[T0:[0-9]+]], ${{[0-9]+}}, %lo(_gp_disp)
733 ; 32R2-DAG: addu $[[GOT:[0-9]+]], $[[T0]], $25
734 ; 32R2-DAG: lw $[[D2:[0-9]+]], %got(d2)($1)
735 ; 32R2-DAG: ldc1 $[[TMP:f[0-9]+]], 0($[[D2]])
736 ; 32R2-DAG: lw $[[D3:[0-9]+]], %got(d3)($1)
737 ; 32R2-DAG: ldc1 $[[TMP1:f[0-9]+]], 0($[[D3]])
738 ; 32R2: c.olt.d $[[TMP]], $[[TMP1]]
739 ; 32R2: movt $5, $4, $fcc0
742 ; 32R6-DAG: addiu $[[T0:[0-9]+]], ${{[0-9]+}}, %lo(_gp_disp)
743 ; 32R6-DAG: addu $[[GOT:[0-9]+]], $[[T0]], $25
744 ; 32R6-DAG: lw $[[D2:[0-9]+]], %got(d2)($1)
745 ; 32R6-DAG: ldc1 $[[TMP:f[0-9]+]], 0($[[D2]])
746 ; 32R6-DAG: lw $[[D3:[0-9]+]], %got(d3)($1)
747 ; 32R6-DAG: ldc1 $[[TMP1:f[0-9]+]], 0($[[D3]])
748 ; 32R6: cmp.lt.d $[[CC:f[0-9]+]], $[[TMP]], $[[TMP1]]
749 ; 32R6: mfc1 $[[CCGPR:[0-9]+]], $[[CC]]
750 ; 32R6: seleqz $[[EQ:[0-9]+]], $5, $[[CCGPR]]
751 ; FIXME: This move is redundant
752 ; 32R6: mfc1 $[[CCGPR:[0-9]+]], $[[CC]]
753 ; 32R6: selnez $[[NE:[0-9]+]], $4, $[[CCGPR]]
754 ; 32R6: or $2, $[[NE]], $[[EQ]]
756 ; 64-DAG: daddiu $[[T0:[0-9]+]], ${{[0-9]+}}, %lo(%neg(%gp_rel(f64_fcmp_olt_i32_val)))
757 ; 64-DAG: daddu $[[GOT:[0-9]+]], $[[T0]], $25
758 ; 64-DAG: ld $[[D2:[0-9]+]], %got_disp(d2)($1)
759 ; 64-DAG: ldc1 $[[TMP:f[0-9]+]], 0($[[D2]])
760 ; 64-DAG: ld $[[D3:[0-9]+]], %got_disp(d3)($1)
761 ; 64-DAG: ldc1 $[[TMP1:f[0-9]+]], 0($[[D3]])
762 ; 64: c.olt.d $[[TMP]], $[[TMP1]]
763 ; 64: movt $5, $4, $fcc0
766 ; 64R2-DAG: daddiu $[[T0:[0-9]+]], ${{[0-9]+}}, %lo(%neg(%gp_rel(f64_fcmp_olt_i32_val)))
767 ; 64R2-DAG: daddu $[[GOT:[0-9]+]], $[[T0]], $25
768 ; 64R2-DAG: ld $[[D2:[0-9]+]], %got_disp(d2)($1)
769 ; 64R2-DAG: ldc1 $[[TMP:f[0-9]+]], 0($[[D2]])
770 ; 64R2-DAG: ld $[[D3:[0-9]+]], %got_disp(d3)($1)
771 ; 64R2-DAG: ldc1 $[[TMP1:f[0-9]+]], 0($[[D3]])
772 ; 64R2: c.olt.d $[[TMP]], $[[TMP1]]
773 ; 64R2: movt $5, $4, $fcc0
776 ; 64R6-DAG: daddiu $[[T0:[0-9]+]], ${{[0-9]+}}, %lo(%neg(%gp_rel(f64_fcmp_olt_i32_val)))
777 ; 64R6-DAG: daddu $[[GOT:[0-9]+]], $[[T0]], $25
778 ; 64R6-DAG: ld $[[D2:[0-9]+]], %got_disp(d2)($1)
779 ; 64R6-DAG: ldc1 $[[TMP:f[0-9]+]], 0($[[D2]])
780 ; 64R6-DAG: ld $[[D3:[0-9]+]], %got_disp(d3)($1)
781 ; 64R6-DAG: ldc1 $[[TMP1:f[0-9]+]], 0($[[D3]])
782 ; 64R6: cmp.lt.d $[[CC:f[0-9]+]], $[[TMP]], $[[TMP1]]
783 ; 64R6: mfc1 $[[CCGPR:[0-9]+]], $[[CC]]
784 ; 64R6: seleqz $[[EQ:[0-9]+]], $5, $[[CCGPR]]
785 ; FIXME: This move is redundant
786 ; 64R6: mfc1 $[[CCGPR:[0-9]+]], $[[CC]]
787 ; 64R6: selnez $[[NE:[0-9]+]], $4, $[[CCGPR]]
788 ; 64R6: or $2, $[[NE]], $[[EQ]]
790 %tmp = load double* @d2, align 8
791 %tmp1 = load double* @d3, align 8
792 %cmp = fcmp olt double %tmp, %tmp1
793 %cond = select i1 %cmp, i32 %f0, i32 %f1
797 define i32 @f64_fcmp_ogt_i32_val(i32 %f0, i32 %f1) nounwind readonly {
799 ; ALL-LABEL: f64_fcmp_ogt_i32_val:
801 ; 32-DAG: addiu $[[T0:[0-9]+]], ${{[0-9]+}}, %lo(_gp_disp)
802 ; 32-DAG: addu $[[GOT:[0-9]+]], $[[T0]], $25
803 ; 32-DAG: lw $[[D2:[0-9]+]], %got(d2)($1)
804 ; 32-DAG: ldc1 $[[TMP:f[0-9]+]], 0($[[D2]])
805 ; 32-DAG: lw $[[D3:[0-9]+]], %got(d3)($1)
806 ; 32-DAG: ldc1 $[[TMP1:f[0-9]+]], 0($[[D3]])
807 ; 32: c.ule.d $[[TMP]], $[[TMP1]]
808 ; 32: movf $5, $4, $fcc0
811 ; 32R2-DAG: addiu $[[T0:[0-9]+]], ${{[0-9]+}}, %lo(_gp_disp)
812 ; 32R2-DAG: addu $[[GOT:[0-9]+]], $[[T0]], $25
813 ; 32R2-DAG: lw $[[D2:[0-9]+]], %got(d2)($1)
814 ; 32R2-DAG: ldc1 $[[TMP:f[0-9]+]], 0($[[D2]])
815 ; 32R2-DAG: lw $[[D3:[0-9]+]], %got(d3)($1)
816 ; 32R2-DAG: ldc1 $[[TMP1:f[0-9]+]], 0($[[D3]])
817 ; 32R2: c.ule.d $[[TMP]], $[[TMP1]]
818 ; 32R2: movf $5, $4, $fcc0
821 ; 32R6-DAG: addiu $[[T0:[0-9]+]], ${{[0-9]+}}, %lo(_gp_disp)
822 ; 32R6-DAG: addu $[[GOT:[0-9]+]], $[[T0]], $25
823 ; 32R6-DAG: lw $[[D2:[0-9]+]], %got(d2)($1)
824 ; 32R6-DAG: ldc1 $[[TMP:f[0-9]+]], 0($[[D2]])
825 ; 32R6-DAG: lw $[[D3:[0-9]+]], %got(d3)($1)
826 ; 32R6-DAG: ldc1 $[[TMP1:f[0-9]+]], 0($[[D3]])
827 ; 32R6: cmp.lt.d $[[CC:f[0-9]+]], $[[TMP1]], $[[TMP]]
828 ; 32R6: mfc1 $[[CCGPR:[0-9]+]], $[[CC]]
829 ; 32R6: seleqz $[[EQ:[0-9]+]], $5, $[[CCGPR]]
830 ; FIXME: This move is redundant
831 ; 32R6: mfc1 $[[CCGPR:[0-9]+]], $[[CC]]
832 ; 32R6: selnez $[[NE:[0-9]+]], $4, $[[CCGPR]]
833 ; 32R6: or $2, $[[NE]], $[[EQ]]
835 ; 64-DAG: daddiu $[[T0:[0-9]+]], ${{[0-9]+}}, %lo(%neg(%gp_rel(f64_fcmp_ogt_i32_val)))
836 ; 64-DAG: daddu $[[GOT:[0-9]+]], $[[T0]], $25
837 ; 64-DAG: ld $[[D2:[0-9]+]], %got_disp(d2)($1)
838 ; 64-DAG: ldc1 $[[TMP:f[0-9]+]], 0($[[D2]])
839 ; 64-DAG: ld $[[D3:[0-9]+]], %got_disp(d3)($1)
840 ; 64-DAG: ldc1 $[[TMP1:f[0-9]+]], 0($[[D3]])
841 ; 64: c.ule.d $[[TMP]], $[[TMP1]]
842 ; 64: movf $5, $4, $fcc0
845 ; 64R2-DAG: daddiu $[[T0:[0-9]+]], ${{[0-9]+}}, %lo(%neg(%gp_rel(f64_fcmp_ogt_i32_val)))
846 ; 64R2-DAG: daddu $[[GOT:[0-9]+]], $[[T0]], $25
847 ; 64R2-DAG: ld $[[D2:[0-9]+]], %got_disp(d2)($1)
848 ; 64R2-DAG: ldc1 $[[TMP:f[0-9]+]], 0($[[D2]])
849 ; 64R2-DAG: ld $[[D3:[0-9]+]], %got_disp(d3)($1)
850 ; 64R2-DAG: ldc1 $[[TMP1:f[0-9]+]], 0($[[D3]])
851 ; 64R2: c.ule.d $[[TMP]], $[[TMP1]]
852 ; 64R2: movf $5, $4, $fcc0
855 ; 64R6-DAG: daddiu $[[T0:[0-9]+]], ${{[0-9]+}}, %lo(%neg(%gp_rel(f64_fcmp_ogt_i32_val)))
856 ; 64R6-DAG: daddu $[[GOT:[0-9]+]], $[[T0]], $25
857 ; 64R6-DAG: ld $[[D2:[0-9]+]], %got_disp(d2)($1)
858 ; 64R6-DAG: ldc1 $[[TMP:f[0-9]+]], 0($[[D2]])
859 ; 64R6-DAG: ld $[[D3:[0-9]+]], %got_disp(d3)($1)
860 ; 64R6-DAG: ldc1 $[[TMP1:f[0-9]+]], 0($[[D3]])
861 ; 64R6: cmp.lt.d $[[CC:f[0-9]+]], $[[TMP1]], $[[TMP]]
862 ; 64R6: mfc1 $[[CCGPR:[0-9]+]], $[[CC]]
863 ; 64R6: seleqz $[[EQ:[0-9]+]], $5, $[[CCGPR]]
864 ; FIXME: This move is redundant
865 ; 64R6: mfc1 $[[CCGPR:[0-9]+]], $[[CC]]
866 ; 64R6: selnez $[[NE:[0-9]+]], $4, $[[CCGPR]]
867 ; 64R6: or $2, $[[NE]], $[[EQ]]
869 %tmp = load double* @d2, align 8
870 %tmp1 = load double* @d3, align 8
871 %cmp = fcmp ogt double %tmp, %tmp1
872 %cond = select i1 %cmp, i32 %f0, i32 %f1