1 ; RUN: llc < %s -march=nvptx -mcpu=sm_20 | FileCheck %s
5 define i32 @atom0(i32* %addr, i32 %val) {
7 %ret = atomicrmw add i32* %addr, i32 %val seq_cst
12 define i64 @atom1(i64* %addr, i64 %val) {
14 %ret = atomicrmw add i64* %addr, i64 %val seq_cst
19 define i32 @atom2(i32* %subr, i32 %val) {
22 %ret = atomicrmw sub i32* %subr, i32 %val seq_cst
27 define i64 @atom3(i64* %subr, i64 %val) {
30 %ret = atomicrmw sub i64* %subr, i64 %val seq_cst
35 define i32 @atom4(i32* %subr, i32 %val) {
37 %ret = atomicrmw and i32* %subr, i32 %val seq_cst
42 define i64 @atom5(i64* %subr, i64 %val) {
44 %ret = atomicrmw and i64* %subr, i64 %val seq_cst
48 ;; NAND not yet supported
49 ;define i32 @atom6(i32* %subr, i32 %val) {
50 ; %ret = atomicrmw nand i32* %subr, i32 %val seq_cst
54 ;define i64 @atom7(i64* %subr, i64 %val) {
55 ; %ret = atomicrmw nand i64* %subr, i64 %val seq_cst
60 define i32 @atom8(i32* %subr, i32 %val) {
62 %ret = atomicrmw or i32* %subr, i32 %val seq_cst
67 define i64 @atom9(i64* %subr, i64 %val) {
69 %ret = atomicrmw or i64* %subr, i64 %val seq_cst
74 define i32 @atom10(i32* %subr, i32 %val) {
76 %ret = atomicrmw xor i32* %subr, i32 %val seq_cst
81 define i64 @atom11(i64* %subr, i64 %val) {
83 %ret = atomicrmw xor i64* %subr, i64 %val seq_cst
88 define i32 @atom12(i32* %subr, i32 %val) {
90 %ret = atomicrmw max i32* %subr, i32 %val seq_cst
95 define i64 @atom13(i64* %subr, i64 %val) {
97 %ret = atomicrmw max i64* %subr, i64 %val seq_cst
101 ; CHECK-LABEL: atom14
102 define i32 @atom14(i32* %subr, i32 %val) {
103 ; CHECK: atom.min.s32
104 %ret = atomicrmw min i32* %subr, i32 %val seq_cst
108 ; CHECK-LABEL: atom15
109 define i64 @atom15(i64* %subr, i64 %val) {
110 ; CHECK: atom.min.s64
111 %ret = atomicrmw min i64* %subr, i64 %val seq_cst
115 ; CHECK-LABEL: atom16
116 define i32 @atom16(i32* %subr, i32 %val) {
117 ; CHECK: atom.max.u32
118 %ret = atomicrmw umax i32* %subr, i32 %val seq_cst
122 ; CHECK-LABEL: atom17
123 define i64 @atom17(i64* %subr, i64 %val) {
124 ; CHECK: atom.max.u64
125 %ret = atomicrmw umax i64* %subr, i64 %val seq_cst
129 ; CHECK-LABEL: atom18
130 define i32 @atom18(i32* %subr, i32 %val) {
131 ; CHECK: atom.min.u32
132 %ret = atomicrmw umin i32* %subr, i32 %val seq_cst
136 ; CHECK-LABEL: atom19
137 define i64 @atom19(i64* %subr, i64 %val) {
138 ; CHECK: atom.min.u64
139 %ret = atomicrmw umin i64* %subr, i64 %val seq_cst
143 declare float @llvm.nvvm.atomic.load.add.f32.p0f32(float* %addr, float %val)
145 ; CHECK-LABEL: atomic_add_f32_generic
146 define float @atomic_add_f32_generic(float* %addr, float %val) {
147 ; CHECK: atom.add.f32
148 %ret = call float @llvm.nvvm.atomic.load.add.f32.p0f32(float* %addr, float %val)
152 declare float @llvm.nvvm.atomic.load.add.f32.p1f32(float addrspace(1)* %addr, float %val)
154 ; CHECK-LABEL: atomic_add_f32_addrspace1
155 define float @atomic_add_f32_addrspace1(float addrspace(1)* %addr, float %val) {
156 ; CHECK: atom.global.add.f32
157 %ret = call float @llvm.nvvm.atomic.load.add.f32.p1f32(float addrspace(1)* %addr, float %val)
161 declare float @llvm.nvvm.atomic.load.add.f32.p3f32(float addrspace(3)* %addr, float %val)
163 ; CHECK-LABEL: atomic_add_f32_addrspace3
164 define float @atomic_add_f32_addrspace3(float addrspace(3)* %addr, float %val) {
165 ; CHECK: atom.shared.add.f32
166 %ret = call float @llvm.nvvm.atomic.load.add.f32.p3f32(float addrspace(3)* %addr, float %val)
170 ; CHECK-LABEL: atomic_cmpxchg_i32
171 define i32 @atomic_cmpxchg_i32(i32* %addr, i32 %cmp, i32 %new) {
172 ; CHECK: atom.cas.b32
173 %pairold = cmpxchg i32* %addr, i32 %cmp, i32 %new seq_cst seq_cst
177 ; CHECK-LABEL: atomic_cmpxchg_i64
178 define i64 @atomic_cmpxchg_i64(i64* %addr, i64 %cmp, i64 %new) {
179 ; CHECK: atom.cas.b64
180 %pairold = cmpxchg i64* %addr, i64 %cmp, i64 %new seq_cst seq_cst