1 ; FIXME: FastISel currently returns false if it hits code that uses VSX
2 ; registers and with -fast-isel-abort=1 turned on the test case will then fail.
3 ; When fastisel better supports VSX fix up this test case.
5 ; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -mattr=-vsx | FileCheck %s --check-prefix=ELF64
6 ; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 -mattr=-vsx | FileCheck %s --check-prefix=ELF64LE
7 ; RUN: llc < %s -O0 -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -mcpu=970 -mattr=-vsx | FileCheck %s --check-prefix=PPC970
9 ;; Tests for 970 don't use -fast-isel-abort=1 because we intentionally punt
10 ;; to SelectionDAG in some cases.
14 define void @sitofp_single_i64(i64 %a, float %b) nounwind ssp {
16 ; ELF64: sitofp_single_i64
17 ; ELF64LE: sitofp_single_i64
18 ; PPC970: sitofp_single_i64
19 %b.addr = alloca float, align 4
20 %conv = sitofp i64 %a to float
31 store float %conv, float* %b.addr, align 4
35 define void @sitofp_single_i32(i32 %a, float %b) nounwind ssp {
37 ; ELF64: sitofp_single_i32
38 ; ELF64LE: sitofp_single_i32
39 ; PPC970: sitofp_single_i32
40 %b.addr = alloca float, align 4
41 %conv = sitofp i32 %a to float
43 ; stack offset used to load the float: 65524 = -16 + 4
44 ; ELF64: ori {{[0-9]+}}, {{[0-9]+}}, 65524
48 ; stack offset used to load the float: 65520 = -16 + 0
49 ; ELF64LE: ori {{[0-9]+}}, {{[0-9]+}}, 65520
56 store float %conv, float* %b.addr, align 4
60 define void @sitofp_single_i16(i16 %a, float %b) nounwind ssp {
62 ; ELF64: sitofp_single_i16
63 ; ELF64LE: sitofp_single_i16
64 ; PPC970: sitofp_single_i16
65 %b.addr = alloca float, align 4
66 %conv = sitofp i16 %a to float
80 store float %conv, float* %b.addr, align 4
84 define void @sitofp_single_i8(i8 %a) nounwind ssp {
86 ; ELF64: sitofp_single_i8
87 ; ELF64LE: sitofp_single_i8
88 ; PPC970: sitofp_single_i8
89 %b.addr = alloca float, align 4
90 %conv = sitofp i8 %a to float
104 store float %conv, float* %b.addr, align 4
108 define void @sitofp_double_i32(i32 %a, double %b) nounwind ssp {
110 ; ELF64: sitofp_double_i32
111 ; ELF64LE: sitofp_double_i32
112 ; PPC970: sitofp_double_i32
113 %b.addr = alloca double, align 8
114 %conv = sitofp i32 %a to double
116 ; stack offset used to load the float: 65524 = -16 + 4
117 ; ELF64: ori {{[0-9]+}}, {{[0-9]+}}, 65524
121 ; stack offset used to load the float: 65520 = -16 + 0
122 ; ELF64LE: ori {{[0-9]+}}, {{[0-9]+}}, 65520
128 store double %conv, double* %b.addr, align 8
132 define void @sitofp_double_i64(i64 %a, double %b) nounwind ssp {
134 ; ELF64: sitofp_double_i64
135 ; ELF64LE: sitofp_double_i64
136 ; PPC970: sitofp_double_i64
137 %b.addr = alloca double, align 8
138 %conv = sitofp i64 %a to double
148 store double %conv, double* %b.addr, align 8
152 define void @sitofp_double_i16(i16 %a, double %b) nounwind ssp {
154 ; ELF64: sitofp_double_i16
155 ; ELF64LE: sitofp_double_i16
156 ; PPC970: sitofp_double_i16
157 %b.addr = alloca double, align 8
158 %conv = sitofp i16 %a to double
171 store double %conv, double* %b.addr, align 8
175 define void @sitofp_double_i8(i8 %a, double %b) nounwind ssp {
177 ; ELF64: sitofp_double_i8
178 ; ELF64LE: sitofp_double_i8
179 ; PPC970: sitofp_double_i8
180 %b.addr = alloca double, align 8
181 %conv = sitofp i8 %a to double
194 store double %conv, double* %b.addr, align 8
200 define void @uitofp_single_i64(i64 %a, float %b) nounwind ssp {
202 ; ELF64: uitofp_single_i64
203 ; ELF64LE: uitofp_single_i64
204 ; PPC970: uitofp_single_i64
205 %b.addr = alloca float, align 4
206 %conv = uitofp i64 %a to float
213 ; PPC970-NOT: fcfidus
214 store float %conv, float* %b.addr, align 4
218 define void @uitofp_single_i32(i32 %a, float %b) nounwind ssp {
220 ; ELF64: uitofp_single_i32
221 ; ELF64LE: uitofp_single_i32
222 ; PPC970: uitofp_single_i32
223 %b.addr = alloca float, align 4
224 %conv = uitofp i32 %a to float
226 ; stack offset used to load the float: 65524 = -16 + 4
227 ; ELF64: ori {{[0-9]+}}, {{[0-9]+}}, 65524
231 ; stack offset used to load the float: 65520 = -16 + 0
232 ; ELF64LE: ori {{[0-9]+}}, {{[0-9]+}}, 65520
236 ; PPC970-NOT: fcfidus
237 store float %conv, float* %b.addr, align 4
241 define void @uitofp_single_i16(i16 %a, float %b) nounwind ssp {
243 ; ELF64: uitofp_single_i16
244 ; ELF64LE: uitofp_single_i16
245 ; PPC970: uitofp_single_i16
246 %b.addr = alloca float, align 4
247 %conv = uitofp i16 %a to float
248 ; ELF64: rldicl {{[0-9]+}}, {{[0-9]+}}, 0, 48
252 ; ELF64LE: rldicl {{[0-9]+}}, {{[0-9]+}}, 0, 48
256 ; PPC970: rlwinm {{[0-9]+}}, {{[0-9]+}}, 0, 16, 31
261 store float %conv, float* %b.addr, align 4
265 define void @uitofp_single_i8(i8 %a) nounwind ssp {
267 ; ELF64: uitofp_single_i8
268 ; ELF64LE: uitofp_single_i8
269 ; PPC970: uitofp_single_i8
270 %b.addr = alloca float, align 4
271 %conv = uitofp i8 %a to float
272 ; ELF64: rldicl {{[0-9]+}}, {{[0-9]+}}, 0, 56
276 ; ELF64LE: rldicl {{[0-9]+}}, {{[0-9]+}}, 0, 56
280 ; PPC970: rlwinm {{[0-9]+}}, {{[0-9]+}}, 0, 24, 31
285 store float %conv, float* %b.addr, align 4
289 define void @uitofp_double_i64(i64 %a, double %b) nounwind ssp {
291 ; ELF64: uitofp_double_i64
292 ; ELF64LE: uitofp_double_i64
293 ; PPC970: uitofp_double_i64
294 %b.addr = alloca double, align 8
295 %conv = uitofp i64 %a to double
303 store double %conv, double* %b.addr, align 8
307 define void @uitofp_double_i32(i32 %a, double %b) nounwind ssp {
309 ; ELF64: uitofp_double_i32
310 ; ELF64LE: uitofp_double_i32
311 ; PPC970: uitofp_double_i32
312 %b.addr = alloca double, align 8
313 %conv = uitofp i32 %a to double
315 ; stack offset used to load the float: 65524 = -16 + 4
316 ; ELF64: ori {{[0-9]+}}, {{[0-9]+}}, 65524
320 ; stack offset used to load the float: 65520 = -16 + 0
321 ; ELF64LE: ori {{[0-9]+}}, {{[0-9]+}}, 65520
326 store double %conv, double* %b.addr, align 8
330 define void @uitofp_double_i16(i16 %a, double %b) nounwind ssp {
332 ; ELF64: uitofp_double_i16
333 ; ELF64LE: uitofp_double_i16
334 ; PPC970: uitofp_double_i16
335 %b.addr = alloca double, align 8
336 %conv = uitofp i16 %a to double
337 ; ELF64: rldicl {{[0-9]+}}, {{[0-9]+}}, 0, 48
341 ; ELF64LE: rldicl {{[0-9]+}}, {{[0-9]+}}, 0, 48
345 ; PPC970: rlwinm {{[0-9]+}}, {{[0-9]+}}, 0, 16, 31
349 store double %conv, double* %b.addr, align 8
353 define void @uitofp_double_i8(i8 %a, double %b) nounwind ssp {
355 ; ELF64: uitofp_double_i8
356 ; ELF64LE: uitofp_double_i8
357 ; PPC970: uitofp_double_i8
358 %b.addr = alloca double, align 8
359 %conv = uitofp i8 %a to double
360 ; ELF64: rldicl {{[0-9]+}}, {{[0-9]+}}, 0, 56
364 ; ELF64LE: rldicl {{[0-9]+}}, {{[0-9]+}}, 0, 56
368 ; PPC970: rlwinm {{[0-9]+}}, {{[0-9]+}}, 0, 24, 31
372 store double %conv, double* %b.addr, align 8
378 define void @fptosi_float_i32(float %a) nounwind ssp {
380 ; ELF64: fptosi_float_i32
381 ; ELF64LE: fptosi_float_i32
382 ; PPC970: fptosi_float_i32
383 %b.addr = alloca i32, align 4
384 %conv = fptosi float %a to i32
394 store i32 %conv, i32* %b.addr, align 4
398 define void @fptosi_float_i64(float %a) nounwind ssp {
400 ; ELF64: fptosi_float_i64
401 ; ELF64LE: fptosi_float_i64
402 ; PPC970: fptosi_float_i64
403 %b.addr = alloca i64, align 4
404 %conv = fptosi float %a to i64
414 store i64 %conv, i64* %b.addr, align 4
418 define void @fptosi_double_i32(double %a) nounwind ssp {
420 ; ELF64: fptosi_double_i32
421 ; ELF64LE: fptosi_double_i32
422 ; PPC970: fptosi_double_i32
423 %b.addr = alloca i32, align 8
424 %conv = fptosi double %a to i32
434 store i32 %conv, i32* %b.addr, align 8
438 define void @fptosi_double_i64(double %a) nounwind ssp {
440 ; ELF64: fptosi_double_i64
441 ; ELF64LE: fptosi_double_i64
442 ; PPC970: fptosi_double_i64
443 %b.addr = alloca i64, align 8
444 %conv = fptosi double %a to i64
454 store i64 %conv, i64* %b.addr, align 8
460 define void @fptoui_float_i32(float %a) nounwind ssp {
462 ; ELF64: fptoui_float_i32
463 ; ELF64LE: fptoui_float_i32
464 ; PPC970: fptoui_float_i32
465 %b.addr = alloca i32, align 4
466 %conv = fptoui float %a to i32
476 store i32 %conv, i32* %b.addr, align 4
480 define void @fptoui_float_i64(float %a) nounwind ssp {
482 ; ELF64: fptoui_float_i64
483 ; ELF64LE: fptoui_float_i64
484 ; PPC970: fptoui_float_i64
485 %b.addr = alloca i64, align 4
486 %conv = fptoui float %a to i64
493 ; PPC970-NOT: fctiduz
494 store i64 %conv, i64* %b.addr, align 4
498 define void @fptoui_double_i32(double %a) nounwind ssp {
500 ; ELF64: fptoui_double_i32
501 ; ELF64LE: fptoui_double_i32
502 ; PPC970: fptoui_double_i32
503 %b.addr = alloca i32, align 8
504 %conv = fptoui double %a to i32
514 store i32 %conv, i32* %b.addr, align 8
518 define void @fptoui_double_i64(double %a) nounwind ssp {
520 ; ELF64: fptoui_double_i64
521 ; ELF64LE: fptoui_double_i64
522 ; PPC970: fptoui_double_i64
523 %b.addr = alloca i64, align 8
524 %conv = fptoui double %a to i64
531 ; PPC970-NOT: fctiduz
532 store i64 %conv, i64* %b.addr, align 8