1 ; RUN: llc -O0 -mcpu=pwr7 -code-model=medium -filetype=obj -fast-isel=false %s -o - | \
2 ; RUN: llvm-readobj -r | FileCheck -check-prefix=MEDIUM %s
3 ; RUN: llc -O0 -mcpu=pwr7 -code-model=large -filetype=obj -fast-isel=false %s -o - | \
4 ; RUN: llvm-readobj -r | FileCheck -check-prefix=LARGE %s
6 ; Run jump table test separately since jump tables aren't generated at -O0.
7 ; RUN: llc -mcpu=pwr7 -code-model=medium -filetype=obj -fast-isel=false %s -o - | \
8 ; RUN: llvm-readobj -r | FileCheck -check-prefix=MEDIUM-JT %s
9 ; RUN: llc -mcpu=pwr7 -code-model=large -filetype=obj -fast-isel=false %s -o - | \
10 ; RUN: llvm-readobj -r | FileCheck -check-prefix=LARGE-JT %s
12 ; FIXME: When asm-parse is available, could make this an assembly test.
14 target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
15 target triple = "powerpc64-unknown-linux-gnu"
17 @ei = external global i32
19 define signext i32 @test_external() nounwind {
21 %0 = load i32, i32* @ei, align 4
22 %inc = add nsw i32 %0, 1
23 store i32 %inc, i32* @ei, align 4
27 ; Verify generation of R_PPC64_TOC16_HA and R_PPC64_TOC16_LO_DS for
28 ; accessing external variable ei.
30 ; MEDIUM: Relocations [
31 ; MEDIUM: Section {{.*}} .rela.text {
32 ; MEDIUM-NEXT: 0x{{[0-9,A-F]+}} R_PPC64_TOC16_HA [[SYM1:[^ ]+]]
33 ; MEDIUM-NEXT: 0x{{[0-9,A-F]+}} R_PPC64_TOC16_LO_DS [[SYM1]]
35 ; LARGE: Relocations [
36 ; LARGE: Section {{.*}} .rela.text {
37 ; LARGE-NEXT: 0x{{[0-9,A-F]+}} R_PPC64_TOC16_HA [[SYM1:[^ ]+]]
38 ; LARGE-NEXT: 0x{{[0-9,A-F]+}} R_PPC64_TOC16_LO_DS [[SYM1]]
40 @test_fn_static.si = internal global i32 0, align 4
42 define signext i32 @test_fn_static() nounwind {
44 %0 = load i32, i32* @test_fn_static.si, align 4
45 %inc = add nsw i32 %0, 1
46 store i32 %inc, i32* @test_fn_static.si, align 4
50 ; Verify generation of R_PPC64_TOC16_HA and R_PPC64_TOC16_LO for
51 ; accessing function-scoped variable si.
53 ; MEDIUM-NEXT: 0x{{[0-9,A-F]+}} R_PPC64_TOC16_HA [[SYM2:[^ ]+]]
54 ; MEDIUM-NEXT: 0x{{[0-9,A-F]+}} R_PPC64_TOC16_LO [[SYM2]]
56 ; Verify generation of R_PPC64_TOC16_HA and R_PPC64_TOC16_LO_DS for
57 ; accessing function-scoped variable si.
59 ; LARGE-NEXT: 0x{{[0-9,A-F]+}} R_PPC64_TOC16_HA [[SYM2:[^ ]+]]
60 ; LARGE-NEXT: 0x{{[0-9,A-F]+}} R_PPC64_TOC16_LO_DS [[SYM2]]
62 @gi = global i32 5, align 4
64 define signext i32 @test_file_static() nounwind {
66 %0 = load i32, i32* @gi, align 4
67 %inc = add nsw i32 %0, 1
68 store i32 %inc, i32* @gi, align 4
72 ; Verify generation of R_PPC64_TOC16_HA and R_PPC64_TOC16_LO for
73 ; accessing file-scope variable gi.
75 ; MEDIUM-NEXT: 0x{{[0-9,A-F]+}} R_PPC64_TOC16_HA [[SYM3:[^ ]+]]
76 ; MEDIUM-NEXT: 0x{{[0-9,A-F]+}} R_PPC64_TOC16_LO [[SYM3]]
78 ; Verify generation of R_PPC64_TOC16_HA and R_PPC64_TOC16_LO_DS for
79 ; accessing file-scope variable gi.
81 ; LARGE-NEXT: 0x{{[0-9,A-F]+}} R_PPC64_TOC16_HA [[SYM3:[^ ]+]]
82 ; LARGE-NEXT: 0x{{[0-9,A-F]+}} R_PPC64_TOC16_LO_DS [[SYM3]]
84 define double @test_double_const() nounwind {
86 ret double 0x3F4FD4920B498CF0
89 ; Verify generation of R_PPC64_TOC16_HA and R_PPC64_TOC16_LO for
90 ; accessing a constant.
92 ; MEDIUM-NEXT: 0x{{[0-9,A-F]+}} R_PPC64_TOC16_HA [[SYM4:[^ ]+]]
93 ; MEDIUM-NEXT: 0x{{[0-9,A-F]+}} R_PPC64_TOC16_LO [[SYM4]]
95 ; Verify generation of R_PPC64_TOC16_HA and R_PPC64_TOC16_LO_DS for
96 ; accessing a constant.
98 ; LARGE-NEXT: 0x{{[0-9,A-F]+}} R_PPC64_TOC16_HA [[SYM4:[^ ]+]]
99 ; LARGE-NEXT: 0x{{[0-9,A-F]+}} R_PPC64_TOC16_LO_DS [[SYM4]]
101 @ti = common global i32 0, align 4
103 define signext i32 @test_tentative() nounwind {
105 %0 = load i32, i32* @ti, align 4
106 %inc = add nsw i32 %0, 1
107 store i32 %inc, i32* @ti, align 4
111 ; Verify generation of R_PPC64_TOC16_HA and R_PPC64_TOC16_LO_DS for
112 ; accessing tentatively declared variable ti.
114 ; MEDIUM-NEXT: 0x{{[0-9,A-F]+}} R_PPC64_TOC16_HA [[SYM6:[^ ]+]]
115 ; MEDIUM-NEXT: 0x{{[0-9,A-F]+}} R_PPC64_TOC16_LO_DS [[SYM6]]
117 ; LARGE-NEXT: 0x{{[0-9,A-F]+}} R_PPC64_TOC16_HA [[SYM6:[^ ]+]]
118 ; LARGE-NEXT: 0x{{[0-9,A-F]+}} R_PPC64_TOC16_LO_DS [[SYM6]]
120 define i8* @test_fnaddr() nounwind {
122 %func = alloca i32 (i32)*, align 8
123 store i32 (i32)* @foo, i32 (i32)** %func, align 8
124 %0 = load i32 (i32)*, i32 (i32)** %func, align 8
125 %1 = bitcast i32 (i32)* %0 to i8*
129 declare signext i32 @foo(i32 signext)
131 ; Verify generation of R_PPC64_TOC16_HA and R_PPC64_TOC16_LO_DS for
132 ; accessing function address foo.
134 ; MEDIUM-NEXT: 0x{{[0-9,A-F]+}} R_PPC64_TOC16_HA [[SYM7:[^ ]+]]
135 ; MEDIUM-NEXT: 0x{{[0-9,A-F]+}} R_PPC64_TOC16_LO_DS [[SYM7]]
137 ; LARGE-NEXT: 0x{{[0-9,A-F]+}} R_PPC64_TOC16_HA [[SYM7:[^ ]+]]
138 ; LARGE-NEXT: 0x{{[0-9,A-F]+}} R_PPC64_TOC16_LO_DS [[SYM7]]
141 define signext i32 @test_jump_table(i32 signext %i) nounwind {
143 %i.addr = alloca i32, align 4
144 store i32 %i, i32* %i.addr, align 4
145 %0 = load i32, i32* %i.addr, align 4
146 switch i32 %0, label %sw.default [
153 sw.default: ; preds = %entry
156 sw.bb: ; preds = %entry
157 %1 = load i32, i32* %i.addr, align 4
158 %mul = mul nsw i32 %1, 7
159 store i32 %mul, i32* %i.addr, align 4
162 sw.bb1: ; preds = %entry, %sw.bb
163 %2 = load i32, i32* %i.addr, align 4
164 %dec = add nsw i32 %2, -1
165 store i32 %dec, i32* %i.addr, align 4
168 sw.bb2: ; preds = %entry, %sw.bb1
169 %3 = load i32, i32* %i.addr, align 4
170 %add = add nsw i32 %3, 3
171 store i32 %add, i32* %i.addr, align 4
174 sw.bb3: ; preds = %entry, %sw.bb2
175 %4 = load i32, i32* %i.addr, align 4
177 store i32 %shl, i32* %i.addr, align 4
180 sw.epilog: ; preds = %sw.bb3, %sw.default
181 %5 = load i32, i32* %i.addr, align 4
185 ; Verify generation of R_PPC64_TOC16_HA and R_PPC64_TOC16_LO_DS for
186 ; accessing a jump table address.
188 ; MEDIUM-JT: Relocations [
189 ; MEDIUM-JT: Section ({{.*}}) .rela.text {
190 ; MEDIUM-JT-NEXT: 0x{{[0-9,A-F]+}} R_PPC64_TOC16_HA [[SYM:[^ ]+]]
191 ; MEDIUM-JT-NEXT: 0x{{[0-9,A-F]+}} R_PPC64_TOC16_LO_DS [[SYM]]
193 ; LARGE-JT: Relocations [
194 ; LARGE-JT: Section ({{.*}}) .rela.text {
195 ; LARGE-JT-NEXT: 0x{{[0-9,A-F]+}} R_PPC64_TOC16_HA [[SYM:[^ ]+]]
196 ; LARGE-JT-NEXT: 0x{{[0-9,A-F]+}} R_PPC64_TOC16_LO_DS [[SYM]]