1 ; RUN: llc < %s -march=ppc64 -mcpu=a2q | FileCheck %s
2 target triple = "powerpc64-bgq-linux"
4 @Q = constant <4 x i1> <i1 0, i1 undef, i1 1, i1 1>, align 16
5 @R = global <4 x i1> <i1 0, i1 0, i1 0, i1 0>, align 16
7 define <4 x float> @test1(<4 x float> %a, <4 x float> %b, <4 x i1> %c) nounwind readnone {
9 %r = select <4 x i1> %c, <4 x float> %a, <4 x float> %b
13 ; CHECK: qvfsel 1, 3, 1, 2
17 define <4 x float> @test2(<4 x float> %a, <4 x float> %b, i1 %c1, i1 %c2, i1 %c3, i1 %c4) nounwind readnone {
19 %v = insertelement <4 x i1> undef, i1 %c1, i32 0
20 %v2 = insertelement <4 x i1> %v, i1 %c2, i32 1
21 %v3 = insertelement <4 x i1> %v2, i1 %c3, i32 2
22 %v4 = insertelement <4 x i1> %v3, i1 %c4, i32 3
23 %r = select <4 x i1> %v4, <4 x float> %a, <4 x float> %b
28 ; CHECK-DAG: qvlfiwzx [[REG1:[0-9]+]],
29 ; CHECK-DAG: qvlfdx [[REG2:[0-9]+]],
30 ; CHECK-DAG: qvfcfidu [[REG3:[0-9]+]], [[REG1]]
31 ; CHECK: qvfcmpeq [[REG4:[0-9]+]], [[REG3]], [[REG2]]
32 ; CHECK: qvfsel 1, [[REG4]], 1, 2
36 define <4 x i1> @test3(<4 x i1> %a) nounwind readnone {
38 %v = and <4 x i1> %a, <i1 0, i1 undef, i1 1, i1 1>
42 ; CHECK: qvlfsx [[REG:[0-9]+]],
43 ; qvflogical 1, 1, [[REG]], 1
47 define <4 x i1> @test4(<4 x i1> %a) nounwind {
49 %q = load <4 x i1>, <4 x i1>* @Q, align 16
50 %v = and <4 x i1> %a, %q
55 ; CHECK-DAG: qvlfdx [[REG1:[0-9]+]],
57 ; CHECK-DAG: qvlfiwzx [[REG2:[0-9]+]],
58 ; CHECK-DAG: qvfcfidu [[REG3:[0-9]+]], [[REG2]]
59 ; CHECK: qvfcmpeq [[REG4:[0-9]+]], [[REG3]], [[REG1]]
60 ; CHECK: qvflogical 1, 1, [[REG4]], 1
64 define void @test5(<4 x i1> %a) nounwind {
66 store <4 x i1> %a, <4 x i1>* @R
70 ; CHECK: qvlfdx [[REG1:[0-9]+]],
71 ; CHECK: qvfmadd [[REG2:[0-9]+]], 1, [[REG1]], [[REG1]]
72 ; CHECK: qvfctiwu [[REG3:[0-9]+]], [[REG2]]
73 ; CHECK: qvstfiwx [[REG3]],
79 define i1 @test6(<4 x i1> %a) nounwind {
81 %r = extractelement <4 x i1> %a, i32 2
85 ; CHECK: qvlfdx [[REG1:[0-9]+]],
86 ; CHECK: qvfmadd [[REG2:[0-9]+]], 1, [[REG1]], [[REG1]]
87 ; CHECK: qvfctiwu [[REG3:[0-9]+]], [[REG2]]
88 ; CHECK: qvstfiwx [[REG3]],
93 define i1 @test7(<4 x i1> %a) nounwind {
95 %r = extractelement <4 x i1> %a, i32 2
96 %s = extractelement <4 x i1> %a, i32 3
100 ; CHECK-LABEL: @test7
101 ; CHECK: qvlfdx [[REG1:[0-9]+]],
102 ; CHECK: qvfmadd [[REG2:[0-9]+]], 1, [[REG1]], [[REG1]]
103 ; CHECK: qvfctiwu [[REG3:[0-9]+]], [[REG2]]
104 ; CHECK: qvstfiwx [[REG3]],
105 ; CHECK-DAG: lwz [[REG4:[0-9]+]],
106 ; FIXME: We're storing the vector twice, and that's silly.
107 ; CHECK-DAG: qvstfiwx [[REG3]],
108 ; CHECK: lwz [[REG5:[0-9]+]],
113 define i1 @test8(<3 x i1> %a) nounwind {
115 %r = extractelement <3 x i1> %a, i32 2
118 ; CHECK-LABEL: @test8
119 ; CHECK: qvlfdx [[REG1:[0-9]+]],
120 ; CHECK: qvfmadd [[REG2:[0-9]+]], 1, [[REG1]], [[REG1]]
121 ; CHECK: qvfctiwu [[REG3:[0-9]+]], [[REG2]]
122 ; CHECK: qvstfiwx [[REG3]],
127 define <3 x float> @test9(<3 x float> %a, <3 x float> %b, i1 %c1, i1 %c2, i1 %c3) nounwind readnone {
129 %v = insertelement <3 x i1> undef, i1 %c1, i32 0
130 %v2 = insertelement <3 x i1> %v, i1 %c2, i32 1
131 %v3 = insertelement <3 x i1> %v2, i1 %c3, i32 2
132 %r = select <3 x i1> %v3, <3 x float> %a, <3 x float> %b
135 ; CHECK-LABEL: @test9
137 ; CHECK-DAG: qvlfiwzx [[REG1:[0-9]+]],
138 ; CHECK-DAG: qvlfdx [[REG2:[0-9]+]],
139 ; CHECK-DAG: qvfcfidu [[REG3:[0-9]+]], [[REG1]]
140 ; CHECK: qvfcmpeq [[REG4:[0-9]+]], [[REG3]], [[REG2]]
141 ; CHECK: qvfsel 1, [[REG4]], 1, 2