1 ; RUN: llc < %s -march=ppc64 -mcpu=a2q | FileCheck %s
2 target triple = "powerpc64-bgq-linux"
4 @Q = constant <4 x i1> <i1 0, i1 undef, i1 1, i1 1>, align 16
5 @R = global <4 x i1> <i1 0, i1 0, i1 0, i1 0>, align 16
7 define <4 x double> @test1(<4 x double> %a, <4 x double> %b, <4 x i1> %c) nounwind readnone {
9 %r = select <4 x i1> %c, <4 x double> %a, <4 x double> %b
13 ; CHECK: qvfsel 1, 3, 1, 2
17 define <4 x double> @test2(<4 x double> %a, <4 x double> %b, i1 %c1, i1 %c2, i1 %c3, i1 %c4) nounwind readnone {
19 %v = insertelement <4 x i1> undef, i1 %c1, i32 0
20 %v2 = insertelement <4 x i1> %v, i1 %c2, i32 1
21 %v3 = insertelement <4 x i1> %v2, i1 %c3, i32 2
22 %v4 = insertelement <4 x i1> %v3, i1 %c4, i32 3
23 %r = select <4 x i1> %v4, <4 x double> %a, <4 x double> %b
28 ; FIXME: This load/store sequence is unnecessary.
32 ; CHECK-DAG: qvlfiwzx [[REG1:[0-9]+]],
33 ; CHECK-DAG: qvlfdx [[REG2:[0-9]+]],
34 ; CHECK-DAG: qvfcfidu [[REG3:[0-9]+]], [[REG1]]
35 ; CHECK: qvfcmpeq [[REG4:[0-9]+]], [[REG3]], [[REG2]]
36 ; CHECK: qvfsel 1, [[REG4]], 1, 2
40 define <4 x i1> @test3(<4 x i1> %a) nounwind readnone {
42 %v = and <4 x i1> %a, <i1 0, i1 undef, i1 1, i1 1>
46 ; CHECK: qvlfsx [[REG:[0-9]+]],
47 ; qvflogical 1, 1, [[REG]], 1
51 define <4 x i1> @test4(<4 x i1> %a) nounwind {
53 %q = load <4 x i1>* @Q, align 16
54 %v = and <4 x i1> %a, %q
59 ; CHECK-DAG: qvlfdx [[REG1:[0-9]+]],
61 ; CHECK-DAG: qvlfiwzx [[REG2:[0-9]+]],
62 ; CHECK-DAG: qvfcfidu [[REG3:[0-9]+]], [[REG2]]
63 ; CHECK: qvfcmpeq [[REG4:[0-9]+]], [[REG3]], [[REG1]]
64 ; CHECK: qvflogical 1, 1, [[REG4]], 1
68 define void @test5(<4 x i1> %a) nounwind {
70 store <4 x i1> %a, <4 x i1>* @R
74 ; CHECK: qvlfdx [[REG1:[0-9]+]],
75 ; CHECK: qvfmadd [[REG2:[0-9]+]], 1, [[REG1]], [[REG1]]
76 ; CHECK: qvfctiwu [[REG3:[0-9]+]], [[REG2]]
77 ; CHECK: qvstfiwx [[REG3]],
83 define i1 @test6(<4 x i1> %a) nounwind {
85 %r = extractelement <4 x i1> %a, i32 2
89 ; CHECK: qvlfdx [[REG1:[0-9]+]],
90 ; CHECK: qvfmadd [[REG2:[0-9]+]], 1, [[REG1]], [[REG1]]
91 ; CHECK: qvfctiwu [[REG3:[0-9]+]], [[REG2]]
92 ; CHECK: qvstfiwx [[REG3]],
97 define i1 @test7(<4 x i1> %a) nounwind {
99 %r = extractelement <4 x i1> %a, i32 2
100 %s = extractelement <4 x i1> %a, i32 3
104 ; CHECK-LABEL: @test7
105 ; CHECK: qvlfdx [[REG1:[0-9]+]],
106 ; CHECK: qvfmadd [[REG2:[0-9]+]], 1, [[REG1]], [[REG1]]
107 ; CHECK: qvfctiwu [[REG3:[0-9]+]], [[REG2]]
108 ; CHECK: qvstfiwx [[REG3]],
109 ; CHECK-DAG: lwz [[REG4:[0-9]+]],
110 ; FIXME: We're storing the vector twice, and that's silly.
111 ; CHECK-DAG: qvstfiwx [[REG3]],
112 ; CHECK-DAG: lwz [[REG5:[0-9]+]],
117 define i1 @test8(<3 x i1> %a) nounwind {
119 %r = extractelement <3 x i1> %a, i32 2
122 ; CHECK-LABEL: @test8
123 ; CHECK: qvlfdx [[REG1:[0-9]+]],
124 ; CHECK: qvfmadd [[REG2:[0-9]+]], 1, [[REG1]], [[REG1]]
125 ; CHECK: qvfctiwu [[REG3:[0-9]+]], [[REG2]]
126 ; CHECK: qvstfiwx [[REG3]],
131 define <3 x double> @test9(<3 x double> %a, <3 x double> %b, i1 %c1, i1 %c2, i1 %c3) nounwind readnone {
133 %v = insertelement <3 x i1> undef, i1 %c1, i32 0
134 %v2 = insertelement <3 x i1> %v, i1 %c2, i32 1
135 %v3 = insertelement <3 x i1> %v2, i1 %c3, i32 2
136 %r = select <3 x i1> %v3, <3 x double> %a, <3 x double> %b
139 ; CHECK-LABEL: @test9
141 ; FIXME: This load/store sequence is unnecessary.
145 ; CHECK-DAG: qvlfiwzx [[REG1:[0-9]+]],
146 ; CHECK-DAG: qvlfdx [[REG2:[0-9]+]],
147 ; CHECK-DAG: qvfcfidu [[REG3:[0-9]+]], [[REG1]]
148 ; CHECK: qvfcmpeq [[REG4:[0-9]+]], [[REG3]], [[REG2]]
149 ; CHECK: qvfsel 1, [[REG4]], 1, 2