1 ; RUN: llc < %s | FileCheck %s
2 target datalayout = "E-m:e-i64:64-n32:64"
3 target triple = "powerpc64-unknown-linux-gnu"
5 ; FIXME: We should check the operands to the cr* logical operation itself, but
6 ; unfortunately, FileCheck does not yet understand how to do arithmetic, so we
7 ; can't do so without introducing a register-allocation dependency.
9 define signext i32 @testi32slt(i32 signext %c1, i32 signext %c2, i32 signext %c3, i32 signext %c4, i32 signext %a1, i32 signext %a2) #0 {
11 %cmp1 = icmp eq i32 %c3, %c4
12 %cmp3tmp = icmp eq i32 %c1, %c2
13 %cmp3 = icmp slt i1 %cmp3tmp, %cmp1
14 %cond = select i1 %cmp3, i32 %a1, i32 %a2
17 ; CHECK-LABEL: @testi32slt
18 ; CHECK-DAG: cmpw {{[0-9]+}}, 5, 6
19 ; CHECK-DAG: cmpw {{[0-9]+}}, 3, 4
20 ; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
21 ; CHECK: isel 3, 7, 8, [[REG1]]
25 define signext i32 @testi32ult(i32 signext %c1, i32 signext %c2, i32 signext %c3, i32 signext %c4, i32 signext %a1, i32 signext %a2) #0 {
27 %cmp1 = icmp eq i32 %c3, %c4
28 %cmp3tmp = icmp eq i32 %c1, %c2
29 %cmp3 = icmp ult i1 %cmp3tmp, %cmp1
30 %cond = select i1 %cmp3, i32 %a1, i32 %a2
33 ; CHECK-LABEL: @testi32ult
34 ; CHECK-DAG: cmpw {{[0-9]+}}, 5, 6
35 ; CHECK-DAG: cmpw {{[0-9]+}}, 3, 4
36 ; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
37 ; CHECK: isel 3, 7, 8, [[REG1]]
41 define signext i32 @testi32sle(i32 signext %c1, i32 signext %c2, i32 signext %c3, i32 signext %c4, i32 signext %a1, i32 signext %a2) #0 {
43 %cmp1 = icmp eq i32 %c3, %c4
44 %cmp3tmp = icmp eq i32 %c1, %c2
45 %cmp3 = icmp sle i1 %cmp3tmp, %cmp1
46 %cond = select i1 %cmp3, i32 %a1, i32 %a2
49 ; CHECK-LABEL: @testi32sle
50 ; CHECK-DAG: cmpw {{[0-9]+}}, 5, 6
51 ; CHECK-DAG: cmpw {{[0-9]+}}, 3, 4
52 ; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
53 ; CHECK: isel 3, 7, 8, [[REG1]]
57 define signext i32 @testi32ule(i32 signext %c1, i32 signext %c2, i32 signext %c3, i32 signext %c4, i32 signext %a1, i32 signext %a2) #0 {
59 %cmp1 = icmp eq i32 %c3, %c4
60 %cmp3tmp = icmp eq i32 %c1, %c2
61 %cmp3 = icmp ule i1 %cmp3tmp, %cmp1
62 %cond = select i1 %cmp3, i32 %a1, i32 %a2
65 ; CHECK-LABEL: @testi32ule
66 ; CHECK-DAG: cmpw {{[0-9]+}}, 5, 6
67 ; CHECK-DAG: cmpw {{[0-9]+}}, 3, 4
68 ; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
69 ; CHECK: isel 3, 7, 8, [[REG1]]
73 define signext i32 @testi32eq(i32 signext %c1, i32 signext %c2, i32 signext %c3, i32 signext %c4, i32 signext %a1, i32 signext %a2) #0 {
75 %cmp1 = icmp eq i32 %c3, %c4
76 %cmp3tmp = icmp eq i32 %c1, %c2
77 %cmp3 = icmp eq i1 %cmp3tmp, %cmp1
78 %cond = select i1 %cmp3, i32 %a1, i32 %a2
81 ; CHECK-LABEL: @testi32eq
82 ; CHECK-DAG: cmpw {{[0-9]+}}, 5, 6
83 ; CHECK-DAG: cmpw {{[0-9]+}}, 3, 4
84 ; CHECK: creqv [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
85 ; CHECK: isel 3, 7, 8, [[REG1]]
89 define signext i32 @testi32sge(i32 signext %c1, i32 signext %c2, i32 signext %c3, i32 signext %c4, i32 signext %a1, i32 signext %a2) #0 {
91 %cmp1 = icmp eq i32 %c3, %c4
92 %cmp3tmp = icmp eq i32 %c1, %c2
93 %cmp3 = icmp sge i1 %cmp3tmp, %cmp1
94 %cond = select i1 %cmp3, i32 %a1, i32 %a2
97 ; CHECK-LABEL: @testi32sge
98 ; CHECK-DAG: cmpw {{[0-9]+}}, 5, 6
99 ; CHECK-DAG: cmpw {{[0-9]+}}, 3, 4
100 ; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
101 ; CHECK: isel 3, 7, 8, [[REG1]]
105 define signext i32 @testi32uge(i32 signext %c1, i32 signext %c2, i32 signext %c3, i32 signext %c4, i32 signext %a1, i32 signext %a2) #0 {
107 %cmp1 = icmp eq i32 %c3, %c4
108 %cmp3tmp = icmp eq i32 %c1, %c2
109 %cmp3 = icmp uge i1 %cmp3tmp, %cmp1
110 %cond = select i1 %cmp3, i32 %a1, i32 %a2
113 ; CHECK-LABEL: @testi32uge
114 ; CHECK-DAG: cmpw {{[0-9]+}}, 5, 6
115 ; CHECK-DAG: cmpw {{[0-9]+}}, 3, 4
116 ; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
117 ; CHECK: isel 3, 7, 8, [[REG1]]
121 define signext i32 @testi32sgt(i32 signext %c1, i32 signext %c2, i32 signext %c3, i32 signext %c4, i32 signext %a1, i32 signext %a2) #0 {
123 %cmp1 = icmp eq i32 %c3, %c4
124 %cmp3tmp = icmp eq i32 %c1, %c2
125 %cmp3 = icmp sgt i1 %cmp3tmp, %cmp1
126 %cond = select i1 %cmp3, i32 %a1, i32 %a2
129 ; CHECK-LABEL: @testi32sgt
130 ; CHECK-DAG: cmpw {{[0-9]+}}, 5, 6
131 ; CHECK-DAG: cmpw {{[0-9]+}}, 3, 4
132 ; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
133 ; CHECK: isel 3, 7, 8, [[REG1]]
137 define signext i32 @testi32ugt(i32 signext %c1, i32 signext %c2, i32 signext %c3, i32 signext %c4, i32 signext %a1, i32 signext %a2) #0 {
139 %cmp1 = icmp eq i32 %c3, %c4
140 %cmp3tmp = icmp eq i32 %c1, %c2
141 %cmp3 = icmp ugt i1 %cmp3tmp, %cmp1
142 %cond = select i1 %cmp3, i32 %a1, i32 %a2
145 ; CHECK-LABEL: @testi32ugt
146 ; CHECK-DAG: cmpw {{[0-9]+}}, 5, 6
147 ; CHECK-DAG: cmpw {{[0-9]+}}, 3, 4
148 ; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
149 ; CHECK: isel 3, 7, 8, [[REG1]]
153 define signext i32 @testi32ne(i32 signext %c1, i32 signext %c2, i32 signext %c3, i32 signext %c4, i32 signext %a1, i32 signext %a2) #0 {
155 %cmp1 = icmp eq i32 %c3, %c4
156 %cmp3tmp = icmp eq i32 %c1, %c2
157 %cmp3 = icmp ne i1 %cmp3tmp, %cmp1
158 %cond = select i1 %cmp3, i32 %a1, i32 %a2
161 ; CHECK-LABEL: @testi32ne
162 ; CHECK-DAG: cmpw {{[0-9]+}}, 5, 6
163 ; CHECK-DAG: cmpw {{[0-9]+}}, 3, 4
164 ; CHECK: crxor [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
165 ; CHECK: isel 3, 7, 8, [[REG1]]
169 define i64 @testi64slt(i64 %c1, i64 %c2, i64 %c3, i64 %c4, i64 %a1, i64 %a2) #0 {
171 %cmp1 = icmp eq i64 %c3, %c4
172 %cmp3tmp = icmp eq i64 %c1, %c2
173 %cmp3 = icmp slt i1 %cmp3tmp, %cmp1
174 %cond = select i1 %cmp3, i64 %a1, i64 %a2
177 ; CHECK-LABEL: @testi64slt
178 ; CHECK-DAG: cmpd {{([0-9]+, )?}}5, 6
179 ; CHECK-DAG: cmpd {{([0-9]+, )?}}3, 4
180 ; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
181 ; CHECK: isel 3, 7, 8, [[REG1]]
185 define i64 @testi64ult(i64 %c1, i64 %c2, i64 %c3, i64 %c4, i64 %a1, i64 %a2) #0 {
187 %cmp1 = icmp eq i64 %c3, %c4
188 %cmp3tmp = icmp eq i64 %c1, %c2
189 %cmp3 = icmp ult i1 %cmp3tmp, %cmp1
190 %cond = select i1 %cmp3, i64 %a1, i64 %a2
193 ; CHECK-LABEL: @testi64ult
194 ; CHECK-DAG: cmpd {{([0-9]+, )?}}5, 6
195 ; CHECK-DAG: cmpd {{([0-9]+, )?}}3, 4
196 ; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
197 ; CHECK: isel 3, 7, 8, [[REG1]]
201 define i64 @testi64sle(i64 %c1, i64 %c2, i64 %c3, i64 %c4, i64 %a1, i64 %a2) #0 {
203 %cmp1 = icmp eq i64 %c3, %c4
204 %cmp3tmp = icmp eq i64 %c1, %c2
205 %cmp3 = icmp sle i1 %cmp3tmp, %cmp1
206 %cond = select i1 %cmp3, i64 %a1, i64 %a2
209 ; CHECK-LABEL: @testi64sle
210 ; CHECK-DAG: cmpd {{([0-9]+, )?}}5, 6
211 ; CHECK-DAG: cmpd {{([0-9]+, )?}}3, 4
212 ; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
213 ; CHECK: isel 3, 7, 8, [[REG1]]
217 define i64 @testi64ule(i64 %c1, i64 %c2, i64 %c3, i64 %c4, i64 %a1, i64 %a2) #0 {
219 %cmp1 = icmp eq i64 %c3, %c4
220 %cmp3tmp = icmp eq i64 %c1, %c2
221 %cmp3 = icmp ule i1 %cmp3tmp, %cmp1
222 %cond = select i1 %cmp3, i64 %a1, i64 %a2
225 ; CHECK-LABEL: @testi64ule
226 ; CHECK-DAG: cmpd {{([0-9]+, )?}}5, 6
227 ; CHECK-DAG: cmpd {{([0-9]+, )?}}3, 4
228 ; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
229 ; CHECK: isel 3, 7, 8, [[REG1]]
233 define i64 @testi64eq(i64 %c1, i64 %c2, i64 %c3, i64 %c4, i64 %a1, i64 %a2) #0 {
235 %cmp1 = icmp eq i64 %c3, %c4
236 %cmp3tmp = icmp eq i64 %c1, %c2
237 %cmp3 = icmp eq i1 %cmp3tmp, %cmp1
238 %cond = select i1 %cmp3, i64 %a1, i64 %a2
241 ; CHECK-LABEL: @testi64eq
242 ; CHECK-DAG: cmpd {{([0-9]+, )?}}5, 6
243 ; CHECK-DAG: cmpd {{([0-9]+, )?}}3, 4
244 ; CHECK: creqv [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
245 ; CHECK: isel 3, 7, 8, [[REG1]]
249 define i64 @testi64sge(i64 %c1, i64 %c2, i64 %c3, i64 %c4, i64 %a1, i64 %a2) #0 {
251 %cmp1 = icmp eq i64 %c3, %c4
252 %cmp3tmp = icmp eq i64 %c1, %c2
253 %cmp3 = icmp sge i1 %cmp3tmp, %cmp1
254 %cond = select i1 %cmp3, i64 %a1, i64 %a2
257 ; CHECK-LABEL: @testi64sge
258 ; CHECK-DAG: cmpd {{([0-9]+, )?}}5, 6
259 ; CHECK-DAG: cmpd {{([0-9]+, )?}}3, 4
260 ; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
261 ; CHECK: isel 3, 7, 8, [[REG1]]
265 define i64 @testi64uge(i64 %c1, i64 %c2, i64 %c3, i64 %c4, i64 %a1, i64 %a2) #0 {
267 %cmp1 = icmp eq i64 %c3, %c4
268 %cmp3tmp = icmp eq i64 %c1, %c2
269 %cmp3 = icmp uge i1 %cmp3tmp, %cmp1
270 %cond = select i1 %cmp3, i64 %a1, i64 %a2
273 ; CHECK-LABEL: @testi64uge
274 ; CHECK-DAG: cmpd {{([0-9]+, )?}}5, 6
275 ; CHECK-DAG: cmpd {{([0-9]+, )?}}3, 4
276 ; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
277 ; CHECK: isel 3, 7, 8, [[REG1]]
281 define i64 @testi64sgt(i64 %c1, i64 %c2, i64 %c3, i64 %c4, i64 %a1, i64 %a2) #0 {
283 %cmp1 = icmp eq i64 %c3, %c4
284 %cmp3tmp = icmp eq i64 %c1, %c2
285 %cmp3 = icmp sgt i1 %cmp3tmp, %cmp1
286 %cond = select i1 %cmp3, i64 %a1, i64 %a2
289 ; CHECK-LABEL: @testi64sgt
290 ; CHECK-DAG: cmpd {{([0-9]+, )?}}5, 6
291 ; CHECK-DAG: cmpd {{([0-9]+, )?}}3, 4
292 ; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
293 ; CHECK: isel 3, 7, 8, [[REG1]]
297 define i64 @testi64ugt(i64 %c1, i64 %c2, i64 %c3, i64 %c4, i64 %a1, i64 %a2) #0 {
299 %cmp1 = icmp eq i64 %c3, %c4
300 %cmp3tmp = icmp eq i64 %c1, %c2
301 %cmp3 = icmp ugt i1 %cmp3tmp, %cmp1
302 %cond = select i1 %cmp3, i64 %a1, i64 %a2
305 ; CHECK-LABEL: @testi64ugt
306 ; CHECK-DAG: cmpd {{([0-9]+, )?}}5, 6
307 ; CHECK-DAG: cmpd {{([0-9]+, )?}}3, 4
308 ; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
309 ; CHECK: isel 3, 7, 8, [[REG1]]
313 define i64 @testi64ne(i64 %c1, i64 %c2, i64 %c3, i64 %c4, i64 %a1, i64 %a2) #0 {
315 %cmp1 = icmp eq i64 %c3, %c4
316 %cmp3tmp = icmp eq i64 %c1, %c2
317 %cmp3 = icmp ne i1 %cmp3tmp, %cmp1
318 %cond = select i1 %cmp3, i64 %a1, i64 %a2
321 ; CHECK-LABEL: @testi64ne
322 ; CHECK-DAG: cmpd {{([0-9]+, )?}}5, 6
323 ; CHECK-DAG: cmpd {{([0-9]+, )?}}3, 4
324 ; CHECK: crxor [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
325 ; CHECK: isel 3, 7, 8, [[REG1]]
329 define float @testfloatslt(float %c1, float %c2, float %c3, float %c4, float %a1, float %a2) #0 {
331 %cmp1 = fcmp oeq float %c3, %c4
332 %cmp3tmp = fcmp oeq float %c1, %c2
333 %cmp3 = icmp slt i1 %cmp3tmp, %cmp1
334 %cond = select i1 %cmp3, float %a1, float %a2
337 ; CHECK-LABEL: @testfloatslt
338 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
339 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
340 ; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
341 ; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
348 define float @testfloatult(float %c1, float %c2, float %c3, float %c4, float %a1, float %a2) #0 {
350 %cmp1 = fcmp oeq float %c3, %c4
351 %cmp3tmp = fcmp oeq float %c1, %c2
352 %cmp3 = icmp ult i1 %cmp3tmp, %cmp1
353 %cond = select i1 %cmp3, float %a1, float %a2
356 ; CHECK-LABEL: @testfloatult
357 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
358 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
359 ; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
360 ; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
367 define float @testfloatsle(float %c1, float %c2, float %c3, float %c4, float %a1, float %a2) #0 {
369 %cmp1 = fcmp oeq float %c3, %c4
370 %cmp3tmp = fcmp oeq float %c1, %c2
371 %cmp3 = icmp sle i1 %cmp3tmp, %cmp1
372 %cond = select i1 %cmp3, float %a1, float %a2
375 ; CHECK-LABEL: @testfloatsle
376 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
377 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
378 ; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
379 ; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
386 define float @testfloatule(float %c1, float %c2, float %c3, float %c4, float %a1, float %a2) #0 {
388 %cmp1 = fcmp oeq float %c3, %c4
389 %cmp3tmp = fcmp oeq float %c1, %c2
390 %cmp3 = icmp ule i1 %cmp3tmp, %cmp1
391 %cond = select i1 %cmp3, float %a1, float %a2
394 ; CHECK-LABEL: @testfloatule
395 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
396 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
397 ; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
398 ; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
405 define float @testfloateq(float %c1, float %c2, float %c3, float %c4, float %a1, float %a2) #0 {
407 %cmp1 = fcmp oeq float %c3, %c4
408 %cmp3tmp = fcmp oeq float %c1, %c2
409 %cmp3 = icmp eq i1 %cmp3tmp, %cmp1
410 %cond = select i1 %cmp3, float %a1, float %a2
413 ; CHECK-LABEL: @testfloateq
414 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
415 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
416 ; CHECK: creqv [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
417 ; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
424 define float @testfloatsge(float %c1, float %c2, float %c3, float %c4, float %a1, float %a2) #0 {
426 %cmp1 = fcmp oeq float %c3, %c4
427 %cmp3tmp = fcmp oeq float %c1, %c2
428 %cmp3 = icmp sge i1 %cmp3tmp, %cmp1
429 %cond = select i1 %cmp3, float %a1, float %a2
432 ; CHECK-LABEL: @testfloatsge
433 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
434 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
435 ; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
436 ; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
443 define float @testfloatuge(float %c1, float %c2, float %c3, float %c4, float %a1, float %a2) #0 {
445 %cmp1 = fcmp oeq float %c3, %c4
446 %cmp3tmp = fcmp oeq float %c1, %c2
447 %cmp3 = icmp uge i1 %cmp3tmp, %cmp1
448 %cond = select i1 %cmp3, float %a1, float %a2
451 ; CHECK-LABEL: @testfloatuge
452 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
453 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
454 ; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
455 ; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
462 define float @testfloatsgt(float %c1, float %c2, float %c3, float %c4, float %a1, float %a2) #0 {
464 %cmp1 = fcmp oeq float %c3, %c4
465 %cmp3tmp = fcmp oeq float %c1, %c2
466 %cmp3 = icmp sgt i1 %cmp3tmp, %cmp1
467 %cond = select i1 %cmp3, float %a1, float %a2
470 ; CHECK-LABEL: @testfloatsgt
471 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
472 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
473 ; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
474 ; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
481 define float @testfloatugt(float %c1, float %c2, float %c3, float %c4, float %a1, float %a2) #0 {
483 %cmp1 = fcmp oeq float %c3, %c4
484 %cmp3tmp = fcmp oeq float %c1, %c2
485 %cmp3 = icmp ugt i1 %cmp3tmp, %cmp1
486 %cond = select i1 %cmp3, float %a1, float %a2
489 ; CHECK-LABEL: @testfloatugt
490 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
491 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
492 ; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
493 ; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
500 define float @testfloatne(float %c1, float %c2, float %c3, float %c4, float %a1, float %a2) #0 {
502 %cmp1 = fcmp oeq float %c3, %c4
503 %cmp3tmp = fcmp oeq float %c1, %c2
504 %cmp3 = icmp ne i1 %cmp3tmp, %cmp1
505 %cond = select i1 %cmp3, float %a1, float %a2
508 ; CHECK-LABEL: @testfloatne
509 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
510 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
511 ; CHECK: crxor [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
512 ; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
519 define double @testdoubleslt(double %c1, double %c2, double %c3, double %c4, double %a1, double %a2) #0 {
521 %cmp1 = fcmp oeq double %c3, %c4
522 %cmp3tmp = fcmp oeq double %c1, %c2
523 %cmp3 = icmp slt i1 %cmp3tmp, %cmp1
524 %cond = select i1 %cmp3, double %a1, double %a2
527 ; CHECK-LABEL: @testdoubleslt
528 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
529 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
530 ; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
531 ; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
538 define double @testdoubleult(double %c1, double %c2, double %c3, double %c4, double %a1, double %a2) #0 {
540 %cmp1 = fcmp oeq double %c3, %c4
541 %cmp3tmp = fcmp oeq double %c1, %c2
542 %cmp3 = icmp ult i1 %cmp3tmp, %cmp1
543 %cond = select i1 %cmp3, double %a1, double %a2
546 ; CHECK-LABEL: @testdoubleult
547 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
548 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
549 ; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
550 ; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
557 define double @testdoublesle(double %c1, double %c2, double %c3, double %c4, double %a1, double %a2) #0 {
559 %cmp1 = fcmp oeq double %c3, %c4
560 %cmp3tmp = fcmp oeq double %c1, %c2
561 %cmp3 = icmp sle i1 %cmp3tmp, %cmp1
562 %cond = select i1 %cmp3, double %a1, double %a2
565 ; CHECK-LABEL: @testdoublesle
566 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
567 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
568 ; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
569 ; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
576 define double @testdoubleule(double %c1, double %c2, double %c3, double %c4, double %a1, double %a2) #0 {
578 %cmp1 = fcmp oeq double %c3, %c4
579 %cmp3tmp = fcmp oeq double %c1, %c2
580 %cmp3 = icmp ule i1 %cmp3tmp, %cmp1
581 %cond = select i1 %cmp3, double %a1, double %a2
584 ; CHECK-LABEL: @testdoubleule
585 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
586 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
587 ; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
588 ; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
595 define double @testdoubleeq(double %c1, double %c2, double %c3, double %c4, double %a1, double %a2) #0 {
597 %cmp1 = fcmp oeq double %c3, %c4
598 %cmp3tmp = fcmp oeq double %c1, %c2
599 %cmp3 = icmp eq i1 %cmp3tmp, %cmp1
600 %cond = select i1 %cmp3, double %a1, double %a2
603 ; CHECK-LABEL: @testdoubleeq
604 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
605 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
606 ; CHECK: creqv [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
607 ; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
614 define double @testdoublesge(double %c1, double %c2, double %c3, double %c4, double %a1, double %a2) #0 {
616 %cmp1 = fcmp oeq double %c3, %c4
617 %cmp3tmp = fcmp oeq double %c1, %c2
618 %cmp3 = icmp sge i1 %cmp3tmp, %cmp1
619 %cond = select i1 %cmp3, double %a1, double %a2
622 ; CHECK-LABEL: @testdoublesge
623 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
624 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
625 ; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
626 ; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
633 define double @testdoubleuge(double %c1, double %c2, double %c3, double %c4, double %a1, double %a2) #0 {
635 %cmp1 = fcmp oeq double %c3, %c4
636 %cmp3tmp = fcmp oeq double %c1, %c2
637 %cmp3 = icmp uge i1 %cmp3tmp, %cmp1
638 %cond = select i1 %cmp3, double %a1, double %a2
641 ; CHECK-LABEL: @testdoubleuge
642 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
643 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
644 ; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
645 ; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
652 define double @testdoublesgt(double %c1, double %c2, double %c3, double %c4, double %a1, double %a2) #0 {
654 %cmp1 = fcmp oeq double %c3, %c4
655 %cmp3tmp = fcmp oeq double %c1, %c2
656 %cmp3 = icmp sgt i1 %cmp3tmp, %cmp1
657 %cond = select i1 %cmp3, double %a1, double %a2
660 ; CHECK-LABEL: @testdoublesgt
661 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
662 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
663 ; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
664 ; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
671 define double @testdoubleugt(double %c1, double %c2, double %c3, double %c4, double %a1, double %a2) #0 {
673 %cmp1 = fcmp oeq double %c3, %c4
674 %cmp3tmp = fcmp oeq double %c1, %c2
675 %cmp3 = icmp ugt i1 %cmp3tmp, %cmp1
676 %cond = select i1 %cmp3, double %a1, double %a2
679 ; CHECK-LABEL: @testdoubleugt
680 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
681 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
682 ; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
683 ; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
690 define double @testdoublene(double %c1, double %c2, double %c3, double %c4, double %a1, double %a2) #0 {
692 %cmp1 = fcmp oeq double %c3, %c4
693 %cmp3tmp = fcmp oeq double %c1, %c2
694 %cmp3 = icmp ne i1 %cmp3tmp, %cmp1
695 %cond = select i1 %cmp3, double %a1, double %a2
698 ; CHECK-LABEL: @testdoublene
699 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
700 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
701 ; CHECK: crxor [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
702 ; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
709 define <4 x float> @testv4floatslt(float %c1, float %c2, float %c3, float %c4, <4 x float> %a1, <4 x float> %a2) #0 {
711 %cmp1 = fcmp oeq float %c3, %c4
712 %cmp3tmp = fcmp oeq float %c1, %c2
713 %cmp3 = icmp slt i1 %cmp3tmp, %cmp1
714 %cond = select i1 %cmp3, <4 x float> %a1, <4 x float> %a2
715 ret <4 x float> %cond
717 ; FIXME: This test (and the other v4f32 tests) should use the same bclr
718 ; technique as the v2f64 tests below.
720 ; CHECK-LABEL: @testv4floatslt
721 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
722 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
723 ; CHECK-DAG: xxlor [[REG2:[0-9]+]], 34, 34
724 ; CHECK-DAG: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
725 ; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
726 ; CHECK: xxlor [[REG2]], 35, 35
728 ; CHECK: xxlor 34, [[REG2]], [[REG2]]
732 define <4 x float> @testv4floatult(float %c1, float %c2, float %c3, float %c4, <4 x float> %a1, <4 x float> %a2) #0 {
734 %cmp1 = fcmp oeq float %c3, %c4
735 %cmp3tmp = fcmp oeq float %c1, %c2
736 %cmp3 = icmp ult i1 %cmp3tmp, %cmp1
737 %cond = select i1 %cmp3, <4 x float> %a1, <4 x float> %a2
738 ret <4 x float> %cond
740 ; CHECK-LABEL: @testv4floatult
741 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
742 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
743 ; CHECK-DAG: xxlor [[REG2:[0-9]+]], 34, 34
744 ; CHECK-DAG: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
745 ; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
746 ; CHECK: xxlor [[REG2]], 35, 35
748 ; CHECK: xxlor 34, [[REG2]], [[REG2]]
752 define <4 x float> @testv4floatsle(float %c1, float %c2, float %c3, float %c4, <4 x float> %a1, <4 x float> %a2) #0 {
754 %cmp1 = fcmp oeq float %c3, %c4
755 %cmp3tmp = fcmp oeq float %c1, %c2
756 %cmp3 = icmp sle i1 %cmp3tmp, %cmp1
757 %cond = select i1 %cmp3, <4 x float> %a1, <4 x float> %a2
758 ret <4 x float> %cond
760 ; CHECK-LABEL: @testv4floatsle
761 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
762 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
763 ; CHECK-DAG: xxlor [[REG2:[0-9]+]], 34, 34
764 ; CHECK-DAG: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
765 ; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
766 ; CHECK: xxlor [[REG2]], 35, 35
768 ; CHECK: xxlor 34, [[REG2]], [[REG2]]
772 define <4 x float> @testv4floatule(float %c1, float %c2, float %c3, float %c4, <4 x float> %a1, <4 x float> %a2) #0 {
774 %cmp1 = fcmp oeq float %c3, %c4
775 %cmp3tmp = fcmp oeq float %c1, %c2
776 %cmp3 = icmp ule i1 %cmp3tmp, %cmp1
777 %cond = select i1 %cmp3, <4 x float> %a1, <4 x float> %a2
778 ret <4 x float> %cond
780 ; CHECK-LABEL: @testv4floatule
781 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
782 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
783 ; CHECK-DAG: xxlor [[REG2:[0-9]+]], 34, 34
784 ; CHECK-DAG: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
785 ; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
786 ; CHECK: xxlor [[REG2]], 35, 35
788 ; CHECK: xxlor 34, [[REG2]], [[REG2]]
792 define <4 x float> @testv4floateq(float %c1, float %c2, float %c3, float %c4, <4 x float> %a1, <4 x float> %a2) #0 {
794 %cmp1 = fcmp oeq float %c3, %c4
795 %cmp3tmp = fcmp oeq float %c1, %c2
796 %cmp3 = icmp eq i1 %cmp3tmp, %cmp1
797 %cond = select i1 %cmp3, <4 x float> %a1, <4 x float> %a2
798 ret <4 x float> %cond
800 ; CHECK-LABEL: @testv4floateq
801 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
802 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
803 ; CHECK-DAG: xxlor [[REG2:[0-9]+]], 34, 34
804 ; CHECK-DAG: creqv [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
805 ; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
806 ; CHECK: xxlor [[REG2]], 35, 35
808 ; CHECK: xxlor 34, [[REG2]], [[REG2]]
812 define <4 x float> @testv4floatsge(float %c1, float %c2, float %c3, float %c4, <4 x float> %a1, <4 x float> %a2) #0 {
814 %cmp1 = fcmp oeq float %c3, %c4
815 %cmp3tmp = fcmp oeq float %c1, %c2
816 %cmp3 = icmp sge i1 %cmp3tmp, %cmp1
817 %cond = select i1 %cmp3, <4 x float> %a1, <4 x float> %a2
818 ret <4 x float> %cond
820 ; CHECK-LABEL: @testv4floatsge
821 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
822 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
823 ; CHECK-DAG: xxlor [[REG2:[0-9]+]], 34, 34
824 ; CHECK-DAG: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
825 ; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
826 ; CHECK: xxlor [[REG2]], 35, 35
828 ; CHECK: xxlor 34, [[REG2]], [[REG2]]
832 define <4 x float> @testv4floatuge(float %c1, float %c2, float %c3, float %c4, <4 x float> %a1, <4 x float> %a2) #0 {
834 %cmp1 = fcmp oeq float %c3, %c4
835 %cmp3tmp = fcmp oeq float %c1, %c2
836 %cmp3 = icmp uge i1 %cmp3tmp, %cmp1
837 %cond = select i1 %cmp3, <4 x float> %a1, <4 x float> %a2
838 ret <4 x float> %cond
840 ; CHECK-LABEL: @testv4floatuge
841 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
842 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
843 ; CHECK-DAG: xxlor [[REG2:[0-9]+]], 34, 34
844 ; CHECK-DAG: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
845 ; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
846 ; CHECK: xxlor [[REG2]], 35, 35
848 ; CHECK: xxlor 34, [[REG2]], [[REG2]]
852 define <4 x float> @testv4floatsgt(float %c1, float %c2, float %c3, float %c4, <4 x float> %a1, <4 x float> %a2) #0 {
854 %cmp1 = fcmp oeq float %c3, %c4
855 %cmp3tmp = fcmp oeq float %c1, %c2
856 %cmp3 = icmp sgt i1 %cmp3tmp, %cmp1
857 %cond = select i1 %cmp3, <4 x float> %a1, <4 x float> %a2
858 ret <4 x float> %cond
860 ; CHECK-LABEL: @testv4floatsgt
861 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
862 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
863 ; CHECK-DAG: xxlor [[REG2:[0-9]+]], 34, 34
864 ; CHECK-DAG: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
865 ; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
866 ; CHECK: xxlor [[REG2]], 35, 35
868 ; CHECK: xxlor 34, [[REG2]], [[REG2]]
872 define <4 x float> @testv4floatugt(float %c1, float %c2, float %c3, float %c4, <4 x float> %a1, <4 x float> %a2) #0 {
874 %cmp1 = fcmp oeq float %c3, %c4
875 %cmp3tmp = fcmp oeq float %c1, %c2
876 %cmp3 = icmp ugt i1 %cmp3tmp, %cmp1
877 %cond = select i1 %cmp3, <4 x float> %a1, <4 x float> %a2
878 ret <4 x float> %cond
880 ; CHECK-LABEL: @testv4floatugt
881 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
882 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
883 ; CHECK-DAG: xxlor [[REG2:[0-9]+]], 34, 34
884 ; CHECK-DAG: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
885 ; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
886 ; CHECK: xxlor [[REG2]], 35, 35
888 ; CHECK: xxlor 34, [[REG2]], [[REG2]]
892 define <4 x float> @testv4floatne(float %c1, float %c2, float %c3, float %c4, <4 x float> %a1, <4 x float> %a2) #0 {
894 %cmp1 = fcmp oeq float %c3, %c4
895 %cmp3tmp = fcmp oeq float %c1, %c2
896 %cmp3 = icmp ne i1 %cmp3tmp, %cmp1
897 %cond = select i1 %cmp3, <4 x float> %a1, <4 x float> %a2
898 ret <4 x float> %cond
900 ; CHECK-LABEL: @testv4floatne
901 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
902 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
903 ; CHECK-DAG: xxlor [[REG2:[0-9]+]], 34, 34
904 ; CHECK-DAG: crxor [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
905 ; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
906 ; CHECK: xxlor [[REG2]], 35, 35
908 ; CHECK: xxlor 34, [[REG2]], [[REG2]]
912 define ppc_fp128 @testppc_fp128eq(ppc_fp128 %c1, ppc_fp128 %c2, ppc_fp128 %c3, ppc_fp128 %c4, ppc_fp128 %a1, ppc_fp128 %a2) #0 {
914 %cmp1 = fcmp oeq ppc_fp128 %c3, %c4
915 %cmp3tmp = fcmp oeq ppc_fp128 %c1, %c2
916 %cmp3 = icmp eq i1 %cmp3tmp, %cmp1
917 %cond = select i1 %cmp3, ppc_fp128 %a1, ppc_fp128 %a2
920 ; FIXME: Because of the way that the late SELECT_* pseudo-instruction expansion
921 ; works, we end up with two blocks with the same predicate. These could be
924 ; CHECK-LABEL: @testppc_fp128eq
925 ; CHECK-DAG: fcmpu {{[0-9]+}}, 6, 8
926 ; CHECK-DAG: fcmpu {{[0-9]+}}, 5, 7
927 ; CHECK-DAG: fcmpu {{[0-9]+}}, 2, 4
928 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 3
929 ; CHECK: crand [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
930 ; CHECK: crand [[REG2:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
931 ; CHECK: creqv [[REG3:[0-9]+]], [[REG2]], [[REG1]]
932 ; CHECK: bc 12, [[REG3]], .LBB[[BB1:[0-9_]+]]
934 ; CHECK: .LBB[[BB1]]:
935 ; CHECK: bc 12, [[REG3]], .LBB[[BB2:[0-9_]+]]
937 ; CHECK: .LBB[[BB2]]:
938 ; CHECK-DAG: fmr 1, 9
939 ; CHECK-DAG: fmr 2, 10
943 define <2 x double> @testv2doubleslt(float %c1, float %c2, float %c3, float %c4, <2 x double> %a1, <2 x double> %a2) #0 {
945 %cmp1 = fcmp oeq float %c3, %c4
946 %cmp3tmp = fcmp oeq float %c1, %c2
947 %cmp3 = icmp slt i1 %cmp3tmp, %cmp1
948 %cond = select i1 %cmp3, <2 x double> %a1, <2 x double> %a2
949 ret <2 x double> %cond
951 ; CHECK-LABEL: @testv2doubleslt
952 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
953 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
954 ; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
955 ; CHECK: bclr 12, [[REG1]], 0
960 define <2 x double> @testv2doubleult(float %c1, float %c2, float %c3, float %c4, <2 x double> %a1, <2 x double> %a2) #0 {
962 %cmp1 = fcmp oeq float %c3, %c4
963 %cmp3tmp = fcmp oeq float %c1, %c2
964 %cmp3 = icmp ult i1 %cmp3tmp, %cmp1
965 %cond = select i1 %cmp3, <2 x double> %a1, <2 x double> %a2
966 ret <2 x double> %cond
968 ; CHECK-LABEL: @testv2doubleult
969 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
970 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
971 ; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
972 ; CHECK: bclr 12, [[REG1]], 0
977 define <2 x double> @testv2doublesle(float %c1, float %c2, float %c3, float %c4, <2 x double> %a1, <2 x double> %a2) #0 {
979 %cmp1 = fcmp oeq float %c3, %c4
980 %cmp3tmp = fcmp oeq float %c1, %c2
981 %cmp3 = icmp sle i1 %cmp3tmp, %cmp1
982 %cond = select i1 %cmp3, <2 x double> %a1, <2 x double> %a2
983 ret <2 x double> %cond
985 ; CHECK-LABEL: @testv2doublesle
986 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
987 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
988 ; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
989 ; CHECK: bclr 12, [[REG1]], 0
994 define <2 x double> @testv2doubleule(float %c1, float %c2, float %c3, float %c4, <2 x double> %a1, <2 x double> %a2) #0 {
996 %cmp1 = fcmp oeq float %c3, %c4
997 %cmp3tmp = fcmp oeq float %c1, %c2
998 %cmp3 = icmp ule i1 %cmp3tmp, %cmp1
999 %cond = select i1 %cmp3, <2 x double> %a1, <2 x double> %a2
1000 ret <2 x double> %cond
1002 ; CHECK-LABEL: @testv2doubleule
1003 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
1004 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
1005 ; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
1006 ; CHECK: bclr 12, [[REG1]], 0
1007 ; CHECK: vor 2, 3, 3
1011 define <2 x double> @testv2doubleeq(float %c1, float %c2, float %c3, float %c4, <2 x double> %a1, <2 x double> %a2) #0 {
1013 %cmp1 = fcmp oeq float %c3, %c4
1014 %cmp3tmp = fcmp oeq float %c1, %c2
1015 %cmp3 = icmp eq i1 %cmp3tmp, %cmp1
1016 %cond = select i1 %cmp3, <2 x double> %a1, <2 x double> %a2
1017 ret <2 x double> %cond
1019 ; CHECK-LABEL: @testv2doubleeq
1020 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
1021 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
1022 ; CHECK: creqv [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
1023 ; CHECK: bclr 12, [[REG1]], 0
1024 ; CHECK: vor 2, 3, 3
1028 define <2 x double> @testv2doublesge(float %c1, float %c2, float %c3, float %c4, <2 x double> %a1, <2 x double> %a2) #0 {
1030 %cmp1 = fcmp oeq float %c3, %c4
1031 %cmp3tmp = fcmp oeq float %c1, %c2
1032 %cmp3 = icmp sge i1 %cmp3tmp, %cmp1
1033 %cond = select i1 %cmp3, <2 x double> %a1, <2 x double> %a2
1034 ret <2 x double> %cond
1036 ; CHECK-LABEL: @testv2doublesge
1037 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
1038 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
1039 ; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
1040 ; CHECK: bclr 12, [[REG1]], 0
1041 ; CHECK: vor 2, 3, 3
1045 define <2 x double> @testv2doubleuge(float %c1, float %c2, float %c3, float %c4, <2 x double> %a1, <2 x double> %a2) #0 {
1047 %cmp1 = fcmp oeq float %c3, %c4
1048 %cmp3tmp = fcmp oeq float %c1, %c2
1049 %cmp3 = icmp uge i1 %cmp3tmp, %cmp1
1050 %cond = select i1 %cmp3, <2 x double> %a1, <2 x double> %a2
1051 ret <2 x double> %cond
1053 ; CHECK-LABEL: @testv2doubleuge
1054 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
1055 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
1056 ; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
1057 ; CHECK: bclr 12, [[REG1]], 0
1058 ; CHECK: vor 2, 3, 3
1062 define <2 x double> @testv2doublesgt(float %c1, float %c2, float %c3, float %c4, <2 x double> %a1, <2 x double> %a2) #0 {
1064 %cmp1 = fcmp oeq float %c3, %c4
1065 %cmp3tmp = fcmp oeq float %c1, %c2
1066 %cmp3 = icmp sgt i1 %cmp3tmp, %cmp1
1067 %cond = select i1 %cmp3, <2 x double> %a1, <2 x double> %a2
1068 ret <2 x double> %cond
1070 ; CHECK-LABEL: @testv2doublesgt
1071 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
1072 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
1073 ; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
1074 ; CHECK: bclr 12, [[REG1]], 0
1075 ; CHECK: vor 2, 3, 3
1079 define <2 x double> @testv2doubleugt(float %c1, float %c2, float %c3, float %c4, <2 x double> %a1, <2 x double> %a2) #0 {
1081 %cmp1 = fcmp oeq float %c3, %c4
1082 %cmp3tmp = fcmp oeq float %c1, %c2
1083 %cmp3 = icmp ugt i1 %cmp3tmp, %cmp1
1084 %cond = select i1 %cmp3, <2 x double> %a1, <2 x double> %a2
1085 ret <2 x double> %cond
1087 ; CHECK-LABEL: @testv2doubleugt
1088 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
1089 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
1090 ; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
1091 ; CHECK: bclr 12, [[REG1]], 0
1092 ; CHECK: vor 2, 3, 3
1096 define <2 x double> @testv2doublene(float %c1, float %c2, float %c3, float %c4, <2 x double> %a1, <2 x double> %a2) #0 {
1098 %cmp1 = fcmp oeq float %c3, %c4
1099 %cmp3tmp = fcmp oeq float %c1, %c2
1100 %cmp3 = icmp ne i1 %cmp3tmp, %cmp1
1101 %cond = select i1 %cmp3, <2 x double> %a1, <2 x double> %a2
1102 ret <2 x double> %cond
1104 ; CHECK-LABEL: @testv2doublene
1105 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
1106 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
1107 ; CHECK: crxor [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
1108 ; CHECK: bclr 12, [[REG1]], 0
1109 ; CHECK: vor 2, 3, 3
1113 define <4 x double> @testqv4doubleslt(float %c1, float %c2, float %c3, float %c4, <4 x double> %a1, <4 x double> %a2) #1 {
1115 %cmp1 = fcmp oeq float %c3, %c4
1116 %cmp3tmp = fcmp oeq float %c1, %c2
1117 %cmp3 = icmp slt i1 %cmp3tmp, %cmp1
1118 %cond = select i1 %cmp3, <4 x double> %a1, <4 x double> %a2
1119 ret <4 x double> %cond
1121 ; CHECK-LABEL: @testqv4doubleslt
1122 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
1123 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
1124 ; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
1125 ; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
1127 ; CHECK: .LBB[[BB]]:
1132 define <4 x double> @testqv4doubleult(float %c1, float %c2, float %c3, float %c4, <4 x double> %a1, <4 x double> %a2) #1 {
1134 %cmp1 = fcmp oeq float %c3, %c4
1135 %cmp3tmp = fcmp oeq float %c1, %c2
1136 %cmp3 = icmp ult i1 %cmp3tmp, %cmp1
1137 %cond = select i1 %cmp3, <4 x double> %a1, <4 x double> %a2
1138 ret <4 x double> %cond
1140 ; CHECK-LABEL: @testqv4doubleult
1141 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
1142 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
1143 ; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
1144 ; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
1146 ; CHECK: .LBB[[BB]]:
1151 define <4 x double> @testqv4doublesle(float %c1, float %c2, float %c3, float %c4, <4 x double> %a1, <4 x double> %a2) #1 {
1153 %cmp1 = fcmp oeq float %c3, %c4
1154 %cmp3tmp = fcmp oeq float %c1, %c2
1155 %cmp3 = icmp sle i1 %cmp3tmp, %cmp1
1156 %cond = select i1 %cmp3, <4 x double> %a1, <4 x double> %a2
1157 ret <4 x double> %cond
1159 ; CHECK-LABEL: @testqv4doublesle
1160 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
1161 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
1162 ; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
1163 ; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
1165 ; CHECK: .LBB[[BB]]:
1170 define <4 x double> @testqv4doubleule(float %c1, float %c2, float %c3, float %c4, <4 x double> %a1, <4 x double> %a2) #1 {
1172 %cmp1 = fcmp oeq float %c3, %c4
1173 %cmp3tmp = fcmp oeq float %c1, %c2
1174 %cmp3 = icmp ule i1 %cmp3tmp, %cmp1
1175 %cond = select i1 %cmp3, <4 x double> %a1, <4 x double> %a2
1176 ret <4 x double> %cond
1178 ; CHECK-LABEL: @testqv4doubleule
1179 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
1180 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
1181 ; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
1182 ; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
1184 ; CHECK: .LBB[[BB]]:
1189 define <4 x double> @testqv4doubleeq(float %c1, float %c2, float %c3, float %c4, <4 x double> %a1, <4 x double> %a2) #1 {
1191 %cmp1 = fcmp oeq float %c3, %c4
1192 %cmp3tmp = fcmp oeq float %c1, %c2
1193 %cmp3 = icmp eq i1 %cmp3tmp, %cmp1
1194 %cond = select i1 %cmp3, <4 x double> %a1, <4 x double> %a2
1195 ret <4 x double> %cond
1197 ; CHECK-LABEL: @testqv4doubleeq
1198 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
1199 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
1200 ; CHECK: creqv [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
1201 ; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
1203 ; CHECK: .LBB[[BB]]:
1208 define <4 x double> @testqv4doublesge(float %c1, float %c2, float %c3, float %c4, <4 x double> %a1, <4 x double> %a2) #1 {
1210 %cmp1 = fcmp oeq float %c3, %c4
1211 %cmp3tmp = fcmp oeq float %c1, %c2
1212 %cmp3 = icmp sge i1 %cmp3tmp, %cmp1
1213 %cond = select i1 %cmp3, <4 x double> %a1, <4 x double> %a2
1214 ret <4 x double> %cond
1216 ; CHECK-LABEL: @testqv4doublesge
1217 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
1218 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
1219 ; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
1220 ; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
1222 ; CHECK: .LBB[[BB]]:
1227 define <4 x double> @testqv4doubleuge(float %c1, float %c2, float %c3, float %c4, <4 x double> %a1, <4 x double> %a2) #1 {
1229 %cmp1 = fcmp oeq float %c3, %c4
1230 %cmp3tmp = fcmp oeq float %c1, %c2
1231 %cmp3 = icmp uge i1 %cmp3tmp, %cmp1
1232 %cond = select i1 %cmp3, <4 x double> %a1, <4 x double> %a2
1233 ret <4 x double> %cond
1235 ; CHECK-LABEL: @testqv4doubleuge
1236 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
1237 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
1238 ; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
1239 ; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
1241 ; CHECK: .LBB[[BB]]:
1246 define <4 x double> @testqv4doublesgt(float %c1, float %c2, float %c3, float %c4, <4 x double> %a1, <4 x double> %a2) #1 {
1248 %cmp1 = fcmp oeq float %c3, %c4
1249 %cmp3tmp = fcmp oeq float %c1, %c2
1250 %cmp3 = icmp sgt i1 %cmp3tmp, %cmp1
1251 %cond = select i1 %cmp3, <4 x double> %a1, <4 x double> %a2
1252 ret <4 x double> %cond
1254 ; CHECK-LABEL: @testqv4doublesgt
1255 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
1256 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
1257 ; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
1258 ; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
1260 ; CHECK: .LBB[[BB]]:
1265 define <4 x double> @testqv4doubleugt(float %c1, float %c2, float %c3, float %c4, <4 x double> %a1, <4 x double> %a2) #1 {
1267 %cmp1 = fcmp oeq float %c3, %c4
1268 %cmp3tmp = fcmp oeq float %c1, %c2
1269 %cmp3 = icmp ugt i1 %cmp3tmp, %cmp1
1270 %cond = select i1 %cmp3, <4 x double> %a1, <4 x double> %a2
1271 ret <4 x double> %cond
1273 ; CHECK-LABEL: @testqv4doubleugt
1274 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
1275 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
1276 ; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
1277 ; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
1279 ; CHECK: .LBB[[BB]]:
1284 define <4 x double> @testqv4doublene(float %c1, float %c2, float %c3, float %c4, <4 x double> %a1, <4 x double> %a2) #1 {
1286 %cmp1 = fcmp oeq float %c3, %c4
1287 %cmp3tmp = fcmp oeq float %c1, %c2
1288 %cmp3 = icmp ne i1 %cmp3tmp, %cmp1
1289 %cond = select i1 %cmp3, <4 x double> %a1, <4 x double> %a2
1290 ret <4 x double> %cond
1292 ; CHECK-LABEL: @testqv4doublene
1293 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
1294 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
1295 ; CHECK: crxor [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
1296 ; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
1298 ; CHECK: .LBB[[BB]]:
1303 define <4 x float> @testqv4floatslt(float %c1, float %c2, float %c3, float %c4, <4 x float> %a1, <4 x float> %a2) #1 {
1305 %cmp1 = fcmp oeq float %c3, %c4
1306 %cmp3tmp = fcmp oeq float %c1, %c2
1307 %cmp3 = icmp slt i1 %cmp3tmp, %cmp1
1308 %cond = select i1 %cmp3, <4 x float> %a1, <4 x float> %a2
1309 ret <4 x float> %cond
1311 ; CHECK-LABEL: @testqv4floatslt
1312 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
1313 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
1314 ; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
1315 ; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
1317 ; CHECK: .LBB[[BB]]:
1322 define <4 x float> @testqv4floatult(float %c1, float %c2, float %c3, float %c4, <4 x float> %a1, <4 x float> %a2) #1 {
1324 %cmp1 = fcmp oeq float %c3, %c4
1325 %cmp3tmp = fcmp oeq float %c1, %c2
1326 %cmp3 = icmp ult i1 %cmp3tmp, %cmp1
1327 %cond = select i1 %cmp3, <4 x float> %a1, <4 x float> %a2
1328 ret <4 x float> %cond
1330 ; CHECK-LABEL: @testqv4floatult
1331 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
1332 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
1333 ; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
1334 ; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
1336 ; CHECK: .LBB[[BB]]:
1341 define <4 x float> @testqv4floatsle(float %c1, float %c2, float %c3, float %c4, <4 x float> %a1, <4 x float> %a2) #1 {
1343 %cmp1 = fcmp oeq float %c3, %c4
1344 %cmp3tmp = fcmp oeq float %c1, %c2
1345 %cmp3 = icmp sle i1 %cmp3tmp, %cmp1
1346 %cond = select i1 %cmp3, <4 x float> %a1, <4 x float> %a2
1347 ret <4 x float> %cond
1349 ; CHECK-LABEL: @testqv4floatsle
1350 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
1351 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
1352 ; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
1353 ; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
1355 ; CHECK: .LBB[[BB]]:
1360 define <4 x float> @testqv4floatule(float %c1, float %c2, float %c3, float %c4, <4 x float> %a1, <4 x float> %a2) #1 {
1362 %cmp1 = fcmp oeq float %c3, %c4
1363 %cmp3tmp = fcmp oeq float %c1, %c2
1364 %cmp3 = icmp ule i1 %cmp3tmp, %cmp1
1365 %cond = select i1 %cmp3, <4 x float> %a1, <4 x float> %a2
1366 ret <4 x float> %cond
1368 ; CHECK-LABEL: @testqv4floatule
1369 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
1370 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
1371 ; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
1372 ; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
1374 ; CHECK: .LBB[[BB]]:
1379 define <4 x float> @testqv4floateq(float %c1, float %c2, float %c3, float %c4, <4 x float> %a1, <4 x float> %a2) #1 {
1381 %cmp1 = fcmp oeq float %c3, %c4
1382 %cmp3tmp = fcmp oeq float %c1, %c2
1383 %cmp3 = icmp eq i1 %cmp3tmp, %cmp1
1384 %cond = select i1 %cmp3, <4 x float> %a1, <4 x float> %a2
1385 ret <4 x float> %cond
1387 ; CHECK-LABEL: @testqv4floateq
1388 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
1389 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
1390 ; CHECK: creqv [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
1391 ; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
1393 ; CHECK: .LBB[[BB]]:
1398 define <4 x float> @testqv4floatsge(float %c1, float %c2, float %c3, float %c4, <4 x float> %a1, <4 x float> %a2) #1 {
1400 %cmp1 = fcmp oeq float %c3, %c4
1401 %cmp3tmp = fcmp oeq float %c1, %c2
1402 %cmp3 = icmp sge i1 %cmp3tmp, %cmp1
1403 %cond = select i1 %cmp3, <4 x float> %a1, <4 x float> %a2
1404 ret <4 x float> %cond
1406 ; CHECK-LABEL: @testqv4floatsge
1407 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
1408 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
1409 ; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
1410 ; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
1412 ; CHECK: .LBB[[BB]]:
1417 define <4 x float> @testqv4floatuge(float %c1, float %c2, float %c3, float %c4, <4 x float> %a1, <4 x float> %a2) #1 {
1419 %cmp1 = fcmp oeq float %c3, %c4
1420 %cmp3tmp = fcmp oeq float %c1, %c2
1421 %cmp3 = icmp uge i1 %cmp3tmp, %cmp1
1422 %cond = select i1 %cmp3, <4 x float> %a1, <4 x float> %a2
1423 ret <4 x float> %cond
1425 ; CHECK-LABEL: @testqv4floatuge
1426 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
1427 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
1428 ; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
1429 ; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
1431 ; CHECK: .LBB[[BB]]:
1436 define <4 x float> @testqv4floatsgt(float %c1, float %c2, float %c3, float %c4, <4 x float> %a1, <4 x float> %a2) #1 {
1438 %cmp1 = fcmp oeq float %c3, %c4
1439 %cmp3tmp = fcmp oeq float %c1, %c2
1440 %cmp3 = icmp sgt i1 %cmp3tmp, %cmp1
1441 %cond = select i1 %cmp3, <4 x float> %a1, <4 x float> %a2
1442 ret <4 x float> %cond
1444 ; CHECK-LABEL: @testqv4floatsgt
1445 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
1446 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
1447 ; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
1448 ; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
1450 ; CHECK: .LBB[[BB]]:
1455 define <4 x float> @testqv4floatugt(float %c1, float %c2, float %c3, float %c4, <4 x float> %a1, <4 x float> %a2) #1 {
1457 %cmp1 = fcmp oeq float %c3, %c4
1458 %cmp3tmp = fcmp oeq float %c1, %c2
1459 %cmp3 = icmp ugt i1 %cmp3tmp, %cmp1
1460 %cond = select i1 %cmp3, <4 x float> %a1, <4 x float> %a2
1461 ret <4 x float> %cond
1463 ; CHECK-LABEL: @testqv4floatugt
1464 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
1465 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
1466 ; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
1467 ; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
1469 ; CHECK: .LBB[[BB]]:
1474 define <4 x float> @testqv4floatne(float %c1, float %c2, float %c3, float %c4, <4 x float> %a1, <4 x float> %a2) #1 {
1476 %cmp1 = fcmp oeq float %c3, %c4
1477 %cmp3tmp = fcmp oeq float %c1, %c2
1478 %cmp3 = icmp ne i1 %cmp3tmp, %cmp1
1479 %cond = select i1 %cmp3, <4 x float> %a1, <4 x float> %a2
1480 ret <4 x float> %cond
1482 ; CHECK-LABEL: @testqv4floatne
1483 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
1484 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
1485 ; CHECK: crxor [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
1486 ; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
1488 ; CHECK: .LBB[[BB]]:
1493 define <4 x i1> @testqv4i1slt(float %c1, float %c2, float %c3, float %c4, <4 x i1> %a1, <4 x i1> %a2) #1 {
1495 %cmp1 = fcmp oeq float %c3, %c4
1496 %cmp3tmp = fcmp oeq float %c1, %c2
1497 %cmp3 = icmp slt i1 %cmp3tmp, %cmp1
1498 %cond = select i1 %cmp3, <4 x i1> %a1, <4 x i1> %a2
1501 ; CHECK-LABEL: @testqv4i1slt
1502 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
1503 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
1504 ; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
1505 ; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
1507 ; CHECK: .LBB[[BB]]:
1512 define <4 x i1> @testqv4i1ult(float %c1, float %c2, float %c3, float %c4, <4 x i1> %a1, <4 x i1> %a2) #1 {
1514 %cmp1 = fcmp oeq float %c3, %c4
1515 %cmp3tmp = fcmp oeq float %c1, %c2
1516 %cmp3 = icmp ult i1 %cmp3tmp, %cmp1
1517 %cond = select i1 %cmp3, <4 x i1> %a1, <4 x i1> %a2
1520 ; CHECK-LABEL: @testqv4i1ult
1521 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
1522 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
1523 ; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
1524 ; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
1526 ; CHECK: .LBB[[BB]]:
1531 define <4 x i1> @testqv4i1sle(float %c1, float %c2, float %c3, float %c4, <4 x i1> %a1, <4 x i1> %a2) #1 {
1533 %cmp1 = fcmp oeq float %c3, %c4
1534 %cmp3tmp = fcmp oeq float %c1, %c2
1535 %cmp3 = icmp sle i1 %cmp3tmp, %cmp1
1536 %cond = select i1 %cmp3, <4 x i1> %a1, <4 x i1> %a2
1539 ; CHECK-LABEL: @testqv4i1sle
1540 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
1541 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
1542 ; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
1543 ; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
1545 ; CHECK: .LBB[[BB]]:
1550 define <4 x i1> @testqv4i1ule(float %c1, float %c2, float %c3, float %c4, <4 x i1> %a1, <4 x i1> %a2) #1 {
1552 %cmp1 = fcmp oeq float %c3, %c4
1553 %cmp3tmp = fcmp oeq float %c1, %c2
1554 %cmp3 = icmp ule i1 %cmp3tmp, %cmp1
1555 %cond = select i1 %cmp3, <4 x i1> %a1, <4 x i1> %a2
1558 ; CHECK-LABEL: @testqv4i1ule
1559 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
1560 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
1561 ; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
1562 ; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
1564 ; CHECK: .LBB[[BB]]:
1569 define <4 x i1> @testqv4i1eq(float %c1, float %c2, float %c3, float %c4, <4 x i1> %a1, <4 x i1> %a2) #1 {
1571 %cmp1 = fcmp oeq float %c3, %c4
1572 %cmp3tmp = fcmp oeq float %c1, %c2
1573 %cmp3 = icmp eq i1 %cmp3tmp, %cmp1
1574 %cond = select i1 %cmp3, <4 x i1> %a1, <4 x i1> %a2
1577 ; CHECK-LABEL: @testqv4i1eq
1578 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
1579 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
1580 ; CHECK: creqv [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
1581 ; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
1583 ; CHECK: .LBB[[BB]]:
1588 define <4 x i1> @testqv4i1sge(float %c1, float %c2, float %c3, float %c4, <4 x i1> %a1, <4 x i1> %a2) #1 {
1590 %cmp1 = fcmp oeq float %c3, %c4
1591 %cmp3tmp = fcmp oeq float %c1, %c2
1592 %cmp3 = icmp sge i1 %cmp3tmp, %cmp1
1593 %cond = select i1 %cmp3, <4 x i1> %a1, <4 x i1> %a2
1596 ; CHECK-LABEL: @testqv4i1sge
1597 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
1598 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
1599 ; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
1600 ; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
1602 ; CHECK: .LBB[[BB]]:
1607 define <4 x i1> @testqv4i1uge(float %c1, float %c2, float %c3, float %c4, <4 x i1> %a1, <4 x i1> %a2) #1 {
1609 %cmp1 = fcmp oeq float %c3, %c4
1610 %cmp3tmp = fcmp oeq float %c1, %c2
1611 %cmp3 = icmp uge i1 %cmp3tmp, %cmp1
1612 %cond = select i1 %cmp3, <4 x i1> %a1, <4 x i1> %a2
1615 ; CHECK-LABEL: @testqv4i1uge
1616 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
1617 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
1618 ; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
1619 ; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
1621 ; CHECK: .LBB[[BB]]:
1626 define <4 x i1> @testqv4i1sgt(float %c1, float %c2, float %c3, float %c4, <4 x i1> %a1, <4 x i1> %a2) #1 {
1628 %cmp1 = fcmp oeq float %c3, %c4
1629 %cmp3tmp = fcmp oeq float %c1, %c2
1630 %cmp3 = icmp sgt i1 %cmp3tmp, %cmp1
1631 %cond = select i1 %cmp3, <4 x i1> %a1, <4 x i1> %a2
1634 ; CHECK-LABEL: @testqv4i1sgt
1635 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
1636 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
1637 ; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
1638 ; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
1640 ; CHECK: .LBB[[BB]]:
1645 define <4 x i1> @testqv4i1ugt(float %c1, float %c2, float %c3, float %c4, <4 x i1> %a1, <4 x i1> %a2) #1 {
1647 %cmp1 = fcmp oeq float %c3, %c4
1648 %cmp3tmp = fcmp oeq float %c1, %c2
1649 %cmp3 = icmp ugt i1 %cmp3tmp, %cmp1
1650 %cond = select i1 %cmp3, <4 x i1> %a1, <4 x i1> %a2
1653 ; CHECK-LABEL: @testqv4i1ugt
1654 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
1655 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
1656 ; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
1657 ; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
1659 ; CHECK: .LBB[[BB]]:
1664 define <4 x i1> @testqv4i1ne(float %c1, float %c2, float %c3, float %c4, <4 x i1> %a1, <4 x i1> %a2) #1 {
1666 %cmp1 = fcmp oeq float %c3, %c4
1667 %cmp3tmp = fcmp oeq float %c1, %c2
1668 %cmp3 = icmp ne i1 %cmp3tmp, %cmp1
1669 %cond = select i1 %cmp3, <4 x i1> %a1, <4 x i1> %a2
1672 ; CHECK-LABEL: @testqv4i1ne
1673 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
1674 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
1675 ; CHECK: crxor [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
1676 ; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
1678 ; CHECK: .LBB[[BB]]:
1683 attributes #0 = { nounwind readnone "target-cpu"="pwr7" }
1684 attributes #1 = { nounwind readnone "target-cpu"="a2q" }