1 ; RUN: llc < %s -mtriple=powerpc-unknown-linux-gnu -march=ppc32 -mattr=+altivec | FileCheck %s
3 define <4 x i32> @test_v4i32(<4 x i32>* %X, <4 x i32>* %Y) {
4 %tmp = load <4 x i32>* %X ; <<4 x i32>> [#uses=1]
5 %tmp2 = load <4 x i32>* %Y ; <<4 x i32>> [#uses=1]
6 %tmp3 = mul <4 x i32> %tmp, %tmp2 ; <<4 x i32>> [#uses=1]
13 define <8 x i16> @test_v8i16(<8 x i16>* %X, <8 x i16>* %Y) {
14 %tmp = load <8 x i16>* %X ; <<8 x i16>> [#uses=1]
15 %tmp2 = load <8 x i16>* %Y ; <<8 x i16>> [#uses=1]
16 %tmp3 = mul <8 x i16> %tmp, %tmp2 ; <<8 x i16>> [#uses=1]
23 define <16 x i8> @test_v16i8(<16 x i8>* %X, <16 x i8>* %Y) {
24 %tmp = load <16 x i8>* %X ; <<16 x i8>> [#uses=1]
25 %tmp2 = load <16 x i8>* %Y ; <<16 x i8>> [#uses=1]
26 %tmp3 = mul <16 x i8> %tmp, %tmp2 ; <<16 x i8>> [#uses=1]
34 define <4 x float> @test_float(<4 x float>* %X, <4 x float>* %Y) {
35 %tmp = load <4 x float>* %X
36 %tmp2 = load <4 x float>* %Y
37 %tmp3 = fmul <4 x float> %tmp, %tmp2
40 ; Check the creation of a negative zero float vector by creating a vector of
41 ; all bits set and shifting it 31 bits to left, resulting a an vector of
42 ; 4 x 0x80000000 (-0.0 as float).
44 ; CHECK: vspltisw [[ZNEG:[0-9]+]], -1
45 ; CHECK: vslw {{[0-9]+}}, [[ZNEG]], [[ZNEG]]