1 ; Check the miscellaneous logical vector operations added in P8
3 ; RUN: llc -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 < %s | FileCheck %s
4 ; RUN: llc -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 -mattr=-vsx < %s | FileCheck %s
6 define <4 x i32> @test_veqv(<4 x i32> %x, <4 x i32> %y) nounwind {
7 %tmp = xor <4 x i32> %x, %y
8 %ret_val = xor <4 x i32> %tmp, < i32 -1, i32 -1, i32 -1, i32 -1>
14 define <4 x i32> @test_vnand(<4 x i32> %x, <4 x i32> %y) nounwind {
15 %tmp = and <4 x i32> %x, %y
16 %ret_val = xor <4 x i32> %tmp, <i32 -1, i32 -1, i32 -1, i32 -1>
17 ret <4 x i32> %ret_val
18 ; CHECK: vnand 2, 2, 3
22 define <4 x i32> @test_vorc(<4 x i32> %x, <4 x i32> %y) nounwind {
23 %tmp = xor <4 x i32> %y, <i32 -1, i32 -1, i32 -1, i32 -1>
24 %ret_val = or <4 x i32> %x, %tmp
25 ret <4 x i32> %ret_val