1 ; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck --check-prefix=EG-CHECK --check-prefix=FUNC %s
2 ; RUN: llc < %s -march=r600 -mcpu=verde -verify-machineinstrs | FileCheck --check-prefix=SI-CHECK --check-prefix=FUNC %s
5 ;EG-CHECK: ADD_INT {{[* ]*}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
7 ;SI-CHECK: V_ADD_I32_e32 [[REG:v[0-9]+]], {{v[0-9]+, v[0-9]+}}
9 ;SI-CHECK: BUFFER_STORE_DWORD [[REG]],
10 define void @test1(i32 addrspace(1)* %out, i32 addrspace(1)* %in) {
11 %b_ptr = getelementptr i32 addrspace(1)* %in, i32 1
12 %a = load i32 addrspace(1)* %in
13 %b = load i32 addrspace(1)* %b_ptr
14 %result = add i32 %a, %b
15 store i32 %result, i32 addrspace(1)* %out
20 ;EG-CHECK: ADD_INT {{[* ]*}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
21 ;EG-CHECK: ADD_INT {{[* ]*}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
23 ;SI-CHECK: V_ADD_I32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
24 ;SI-CHECK: V_ADD_I32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
26 define void @test2(<2 x i32> addrspace(1)* %out, <2 x i32> addrspace(1)* %in) {
27 %b_ptr = getelementptr <2 x i32> addrspace(1)* %in, i32 1
28 %a = load <2 x i32> addrspace(1)* %in
29 %b = load <2 x i32> addrspace(1)* %b_ptr
30 %result = add <2 x i32> %a, %b
31 store <2 x i32> %result, <2 x i32> addrspace(1)* %out
36 ;EG-CHECK: ADD_INT {{[* ]*}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
37 ;EG-CHECK: ADD_INT {{[* ]*}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
38 ;EG-CHECK: ADD_INT {{[* ]*}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
39 ;EG-CHECK: ADD_INT {{[* ]*}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
41 ;SI-CHECK: V_ADD_I32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
42 ;SI-CHECK: V_ADD_I32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
43 ;SI-CHECK: V_ADD_I32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
44 ;SI-CHECK: V_ADD_I32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
46 define void @test4(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) {
47 %b_ptr = getelementptr <4 x i32> addrspace(1)* %in, i32 1
48 %a = load <4 x i32> addrspace(1)* %in
49 %b = load <4 x i32> addrspace(1)* %b_ptr
50 %result = add <4 x i32> %a, %b
51 store <4 x i32> %result, <4 x i32> addrspace(1)* %out
72 define void @test8(<8 x i32> addrspace(1)* %out, <8 x i32> %a, <8 x i32> %b) {
74 %0 = add <8 x i32> %a, %b
75 store <8 x i32> %0, <8 x i32> addrspace(1)* %out
100 ; SI-CHECK: S_ADD_I32
101 ; SI-CHECK: S_ADD_I32
102 ; SI-CHECK: S_ADD_I32
103 ; SI-CHECK: S_ADD_I32
104 ; SI-CHECK: S_ADD_I32
105 ; SI-CHECK: S_ADD_I32
106 ; SI-CHECK: S_ADD_I32
107 ; SI-CHECK: S_ADD_I32
108 ; SI-CHECK: S_ADD_I32
109 ; SI-CHECK: S_ADD_I32
110 ; SI-CHECK: S_ADD_I32
111 ; SI-CHECK: S_ADD_I32
112 define void @test16(<16 x i32> addrspace(1)* %out, <16 x i32> %a, <16 x i32> %b) {
114 %0 = add <16 x i32> %a, %b
115 store <16 x i32> %0, <16 x i32> addrspace(1)* %out
120 ; SI-CHECK: S_ADD_I32
121 ; SI-CHECK: S_ADDC_U32
122 define void @add64(i64 addrspace(1)* %out, i64 %a, i64 %b) {
125 store i64 %0, i64 addrspace(1)* %out
129 ; The V_ADDC_U32 and V_ADD_I32 instruction can't read SGPRs, because they
130 ; use VCC. The test is designed so that %a will be stored in an SGPR and
131 ; %0 will be stored in a VGPR, so the comiler will be forced to copy %a
132 ; to a VGPR before doing the add.
134 ; FUNC-LABEL: @add64_sgpr_vgpr
135 ; SI-CHECK-NOT: V_ADDC_U32_e32 s
136 define void @add64_sgpr_vgpr(i64 addrspace(1)* %out, i64 %a, i64 addrspace(1)* %in) {
138 %0 = load i64 addrspace(1)* %in
140 store i64 %1, i64 addrspace(1)* %out