1 ; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
2 ; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
3 ; RUN: llc -march=r600 -mcpu=cypress -verify-machineinstrs < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s
5 declare i32 @llvm.ctlz.i32(i32, i1) nounwind readnone
6 declare <2 x i32> @llvm.ctlz.v2i32(<2 x i32>, i1) nounwind readnone
7 declare <4 x i32> @llvm.ctlz.v4i32(<4 x i32>, i1) nounwind readnone
9 ; FUNC-LABEL: {{^}}s_ctlz_zero_undef_i32:
10 ; SI: s_load_dword [[VAL:s[0-9]+]],
11 ; SI: s_flbit_i32_b32 [[SRESULT:s[0-9]+]], [[VAL]]
12 ; SI: v_mov_b32_e32 [[VRESULT:v[0-9]+]], [[SRESULT]]
13 ; SI: buffer_store_dword [[VRESULT]],
15 ; EG: MEM_RAT_CACHELESS STORE_RAW [[RESULT:T[0-9]+\.[XYZW]]]
16 ; EG: FFBH_UINT {{\*? *}}[[RESULT]]
17 define void @s_ctlz_zero_undef_i32(i32 addrspace(1)* noalias %out, i32 %val) nounwind {
18 %ctlz = call i32 @llvm.ctlz.i32(i32 %val, i1 true) nounwind readnone
19 store i32 %ctlz, i32 addrspace(1)* %out, align 4
23 ; FUNC-LABEL: {{^}}v_ctlz_zero_undef_i32:
24 ; SI: buffer_load_dword [[VAL:v[0-9]+]],
25 ; SI: v_ffbh_u32_e32 [[RESULT:v[0-9]+]], [[VAL]]
26 ; SI: buffer_store_dword [[RESULT]],
28 ; EG: MEM_RAT_CACHELESS STORE_RAW [[RESULT:T[0-9]+\.[XYZW]]]
29 ; EG: FFBH_UINT {{\*? *}}[[RESULT]]
30 define void @v_ctlz_zero_undef_i32(i32 addrspace(1)* noalias %out, i32 addrspace(1)* noalias %valptr) nounwind {
31 %val = load i32 addrspace(1)* %valptr, align 4
32 %ctlz = call i32 @llvm.ctlz.i32(i32 %val, i1 true) nounwind readnone
33 store i32 %ctlz, i32 addrspace(1)* %out, align 4
37 ; FUNC-LABEL: {{^}}v_ctlz_zero_undef_v2i32:
38 ; SI: buffer_load_dwordx2
41 ; SI: buffer_store_dwordx2
43 ; EG: MEM_RAT_CACHELESS STORE_RAW [[RESULT:T[0-9]+]]{{\.[XYZW]}}
44 ; EG: FFBH_UINT {{\*? *}}[[RESULT]]
45 ; EG: FFBH_UINT {{\*? *}}[[RESULT]]
46 define void @v_ctlz_zero_undef_v2i32(<2 x i32> addrspace(1)* noalias %out, <2 x i32> addrspace(1)* noalias %valptr) nounwind {
47 %val = load <2 x i32> addrspace(1)* %valptr, align 8
48 %ctlz = call <2 x i32> @llvm.ctlz.v2i32(<2 x i32> %val, i1 true) nounwind readnone
49 store <2 x i32> %ctlz, <2 x i32> addrspace(1)* %out, align 8
53 ; FUNC-LABEL: {{^}}v_ctlz_zero_undef_v4i32:
54 ; SI: buffer_load_dwordx4
59 ; SI: buffer_store_dwordx4
61 ; EG: MEM_RAT_CACHELESS STORE_RAW [[RESULT:T[0-9]+]]{{\.[XYZW]}}
62 ; EG: FFBH_UINT {{\*? *}}[[RESULT]]
63 ; EG: FFBH_UINT {{\*? *}}[[RESULT]]
64 ; EG: FFBH_UINT {{\*? *}}[[RESULT]]
65 ; EG: FFBH_UINT {{\*? *}}[[RESULT]]
66 define void @v_ctlz_zero_undef_v4i32(<4 x i32> addrspace(1)* noalias %out, <4 x i32> addrspace(1)* noalias %valptr) nounwind {
67 %val = load <4 x i32> addrspace(1)* %valptr, align 16
68 %ctlz = call <4 x i32> @llvm.ctlz.v4i32(<4 x i32> %val, i1 true) nounwind readnone
69 store <4 x i32> %ctlz, <4 x i32> addrspace(1)* %out, align 16