1 ; RUN: llc -march=r600 -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
2 ; RUN: llc -march=r600 -mcpu=cypress -verify-machineinstrs < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s
4 declare i32 @llvm.cttz.i32(i32, i1) nounwind readnone
5 declare <2 x i32> @llvm.cttz.v2i32(<2 x i32>, i1) nounwind readnone
6 declare <4 x i32> @llvm.cttz.v4i32(<4 x i32>, i1) nounwind readnone
8 ; FUNC-LABEL: @s_cttz_zero_undef_i32:
9 ; SI: S_LOAD_DWORD [[VAL:s[0-9]+]],
10 ; SI: S_FF1_I32_B32 [[SRESULT:s[0-9]+]], [[VAL]]
11 ; SI: V_MOV_B32_e32 [[VRESULT:v[0-9]+]], [[SRESULT]]
12 ; SI: BUFFER_STORE_DWORD [[VRESULT]],
14 ; EG: MEM_RAT_CACHELESS STORE_RAW [[RESULT:T[0-9]+\.[XYZW]]]
15 ; EG: FFBL_INT {{\*? *}}[[RESULT]]
16 define void @s_cttz_zero_undef_i32(i32 addrspace(1)* noalias %out, i32 %val) nounwind {
17 %cttz = call i32 @llvm.cttz.i32(i32 %val, i1 true) nounwind readnone
18 store i32 %cttz, i32 addrspace(1)* %out, align 4
22 ; FUNC-LABEL: @v_cttz_zero_undef_i32:
23 ; SI: BUFFER_LOAD_DWORD [[VAL:v[0-9]+]],
24 ; SI: V_FFBL_B32_e32 [[RESULT:v[0-9]+]], [[VAL]]
25 ; SI: BUFFER_STORE_DWORD [[RESULT]],
27 ; EG: MEM_RAT_CACHELESS STORE_RAW [[RESULT:T[0-9]+\.[XYZW]]]
28 ; EG: FFBL_INT {{\*? *}}[[RESULT]]
29 define void @v_cttz_zero_undef_i32(i32 addrspace(1)* noalias %out, i32 addrspace(1)* noalias %valptr) nounwind {
30 %val = load i32 addrspace(1)* %valptr, align 4
31 %cttz = call i32 @llvm.cttz.i32(i32 %val, i1 true) nounwind readnone
32 store i32 %cttz, i32 addrspace(1)* %out, align 4
36 ; FUNC-LABEL: @v_cttz_zero_undef_v2i32:
37 ; SI: BUFFER_LOAD_DWORDX2
40 ; SI: BUFFER_STORE_DWORDX2
42 ; EG: MEM_RAT_CACHELESS STORE_RAW [[RESULT:T[0-9]+]]{{\.[XYZW]}}
43 ; EG: FFBL_INT {{\*? *}}[[RESULT]]
44 ; EG: FFBL_INT {{\*? *}}[[RESULT]]
45 define void @v_cttz_zero_undef_v2i32(<2 x i32> addrspace(1)* noalias %out, <2 x i32> addrspace(1)* noalias %valptr) nounwind {
46 %val = load <2 x i32> addrspace(1)* %valptr, align 8
47 %cttz = call <2 x i32> @llvm.cttz.v2i32(<2 x i32> %val, i1 true) nounwind readnone
48 store <2 x i32> %cttz, <2 x i32> addrspace(1)* %out, align 8
52 ; FUNC-LABEL: @v_cttz_zero_undef_v4i32:
53 ; SI: BUFFER_LOAD_DWORDX4
58 ; SI: BUFFER_STORE_DWORDX4
60 ; EG: MEM_RAT_CACHELESS STORE_RAW [[RESULT:T[0-9]+]]{{\.[XYZW]}}
61 ; EG: FFBL_INT {{\*? *}}[[RESULT]]
62 ; EG: FFBL_INT {{\*? *}}[[RESULT]]
63 ; EG: FFBL_INT {{\*? *}}[[RESULT]]
64 ; EG: FFBL_INT {{\*? *}}[[RESULT]]
65 define void @v_cttz_zero_undef_v4i32(<4 x i32> addrspace(1)* noalias %out, <4 x i32> addrspace(1)* noalias %valptr) nounwind {
66 %val = load <4 x i32> addrspace(1)* %valptr, align 16
67 %cttz = call <4 x i32> @llvm.cttz.v4i32(<4 x i32> %val, i1 true) nounwind readnone
68 store <4 x i32> %cttz, <4 x i32> addrspace(1)* %out, align 16