1 ; RUN: llc -march=r600 -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s
3 ; SI-LABEL: @load_i8_to_f32:
4 ; SI: BUFFER_LOAD_UBYTE [[LOADREG:v[0-9]+]],
7 ; SI: V_CVT_F32_UBYTE0_e32 [[CONV:v[0-9]+]], [[LOADREG]]
8 ; SI: BUFFER_STORE_DWORD [[CONV]],
9 define void @load_i8_to_f32(float addrspace(1)* noalias %out, i8 addrspace(1)* noalias %in) nounwind {
10 %load = load i8 addrspace(1)* %in, align 1
11 %cvt = uitofp i8 %load to float
12 store float %cvt, float addrspace(1)* %out, align 4
16 ; SI-LABEL: @load_v2i8_to_v2f32:
17 ; SI: BUFFER_LOAD_USHORT [[LOADREG:v[0-9]+]],
21 ; SI-DAG: V_CVT_F32_UBYTE1_e32 v[[HIRESULT:[0-9]+]], [[LOADREG]]
22 ; SI-DAG: V_CVT_F32_UBYTE0_e32 v[[LORESULT:[0-9]+]], [[LOADREG]]
23 ; SI: BUFFER_STORE_DWORDX2 v{{\[}}[[LORESULT]]:[[HIRESULT]]{{\]}},
24 define void @load_v2i8_to_v2f32(<2 x float> addrspace(1)* noalias %out, <2 x i8> addrspace(1)* noalias %in) nounwind {
25 %load = load <2 x i8> addrspace(1)* %in, align 1
26 %cvt = uitofp <2 x i8> %load to <2 x float>
27 store <2 x float> %cvt, <2 x float> addrspace(1)* %out, align 16
31 ; SI-LABEL: @load_v3i8_to_v3f32:
33 ; SI-NOT: V_CVT_F32_UBYTE3_e32
34 ; SI-DAG: V_CVT_F32_UBYTE2_e32
35 ; SI-DAG: V_CVT_F32_UBYTE1_e32
36 ; SI-DAG: V_CVT_F32_UBYTE0_e32
37 ; SI: BUFFER_STORE_DWORDX2 v{{\[}}[[LORESULT]]:[[HIRESULT]]{{\]}},
38 define void @load_v3i8_to_v3f32(<3 x float> addrspace(1)* noalias %out, <3 x i8> addrspace(1)* noalias %in) nounwind {
39 %load = load <3 x i8> addrspace(1)* %in, align 1
40 %cvt = uitofp <3 x i8> %load to <3 x float>
41 store <3 x float> %cvt, <3 x float> addrspace(1)* %out, align 16
45 ; SI-LABEL: @load_v4i8_to_v4f32:
46 ; We can't use BUFFER_LOAD_DWORD here, because the load is byte aligned, and
47 ; BUFFER_LOAD_DWORD requires dword alignment.
48 ; SI: BUFFER_LOAD_USHORT
49 ; SI: BUFFER_LOAD_USHORT
50 ; SI: V_OR_B32_e32 [[LOADREG:v[0-9]+]]
53 ; SI-DAG: V_CVT_F32_UBYTE3_e32 v[[HIRESULT:[0-9]+]], [[LOADREG]]
54 ; SI-DAG: V_CVT_F32_UBYTE2_e32 v{{[0-9]+}}, [[LOADREG]]
55 ; SI-DAG: V_CVT_F32_UBYTE1_e32 v{{[0-9]+}}, [[LOADREG]]
56 ; SI-DAG: V_CVT_F32_UBYTE0_e32 v[[LORESULT:[0-9]+]], [[LOADREG]]
57 ; SI: BUFFER_STORE_DWORDX4 v{{\[}}[[LORESULT]]:[[HIRESULT]]{{\]}},
58 define void @load_v4i8_to_v4f32(<4 x float> addrspace(1)* noalias %out, <4 x i8> addrspace(1)* noalias %in) nounwind {
59 %load = load <4 x i8> addrspace(1)* %in, align 1
60 %cvt = uitofp <4 x i8> %load to <4 x float>
61 store <4 x float> %cvt, <4 x float> addrspace(1)* %out, align 16
65 ; XXX - This should really still be able to use the V_CVT_F32_UBYTE0
66 ; for each component, but computeKnownBits doesn't handle vectors very
69 ; SI-LABEL: @load_v4i8_to_v4f32_2_uses:
70 ; SI: BUFFER_LOAD_UBYTE
71 ; SI: BUFFER_LOAD_UBYTE
72 ; SI: BUFFER_LOAD_UBYTE
73 ; SI: BUFFER_LOAD_UBYTE
74 ; SI: V_CVT_F32_UBYTE0_e32
75 ; SI: V_CVT_F32_UBYTE0_e32
76 ; SI: V_CVT_F32_UBYTE0_e32
77 ; SI: V_CVT_F32_UBYTE0_e32
79 ; XXX - replace with this when v4i8 loads aren't scalarized anymore.
80 ; XSI: BUFFER_LOAD_DWORD
81 ; XSI: V_CVT_F32_U32_e32
82 ; XSI: V_CVT_F32_U32_e32
83 ; XSI: V_CVT_F32_U32_e32
84 ; XSI: V_CVT_F32_U32_e32
86 define void @load_v4i8_to_v4f32_2_uses(<4 x float> addrspace(1)* noalias %out, <4 x i8> addrspace(1)* noalias %out2, <4 x i8> addrspace(1)* noalias %in) nounwind {
87 %load = load <4 x i8> addrspace(1)* %in, align 4
88 %cvt = uitofp <4 x i8> %load to <4 x float>
89 store <4 x float> %cvt, <4 x float> addrspace(1)* %out, align 16
90 %add = add <4 x i8> %load, <i8 9, i8 9, i8 9, i8 9> ; Second use of %load
91 store <4 x i8> %add, <4 x i8> addrspace(1)* %out2, align 4
95 ; Make sure this doesn't crash.
96 ; SI-LABEL: @load_v7i8_to_v7f32:
98 define void @load_v7i8_to_v7f32(<7 x float> addrspace(1)* noalias %out, <7 x i8> addrspace(1)* noalias %in) nounwind {
99 %load = load <7 x i8> addrspace(1)* %in, align 1
100 %cvt = uitofp <7 x i8> %load to <7 x float>
101 store <7 x float> %cvt, <7 x float> addrspace(1)* %out, align 16
105 ; SI-LABEL: @load_v8i8_to_v8f32:
106 ; SI: BUFFER_LOAD_DWORDX2 v{{\[}}[[LOLOAD:[0-9]+]]:[[HILOAD:[0-9]+]]{{\]}},
109 ; SI-DAG: V_CVT_F32_UBYTE3_e32 v{{[0-9]+}}, v[[LOLOAD]]
110 ; SI-DAG: V_CVT_F32_UBYTE2_e32 v{{[0-9]+}}, v[[LOLOAD]]
111 ; SI-DAG: V_CVT_F32_UBYTE1_e32 v{{[0-9]+}}, v[[LOLOAD]]
112 ; SI-DAG: V_CVT_F32_UBYTE0_e32 v{{[0-9]+}}, v[[LOLOAD]]
113 ; SI-DAG: V_CVT_F32_UBYTE3_e32 v{{[0-9]+}}, v[[HILOAD]]
114 ; SI-DAG: V_CVT_F32_UBYTE2_e32 v{{[0-9]+}}, v[[HILOAD]]
115 ; SI-DAG: V_CVT_F32_UBYTE1_e32 v{{[0-9]+}}, v[[HILOAD]]
116 ; SI-DAG: V_CVT_F32_UBYTE0_e32 v{{[0-9]+}}, v[[HILOAD]]
119 ; SI: BUFFER_STORE_DWORD
120 ; SI: BUFFER_STORE_DWORD
121 ; SI: BUFFER_STORE_DWORD
122 ; SI: BUFFER_STORE_DWORD
123 ; SI: BUFFER_STORE_DWORD
124 ; SI: BUFFER_STORE_DWORD
125 ; SI: BUFFER_STORE_DWORD
126 ; SI: BUFFER_STORE_DWORD
127 define void @load_v8i8_to_v8f32(<8 x float> addrspace(1)* noalias %out, <8 x i8> addrspace(1)* noalias %in) nounwind {
128 %load = load <8 x i8> addrspace(1)* %in, align 1
129 %cvt = uitofp <8 x i8> %load to <8 x float>
130 store <8 x float> %cvt, <8 x float> addrspace(1)* %out, align 16
134 ; SI-LABEL: @i8_zext_inreg_i32_to_f32:
135 ; SI: BUFFER_LOAD_DWORD [[LOADREG:v[0-9]+]],
136 ; SI: V_ADD_I32_e32 [[ADD:v[0-9]+]], 2, [[LOADREG]]
137 ; SI-NEXT: V_CVT_F32_UBYTE0_e32 [[CONV:v[0-9]+]], [[ADD]]
138 ; SI: BUFFER_STORE_DWORD [[CONV]],
139 define void @i8_zext_inreg_i32_to_f32(float addrspace(1)* noalias %out, i32 addrspace(1)* noalias %in) nounwind {
140 %load = load i32 addrspace(1)* %in, align 4
141 %add = add i32 %load, 2
142 %inreg = and i32 %add, 255
143 %cvt = uitofp i32 %inreg to float
144 store float %cvt, float addrspace(1)* %out, align 4
148 ; SI-LABEL: @i8_zext_inreg_hi1_to_f32:
149 define void @i8_zext_inreg_hi1_to_f32(float addrspace(1)* noalias %out, i32 addrspace(1)* noalias %in) nounwind {
150 %load = load i32 addrspace(1)* %in, align 4
151 %inreg = and i32 %load, 65280
152 %shr = lshr i32 %inreg, 8
153 %cvt = uitofp i32 %shr to float
154 store float %cvt, float addrspace(1)* %out, align 4
159 ; We don't get these ones because of the zext, but instcombine removes
160 ; them so it shouldn't really matter.
161 define void @i8_zext_i32_to_f32(float addrspace(1)* noalias %out, i8 addrspace(1)* noalias %in) nounwind {
162 %load = load i8 addrspace(1)* %in, align 1
163 %ext = zext i8 %load to i32
164 %cvt = uitofp i32 %ext to float
165 store float %cvt, float addrspace(1)* %out, align 4
169 define void @v4i8_zext_v4i32_to_v4f32(<4 x float> addrspace(1)* noalias %out, <4 x i8> addrspace(1)* noalias %in) nounwind {
170 %load = load <4 x i8> addrspace(1)* %in, align 1
171 %ext = zext <4 x i8> %load to <4 x i32>
172 %cvt = uitofp <4 x i32> %ext to <4 x float>
173 store <4 x float> %cvt, <4 x float> addrspace(1)* %out, align 16