1 ; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=R600 -check-prefix=FUNC %s
2 ; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
5 ; FUNC-LABEL: {{^}}v_fsub_f32:
6 ; SI: v_subrev_f32_e32 {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
7 define void @v_fsub_f32(float addrspace(1)* %out, float addrspace(1)* %in) {
8 %b_ptr = getelementptr float addrspace(1)* %in, i32 1
9 %a = load float addrspace(1)* %in, align 4
10 %b = load float addrspace(1)* %b_ptr, align 4
11 %result = fsub float %a, %b
12 store float %result, float addrspace(1)* %out, align 4
16 ; FUNC-LABEL: {{^}}s_fsub_f32:
17 ; R600: ADD {{\** *}}T{{[0-9]+\.[XYZW]}}, KC0[2].Z, -KC0[2].W
19 ; SI: v_sub_f32_e32 {{v[0-9]+}}, {{s[0-9]+}}, {{v[0-9]+}}
20 define void @s_fsub_f32(float addrspace(1)* %out, float %a, float %b) {
21 %sub = fsub float %a, %b
22 store float %sub, float addrspace(1)* %out, align 4
26 declare float @llvm.R600.load.input(i32) readnone
28 declare void @llvm.AMDGPU.store.output(float, i32)
30 ; FUNC-LABEL: {{^}}fsub_v2f32:
31 ; R600-DAG: ADD {{\** *}}T{{[0-9]+\.[XYZW]}}, KC0[3].X, -KC0[3].Z
32 ; R600-DAG: ADD {{\** *}}T{{[0-9]+\.[XYZW]}}, KC0[2].W, -KC0[3].Y
34 ; FIXME: Should be using SGPR directly for first operand
35 ; SI: v_subrev_f32_e32 {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
36 ; SI: v_subrev_f32_e32 {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
37 define void @fsub_v2f32(<2 x float> addrspace(1)* %out, <2 x float> %a, <2 x float> %b) {
38 %sub = fsub <2 x float> %a, %b
39 store <2 x float> %sub, <2 x float> addrspace(1)* %out, align 8
43 ; FUNC-LABEL: {{^}}v_fsub_v4f32:
44 ; R600: ADD {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], -T[0-9]+\.[XYZW]}}
45 ; R600: ADD {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], -T[0-9]+\.[XYZW]}}
46 ; R600: ADD {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], -T[0-9]+\.[XYZW]}}
47 ; R600: ADD {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], -T[0-9]+\.[XYZW]}}
49 ; SI: v_subrev_f32_e32 {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
50 ; SI: v_subrev_f32_e32 {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
51 ; SI: v_subrev_f32_e32 {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
52 ; SI: v_subrev_f32_e32 {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
53 define void @v_fsub_v4f32(<4 x float> addrspace(1)* %out, <4 x float> addrspace(1)* %in) {
54 %b_ptr = getelementptr <4 x float> addrspace(1)* %in, i32 1
55 %a = load <4 x float> addrspace(1)* %in, align 16
56 %b = load <4 x float> addrspace(1)* %b_ptr, align 16
57 %result = fsub <4 x float> %a, %b
58 store <4 x float> %result, <4 x float> addrspace(1)* %out, align 16
62 ; FIXME: Should be using SGPR directly for first operand
64 ; FUNC-LABEL: {{^}}s_fsub_v4f32:
65 ; SI: v_subrev_f32_e32 {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
66 ; SI: v_subrev_f32_e32 {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
67 ; SI: v_subrev_f32_e32 {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
68 ; SI: v_subrev_f32_e32 {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
70 define void @s_fsub_v4f32(<4 x float> addrspace(1)* %out, <4 x float> %a, <4 x float> %b) {
71 %result = fsub <4 x float> %a, %b
72 store <4 x float> %result, <4 x float> addrspace(1)* %out, align 16