1 ; RUN: llc -march=r600 -mcpu=verde -verify-machineinstrs < %s | FileCheck %s
3 ; Use a 64-bit value with lo bits that can be represented as an inline constant
4 ; CHECK-LABEL: {{^}}i64_imm_inline_lo:
5 ; CHECK: S_MOV_B32 [[LO:s[0-9]+]], 5
6 ; CHECK: V_MOV_B32_e32 v[[LO_VGPR:[0-9]+]], [[LO]]
7 ; CHECK: BUFFER_STORE_DWORDX2 v{{\[}}[[LO_VGPR]]:
8 define void @i64_imm_inline_lo(i64 addrspace(1) *%out) {
10 store i64 1311768464867721221, i64 addrspace(1) *%out ; 0x1234567800000005
14 ; Use a 64-bit value with hi bits that can be represented as an inline constant
15 ; CHECK-LABEL: {{^}}i64_imm_inline_hi:
16 ; CHECK: S_MOV_B32 [[HI:s[0-9]+]], 5
17 ; CHECK: V_MOV_B32_e32 v[[HI_VGPR:[0-9]+]], [[HI]]
18 ; CHECK: BUFFER_STORE_DWORDX2 v{{\[[0-9]+:}}[[HI_VGPR]]
19 define void @i64_imm_inline_hi(i64 addrspace(1) *%out) {
21 store i64 21780256376, i64 addrspace(1) *%out ; 0x0000000512345678
25 ; CHECK-LABEL: {{^}}store_inline_imm_0.0_f32
26 ; CHECK: V_MOV_B32_e32 [[REG:v[0-9]+]], 0{{$}}
27 ; CHECK-NEXT: BUFFER_STORE_DWORD [[REG]]
28 define void @store_inline_imm_0.0_f32(float addrspace(1)* %out) {
29 store float 0.0, float addrspace(1)* %out
33 ; CHECK-LABEL: {{^}}store_inline_imm_0.5_f32
34 ; CHECK: V_MOV_B32_e32 [[REG:v[0-9]+]], 0.5{{$}}
35 ; CHECK-NEXT: BUFFER_STORE_DWORD [[REG]]
36 define void @store_inline_imm_0.5_f32(float addrspace(1)* %out) {
37 store float 0.5, float addrspace(1)* %out
41 ; CHECK-LABEL: {{^}}store_inline_imm_m_0.5_f32
42 ; CHECK: V_MOV_B32_e32 [[REG:v[0-9]+]], -0.5{{$}}
43 ; CHECK-NEXT: BUFFER_STORE_DWORD [[REG]]
44 define void @store_inline_imm_m_0.5_f32(float addrspace(1)* %out) {
45 store float -0.5, float addrspace(1)* %out
49 ; CHECK-LABEL: {{^}}store_inline_imm_1.0_f32
50 ; CHECK: V_MOV_B32_e32 [[REG:v[0-9]+]], 1.0{{$}}
51 ; CHECK-NEXT: BUFFER_STORE_DWORD [[REG]]
52 define void @store_inline_imm_1.0_f32(float addrspace(1)* %out) {
53 store float 1.0, float addrspace(1)* %out
57 ; CHECK-LABEL: {{^}}store_inline_imm_m_1.0_f32
58 ; CHECK: V_MOV_B32_e32 [[REG:v[0-9]+]], -1.0{{$}}
59 ; CHECK-NEXT: BUFFER_STORE_DWORD [[REG]]
60 define void @store_inline_imm_m_1.0_f32(float addrspace(1)* %out) {
61 store float -1.0, float addrspace(1)* %out
65 ; CHECK-LABEL: {{^}}store_inline_imm_2.0_f32
66 ; CHECK: V_MOV_B32_e32 [[REG:v[0-9]+]], 2.0{{$}}
67 ; CHECK-NEXT: BUFFER_STORE_DWORD [[REG]]
68 define void @store_inline_imm_2.0_f32(float addrspace(1)* %out) {
69 store float 2.0, float addrspace(1)* %out
73 ; CHECK-LABEL: {{^}}store_inline_imm_m_2.0_f32
74 ; CHECK: V_MOV_B32_e32 [[REG:v[0-9]+]], -2.0{{$}}
75 ; CHECK-NEXT: BUFFER_STORE_DWORD [[REG]]
76 define void @store_inline_imm_m_2.0_f32(float addrspace(1)* %out) {
77 store float -2.0, float addrspace(1)* %out
81 ; CHECK-LABEL: {{^}}store_inline_imm_4.0_f32
82 ; CHECK: V_MOV_B32_e32 [[REG:v[0-9]+]], 4.0{{$}}
83 ; CHECK-NEXT: BUFFER_STORE_DWORD [[REG]]
84 define void @store_inline_imm_4.0_f32(float addrspace(1)* %out) {
85 store float 4.0, float addrspace(1)* %out
89 ; CHECK-LABEL: {{^}}store_inline_imm_m_4.0_f32
90 ; CHECK: V_MOV_B32_e32 [[REG:v[0-9]+]], -4.0{{$}}
91 ; CHECK-NEXT: BUFFER_STORE_DWORD [[REG]]
92 define void @store_inline_imm_m_4.0_f32(float addrspace(1)* %out) {
93 store float -4.0, float addrspace(1)* %out
97 ; CHECK-LABEL: {{^}}store_literal_imm_f32:
98 ; CHECK: V_MOV_B32_e32 [[REG:v[0-9]+]], 0x45800000
99 ; CHECK-NEXT: BUFFER_STORE_DWORD [[REG]]
100 define void @store_literal_imm_f32(float addrspace(1)* %out) {
101 store float 4096.0, float addrspace(1)* %out
105 ; CHECK-LABEL: {{^}}add_inline_imm_0.0_f32
106 ; CHECK: S_LOAD_DWORD [[VAL:s[0-9]+]]
107 ; CHECK: V_ADD_F32_e64 [[REG:v[0-9]+]], [[VAL]], 0.0{{$}}
108 ; CHECK-NEXT: BUFFER_STORE_DWORD [[REG]]
109 define void @add_inline_imm_0.0_f32(float addrspace(1)* %out, float %x) {
110 %y = fadd float %x, 0.0
111 store float %y, float addrspace(1)* %out
115 ; CHECK-LABEL: {{^}}add_inline_imm_0.5_f32
116 ; CHECK: S_LOAD_DWORD [[VAL:s[0-9]+]]
117 ; CHECK: V_ADD_F32_e64 [[REG:v[0-9]+]], [[VAL]], 0.5{{$}}
118 ; CHECK-NEXT: BUFFER_STORE_DWORD [[REG]]
119 define void @add_inline_imm_0.5_f32(float addrspace(1)* %out, float %x) {
120 %y = fadd float %x, 0.5
121 store float %y, float addrspace(1)* %out
125 ; CHECK-LABEL: {{^}}add_inline_imm_neg_0.5_f32
126 ; CHECK: S_LOAD_DWORD [[VAL:s[0-9]+]]
127 ; CHECK: V_ADD_F32_e64 [[REG:v[0-9]+]], [[VAL]], -0.5{{$}}
128 ; CHECK-NEXT: BUFFER_STORE_DWORD [[REG]]
129 define void @add_inline_imm_neg_0.5_f32(float addrspace(1)* %out, float %x) {
130 %y = fadd float %x, -0.5
131 store float %y, float addrspace(1)* %out
135 ; CHECK-LABEL: {{^}}add_inline_imm_1.0_f32
136 ; CHECK: S_LOAD_DWORD [[VAL:s[0-9]+]]
137 ; CHECK: V_ADD_F32_e64 [[REG:v[0-9]+]], [[VAL]], 1.0{{$}}
138 ; CHECK-NEXT: BUFFER_STORE_DWORD [[REG]]
139 define void @add_inline_imm_1.0_f32(float addrspace(1)* %out, float %x) {
140 %y = fadd float %x, 1.0
141 store float %y, float addrspace(1)* %out
145 ; CHECK-LABEL: {{^}}add_inline_imm_neg_1.0_f32
146 ; CHECK: S_LOAD_DWORD [[VAL:s[0-9]+]]
147 ; CHECK: V_ADD_F32_e64 [[REG:v[0-9]+]], [[VAL]], -1.0{{$}}
148 ; CHECK-NEXT: BUFFER_STORE_DWORD [[REG]]
149 define void @add_inline_imm_neg_1.0_f32(float addrspace(1)* %out, float %x) {
150 %y = fadd float %x, -1.0
151 store float %y, float addrspace(1)* %out
155 ; CHECK-LABEL: {{^}}add_inline_imm_2.0_f32
156 ; CHECK: S_LOAD_DWORD [[VAL:s[0-9]+]]
157 ; CHECK: V_ADD_F32_e64 [[REG:v[0-9]+]], [[VAL]], 2.0{{$}}
158 ; CHECK-NEXT: BUFFER_STORE_DWORD [[REG]]
159 define void @add_inline_imm_2.0_f32(float addrspace(1)* %out, float %x) {
160 %y = fadd float %x, 2.0
161 store float %y, float addrspace(1)* %out
165 ; CHECK-LABEL: {{^}}add_inline_imm_neg_2.0_f32
166 ; CHECK: S_LOAD_DWORD [[VAL:s[0-9]+]]
167 ; CHECK: V_ADD_F32_e64 [[REG:v[0-9]+]], [[VAL]], -2.0{{$}}
168 ; CHECK-NEXT: BUFFER_STORE_DWORD [[REG]]
169 define void @add_inline_imm_neg_2.0_f32(float addrspace(1)* %out, float %x) {
170 %y = fadd float %x, -2.0
171 store float %y, float addrspace(1)* %out
175 ; CHECK-LABEL: {{^}}add_inline_imm_4.0_f32
176 ; CHECK: S_LOAD_DWORD [[VAL:s[0-9]+]]
177 ; CHECK: V_ADD_F32_e64 [[REG:v[0-9]+]], [[VAL]], 4.0{{$}}
178 ; CHECK-NEXT: BUFFER_STORE_DWORD [[REG]]
179 define void @add_inline_imm_4.0_f32(float addrspace(1)* %out, float %x) {
180 %y = fadd float %x, 4.0
181 store float %y, float addrspace(1)* %out
185 ; CHECK-LABEL: {{^}}add_inline_imm_neg_4.0_f32
186 ; CHECK: S_LOAD_DWORD [[VAL:s[0-9]+]]
187 ; CHECK: V_ADD_F32_e64 [[REG:v[0-9]+]], [[VAL]], -4.0{{$}}
188 ; CHECK-NEXT: BUFFER_STORE_DWORD [[REG]]
189 define void @add_inline_imm_neg_4.0_f32(float addrspace(1)* %out, float %x) {
190 %y = fadd float %x, -4.0
191 store float %y, float addrspace(1)* %out