1 ; RUN: llc -march=amdgcn -mcpu=verde -verify-machineinstrs < %s | FileCheck %s
3 ; Use a 64-bit value with lo bits that can be represented as an inline constant
4 ; CHECK-LABEL: {{^}}i64_imm_inline_lo:
5 ; CHECK: s_mov_b32 [[LO:s[0-9]+]], 5
6 ; CHECK: v_mov_b32_e32 v[[LO_VGPR:[0-9]+]], [[LO]]
7 ; CHECK: buffer_store_dwordx2 v{{\[}}[[LO_VGPR]]:
8 define void @i64_imm_inline_lo(i64 addrspace(1) *%out) {
10 store i64 1311768464867721221, i64 addrspace(1) *%out ; 0x1234567800000005
14 ; Use a 64-bit value with hi bits that can be represented as an inline constant
15 ; CHECK-LABEL: {{^}}i64_imm_inline_hi:
16 ; CHECK: s_mov_b32 [[HI:s[0-9]+]], 5
17 ; CHECK: v_mov_b32_e32 v[[HI_VGPR:[0-9]+]], [[HI]]
18 ; CHECK: buffer_store_dwordx2 v{{\[[0-9]+:}}[[HI_VGPR]]
19 define void @i64_imm_inline_hi(i64 addrspace(1) *%out) {
21 store i64 21780256376, i64 addrspace(1) *%out ; 0x0000000512345678
25 ; CHECK-LABEL: {{^}}store_inline_imm_0.0_f32
26 ; CHECK: v_mov_b32_e32 [[REG:v[0-9]+]], 0{{$}}
27 ; CHECK: buffer_store_dword [[REG]]
28 define void @store_inline_imm_0.0_f32(float addrspace(1)* %out) {
29 store float 0.0, float addrspace(1)* %out
33 ; CHECK-LABEL: {{^}}store_imm_neg_0.0_f32
34 ; CHECK: v_mov_b32_e32 [[REG:v[0-9]+]], 0x80000000
35 ; CHECK: buffer_store_dword [[REG]]
36 define void @store_imm_neg_0.0_f32(float addrspace(1)* %out) {
37 store float -0.0, float addrspace(1)* %out
41 ; CHECK-LABEL: {{^}}store_inline_imm_0.5_f32
42 ; CHECK: v_mov_b32_e32 [[REG:v[0-9]+]], 0.5{{$}}
43 ; CHECK: buffer_store_dword [[REG]]
44 define void @store_inline_imm_0.5_f32(float addrspace(1)* %out) {
45 store float 0.5, float addrspace(1)* %out
49 ; CHECK-LABEL: {{^}}store_inline_imm_m_0.5_f32
50 ; CHECK: v_mov_b32_e32 [[REG:v[0-9]+]], -0.5{{$}}
51 ; CHECK: buffer_store_dword [[REG]]
52 define void @store_inline_imm_m_0.5_f32(float addrspace(1)* %out) {
53 store float -0.5, float addrspace(1)* %out
57 ; CHECK-LABEL: {{^}}store_inline_imm_1.0_f32
58 ; CHECK: v_mov_b32_e32 [[REG:v[0-9]+]], 1.0{{$}}
59 ; CHECK: buffer_store_dword [[REG]]
60 define void @store_inline_imm_1.0_f32(float addrspace(1)* %out) {
61 store float 1.0, float addrspace(1)* %out
65 ; CHECK-LABEL: {{^}}store_inline_imm_m_1.0_f32
66 ; CHECK: v_mov_b32_e32 [[REG:v[0-9]+]], -1.0{{$}}
67 ; CHECK: buffer_store_dword [[REG]]
68 define void @store_inline_imm_m_1.0_f32(float addrspace(1)* %out) {
69 store float -1.0, float addrspace(1)* %out
73 ; CHECK-LABEL: {{^}}store_inline_imm_2.0_f32
74 ; CHECK: v_mov_b32_e32 [[REG:v[0-9]+]], 2.0{{$}}
75 ; CHECK: buffer_store_dword [[REG]]
76 define void @store_inline_imm_2.0_f32(float addrspace(1)* %out) {
77 store float 2.0, float addrspace(1)* %out
81 ; CHECK-LABEL: {{^}}store_inline_imm_m_2.0_f32
82 ; CHECK: v_mov_b32_e32 [[REG:v[0-9]+]], -2.0{{$}}
83 ; CHECK: buffer_store_dword [[REG]]
84 define void @store_inline_imm_m_2.0_f32(float addrspace(1)* %out) {
85 store float -2.0, float addrspace(1)* %out
89 ; CHECK-LABEL: {{^}}store_inline_imm_4.0_f32
90 ; CHECK: v_mov_b32_e32 [[REG:v[0-9]+]], 4.0{{$}}
91 ; CHECK: buffer_store_dword [[REG]]
92 define void @store_inline_imm_4.0_f32(float addrspace(1)* %out) {
93 store float 4.0, float addrspace(1)* %out
97 ; CHECK-LABEL: {{^}}store_inline_imm_m_4.0_f32
98 ; CHECK: v_mov_b32_e32 [[REG:v[0-9]+]], -4.0{{$}}
99 ; CHECK: buffer_store_dword [[REG]]
100 define void @store_inline_imm_m_4.0_f32(float addrspace(1)* %out) {
101 store float -4.0, float addrspace(1)* %out
105 ; CHECK-LABEL: {{^}}store_literal_imm_f32:
106 ; CHECK: v_mov_b32_e32 [[REG:v[0-9]+]], 0x45800000
107 ; CHECK: buffer_store_dword [[REG]]
108 define void @store_literal_imm_f32(float addrspace(1)* %out) {
109 store float 4096.0, float addrspace(1)* %out
113 ; CHECK-LABEL: {{^}}add_inline_imm_0.0_f32
114 ; CHECK: s_load_dword [[VAL:s[0-9]+]]
115 ; CHECK: v_add_f32_e64 [[REG:v[0-9]+]], 0, [[VAL]]{{$}}
116 ; CHECK: buffer_store_dword [[REG]]
117 define void @add_inline_imm_0.0_f32(float addrspace(1)* %out, float %x) {
118 %y = fadd float %x, 0.0
119 store float %y, float addrspace(1)* %out
123 ; CHECK-LABEL: {{^}}add_inline_imm_0.5_f32
124 ; CHECK: s_load_dword [[VAL:s[0-9]+]]
125 ; CHECK: v_add_f32_e64 [[REG:v[0-9]+]], 0.5, [[VAL]]{{$}}
126 ; CHECK: buffer_store_dword [[REG]]
127 define void @add_inline_imm_0.5_f32(float addrspace(1)* %out, float %x) {
128 %y = fadd float %x, 0.5
129 store float %y, float addrspace(1)* %out
133 ; CHECK-LABEL: {{^}}add_inline_imm_neg_0.5_f32
134 ; CHECK: s_load_dword [[VAL:s[0-9]+]]
135 ; CHECK: v_add_f32_e64 [[REG:v[0-9]+]], -0.5, [[VAL]]{{$}}
136 ; CHECK: buffer_store_dword [[REG]]
137 define void @add_inline_imm_neg_0.5_f32(float addrspace(1)* %out, float %x) {
138 %y = fadd float %x, -0.5
139 store float %y, float addrspace(1)* %out
143 ; CHECK-LABEL: {{^}}add_inline_imm_1.0_f32
144 ; CHECK: s_load_dword [[VAL:s[0-9]+]]
145 ; CHECK: v_add_f32_e64 [[REG:v[0-9]+]], 1.0, [[VAL]]{{$}}
146 ; CHECK: buffer_store_dword [[REG]]
147 define void @add_inline_imm_1.0_f32(float addrspace(1)* %out, float %x) {
148 %y = fadd float %x, 1.0
149 store float %y, float addrspace(1)* %out
153 ; CHECK-LABEL: {{^}}add_inline_imm_neg_1.0_f32
154 ; CHECK: s_load_dword [[VAL:s[0-9]+]]
155 ; CHECK: v_add_f32_e64 [[REG:v[0-9]+]], -1.0, [[VAL]]{{$}}
156 ; CHECK: buffer_store_dword [[REG]]
157 define void @add_inline_imm_neg_1.0_f32(float addrspace(1)* %out, float %x) {
158 %y = fadd float %x, -1.0
159 store float %y, float addrspace(1)* %out
163 ; CHECK-LABEL: {{^}}add_inline_imm_2.0_f32
164 ; CHECK: s_load_dword [[VAL:s[0-9]+]]
165 ; CHECK: v_add_f32_e64 [[REG:v[0-9]+]], 2.0, [[VAL]]{{$}}
166 ; CHECK: buffer_store_dword [[REG]]
167 define void @add_inline_imm_2.0_f32(float addrspace(1)* %out, float %x) {
168 %y = fadd float %x, 2.0
169 store float %y, float addrspace(1)* %out
173 ; CHECK-LABEL: {{^}}add_inline_imm_neg_2.0_f32
174 ; CHECK: s_load_dword [[VAL:s[0-9]+]]
175 ; CHECK: v_add_f32_e64 [[REG:v[0-9]+]], -2.0, [[VAL]]{{$}}
176 ; CHECK: buffer_store_dword [[REG]]
177 define void @add_inline_imm_neg_2.0_f32(float addrspace(1)* %out, float %x) {
178 %y = fadd float %x, -2.0
179 store float %y, float addrspace(1)* %out
183 ; CHECK-LABEL: {{^}}add_inline_imm_4.0_f32
184 ; CHECK: s_load_dword [[VAL:s[0-9]+]]
185 ; CHECK: v_add_f32_e64 [[REG:v[0-9]+]], 4.0, [[VAL]]{{$}}
186 ; CHECK: buffer_store_dword [[REG]]
187 define void @add_inline_imm_4.0_f32(float addrspace(1)* %out, float %x) {
188 %y = fadd float %x, 4.0
189 store float %y, float addrspace(1)* %out
193 ; CHECK-LABEL: {{^}}add_inline_imm_neg_4.0_f32
194 ; CHECK: s_load_dword [[VAL:s[0-9]+]]
195 ; CHECK: v_add_f32_e64 [[REG:v[0-9]+]], -4.0, [[VAL]]{{$}}
196 ; CHECK: buffer_store_dword [[REG]]
197 define void @add_inline_imm_neg_4.0_f32(float addrspace(1)* %out, float %x) {
198 %y = fadd float %x, -4.0
199 store float %y, float addrspace(1)* %out
203 ; CHECK-LABEL: @commute_add_inline_imm_0.5_f32
204 ; CHECK: buffer_load_dword [[VAL:v[0-9]+]]
205 ; CHECK: v_add_f32_e32 [[REG:v[0-9]+]], 0.5, [[VAL]]
206 ; CHECK: buffer_store_dword [[REG]]
207 define void @commute_add_inline_imm_0.5_f32(float addrspace(1)* %out, float addrspace(1)* %in) {
208 %x = load float addrspace(1)* %in
209 %y = fadd float %x, 0.5
210 store float %y, float addrspace(1)* %out
214 ; CHECK-LABEL: @commute_add_literal_f32
215 ; CHECK: buffer_load_dword [[VAL:v[0-9]+]]
216 ; CHECK: v_add_f32_e32 [[REG:v[0-9]+]], 0x44800000, [[VAL]]
217 ; CHECK: buffer_store_dword [[REG]]
218 define void @commute_add_literal_f32(float addrspace(1)* %out, float addrspace(1)* %in) {
219 %x = load float addrspace(1)* %in
220 %y = fadd float %x, 1024.0
221 store float %y, float addrspace(1)* %out
225 ; CHECK-LABEL: {{^}}add_inline_imm_1_f32
226 ; CHECK: s_load_dword [[VAL:s[0-9]+]]
227 ; CHECK: v_add_f32_e64 [[REG:v[0-9]+]], 1, [[VAL]]{{$}}
228 ; CHECK: buffer_store_dword [[REG]]
229 define void @add_inline_imm_1_f32(float addrspace(1)* %out, float %x) {
230 %y = fadd float %x, 0x36a0000000000000
231 store float %y, float addrspace(1)* %out
235 ; CHECK-LABEL: {{^}}add_inline_imm_2_f32
236 ; CHECK: s_load_dword [[VAL:s[0-9]+]]
237 ; CHECK: v_add_f32_e64 [[REG:v[0-9]+]], 2, [[VAL]]{{$}}
238 ; CHECK: buffer_store_dword [[REG]]
239 define void @add_inline_imm_2_f32(float addrspace(1)* %out, float %x) {
240 %y = fadd float %x, 0x36b0000000000000
241 store float %y, float addrspace(1)* %out
245 ; CHECK-LABEL: {{^}}add_inline_imm_16_f32
246 ; CHECK: s_load_dword [[VAL:s[0-9]+]]
247 ; CHECK: v_add_f32_e64 [[REG:v[0-9]+]], 16, [[VAL]]
248 ; CHECK: buffer_store_dword [[REG]]
249 define void @add_inline_imm_16_f32(float addrspace(1)* %out, float %x) {
250 %y = fadd float %x, 0x36e0000000000000
251 store float %y, float addrspace(1)* %out
255 ; CHECK-LABEL: {{^}}add_inline_imm_neg_1_f32
256 ; CHECK: s_load_dword [[VAL:s[0-9]+]]
257 ; CHECK: v_add_f32_e64 [[REG:v[0-9]+]], -1, [[VAL]]
258 ; CHECK: buffer_store_dword [[REG]]
259 define void @add_inline_imm_neg_1_f32(float addrspace(1)* %out, float %x) {
260 %y = fadd float %x, 0xffffffffe0000000
261 store float %y, float addrspace(1)* %out
265 ; CHECK-LABEL: {{^}}add_inline_imm_neg_2_f32
266 ; CHECK: s_load_dword [[VAL:s[0-9]+]]
267 ; CHECK: v_add_f32_e64 [[REG:v[0-9]+]], -2, [[VAL]]
268 ; CHECK: buffer_store_dword [[REG]]
269 define void @add_inline_imm_neg_2_f32(float addrspace(1)* %out, float %x) {
270 %y = fadd float %x, 0xffffffffc0000000
271 store float %y, float addrspace(1)* %out
275 ; CHECK-LABEL: {{^}}add_inline_imm_neg_16_f32
276 ; CHECK: s_load_dword [[VAL:s[0-9]+]]
277 ; CHECK: v_add_f32_e64 [[REG:v[0-9]+]], -16, [[VAL]]
278 ; CHECK: buffer_store_dword [[REG]]
279 define void @add_inline_imm_neg_16_f32(float addrspace(1)* %out, float %x) {
280 %y = fadd float %x, 0xfffffffe00000000
281 store float %y, float addrspace(1)* %out
285 ; CHECK-LABEL: {{^}}add_inline_imm_63_f32
286 ; CHECK: s_load_dword [[VAL:s[0-9]+]]
287 ; CHECK: v_add_f32_e64 [[REG:v[0-9]+]], 63, [[VAL]]
288 ; CHECK: buffer_store_dword [[REG]]
289 define void @add_inline_imm_63_f32(float addrspace(1)* %out, float %x) {
290 %y = fadd float %x, 0x36ff800000000000
291 store float %y, float addrspace(1)* %out
295 ; CHECK-LABEL: {{^}}add_inline_imm_64_f32
296 ; CHECK: s_load_dword [[VAL:s[0-9]+]]
297 ; CHECK: v_add_f32_e64 [[REG:v[0-9]+]], 64, [[VAL]]
298 ; CHECK: buffer_store_dword [[REG]]
299 define void @add_inline_imm_64_f32(float addrspace(1)* %out, float %x) {
300 %y = fadd float %x, 0x3700000000000000
301 store float %y, float addrspace(1)* %out
305 ; CHECK-LABEL: {{^}}add_inline_imm_0.0_f64
306 ; CHECK: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0xb
307 ; CHECK: v_add_f64 [[REG:v\[[0-9]+:[0-9]+\]]], 0, [[VAL]]
308 ; CHECK: buffer_store_dwordx2 [[REG]]
309 define void @add_inline_imm_0.0_f64(double addrspace(1)* %out, double %x) {
310 %y = fadd double %x, 0.0
311 store double %y, double addrspace(1)* %out
315 ; CHECK-LABEL: {{^}}add_inline_imm_0.5_f64
316 ; CHECK: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0xb
317 ; CHECK: v_add_f64 [[REG:v\[[0-9]+:[0-9]+\]]], 0.5, [[VAL]]
318 ; CHECK: buffer_store_dwordx2 [[REG]]
319 define void @add_inline_imm_0.5_f64(double addrspace(1)* %out, double %x) {
320 %y = fadd double %x, 0.5
321 store double %y, double addrspace(1)* %out
325 ; CHECK-LABEL: {{^}}add_inline_imm_neg_0.5_f64
326 ; CHECK: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0xb
327 ; CHECK: v_add_f64 [[REG:v\[[0-9]+:[0-9]+\]]], -0.5, [[VAL]]
328 ; CHECK: buffer_store_dwordx2 [[REG]]
329 define void @add_inline_imm_neg_0.5_f64(double addrspace(1)* %out, double %x) {
330 %y = fadd double %x, -0.5
331 store double %y, double addrspace(1)* %out
335 ; CHECK-LABEL: {{^}}add_inline_imm_1.0_f64
336 ; CHECK: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0xb
337 ; CHECK: v_add_f64 [[REG:v\[[0-9]+:[0-9]+\]]], 1.0, [[VAL]]
338 ; CHECK: buffer_store_dwordx2 [[REG]]
339 define void @add_inline_imm_1.0_f64(double addrspace(1)* %out, double %x) {
340 %y = fadd double %x, 1.0
341 store double %y, double addrspace(1)* %out
345 ; CHECK-LABEL: {{^}}add_inline_imm_neg_1.0_f64
346 ; CHECK: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0xb
347 ; CHECK: v_add_f64 [[REG:v\[[0-9]+:[0-9]+\]]], -1.0, [[VAL]]
348 ; CHECK: buffer_store_dwordx2 [[REG]]
349 define void @add_inline_imm_neg_1.0_f64(double addrspace(1)* %out, double %x) {
350 %y = fadd double %x, -1.0
351 store double %y, double addrspace(1)* %out
355 ; CHECK-LABEL: {{^}}add_inline_imm_2.0_f64
356 ; CHECK: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0xb
357 ; CHECK: v_add_f64 [[REG:v\[[0-9]+:[0-9]+\]]], 2.0, [[VAL]]
358 ; CHECK: buffer_store_dwordx2 [[REG]]
359 define void @add_inline_imm_2.0_f64(double addrspace(1)* %out, double %x) {
360 %y = fadd double %x, 2.0
361 store double %y, double addrspace(1)* %out
365 ; CHECK-LABEL: {{^}}add_inline_imm_neg_2.0_f64
366 ; CHECK: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0xb
367 ; CHECK: v_add_f64 [[REG:v\[[0-9]+:[0-9]+\]]], -2.0, [[VAL]]
368 ; CHECK: buffer_store_dwordx2 [[REG]]
369 define void @add_inline_imm_neg_2.0_f64(double addrspace(1)* %out, double %x) {
370 %y = fadd double %x, -2.0
371 store double %y, double addrspace(1)* %out
375 ; CHECK-LABEL: {{^}}add_inline_imm_4.0_f64
376 ; CHECK: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0xb
377 ; CHECK: v_add_f64 [[REG:v\[[0-9]+:[0-9]+\]]], 4.0, [[VAL]]
378 ; CHECK: buffer_store_dwordx2 [[REG]]
379 define void @add_inline_imm_4.0_f64(double addrspace(1)* %out, double %x) {
380 %y = fadd double %x, 4.0
381 store double %y, double addrspace(1)* %out
385 ; CHECK-LABEL: {{^}}add_inline_imm_neg_4.0_f64
386 ; CHECK: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0xb
387 ; CHECK: v_add_f64 [[REG:v\[[0-9]+:[0-9]+\]]], -4.0, [[VAL]]
388 ; CHECK: buffer_store_dwordx2 [[REG]]
389 define void @add_inline_imm_neg_4.0_f64(double addrspace(1)* %out, double %x) {
390 %y = fadd double %x, -4.0
391 store double %y, double addrspace(1)* %out
396 ; CHECK-LABEL: {{^}}add_inline_imm_1_f64
397 ; CHECK: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0xb
398 ; CHECK: v_add_f64 [[REG:v\[[0-9]+:[0-9]+\]]], 1, [[VAL]]
399 ; CHECK: buffer_store_dwordx2 [[REG]]
400 define void @add_inline_imm_1_f64(double addrspace(1)* %out, double %x) {
401 %y = fadd double %x, 0x0000000000000001
402 store double %y, double addrspace(1)* %out
406 ; CHECK-LABEL: {{^}}add_inline_imm_2_f64
407 ; CHECK: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0xb
408 ; CHECK: v_add_f64 [[REG:v\[[0-9]+:[0-9]+\]]], 2, [[VAL]]
409 ; CHECK: buffer_store_dwordx2 [[REG]]
410 define void @add_inline_imm_2_f64(double addrspace(1)* %out, double %x) {
411 %y = fadd double %x, 0x0000000000000002
412 store double %y, double addrspace(1)* %out
416 ; CHECK-LABEL: {{^}}add_inline_imm_16_f64
417 ; CHECK: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0xb
418 ; CHECK: v_add_f64 [[REG:v\[[0-9]+:[0-9]+\]]], 16, [[VAL]]
419 ; CHECK: buffer_store_dwordx2 [[REG]]
420 define void @add_inline_imm_16_f64(double addrspace(1)* %out, double %x) {
421 %y = fadd double %x, 0x0000000000000010
422 store double %y, double addrspace(1)* %out
426 ; CHECK-LABEL: {{^}}add_inline_imm_neg_1_f64
427 ; CHECK: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0xb
428 ; CHECK: v_add_f64 [[REG:v\[[0-9]+:[0-9]+\]]], -1, [[VAL]]
429 ; CHECK: buffer_store_dwordx2 [[REG]]
430 define void @add_inline_imm_neg_1_f64(double addrspace(1)* %out, double %x) {
431 %y = fadd double %x, 0xffffffffffffffff
432 store double %y, double addrspace(1)* %out
436 ; CHECK-LABEL: {{^}}add_inline_imm_neg_2_f64
437 ; CHECK: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0xb
438 ; CHECK: v_add_f64 [[REG:v\[[0-9]+:[0-9]+\]]], -2, [[VAL]]
439 ; CHECK: buffer_store_dwordx2 [[REG]]
440 define void @add_inline_imm_neg_2_f64(double addrspace(1)* %out, double %x) {
441 %y = fadd double %x, 0xfffffffffffffffe
442 store double %y, double addrspace(1)* %out
446 ; CHECK-LABEL: {{^}}add_inline_imm_neg_16_f64
447 ; CHECK: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0xb
448 ; CHECK: v_add_f64 [[REG:v\[[0-9]+:[0-9]+\]]], -16, [[VAL]]
449 ; CHECK: buffer_store_dwordx2 [[REG]]
450 define void @add_inline_imm_neg_16_f64(double addrspace(1)* %out, double %x) {
451 %y = fadd double %x, 0xfffffffffffffff0
452 store double %y, double addrspace(1)* %out
456 ; CHECK-LABEL: {{^}}add_inline_imm_63_f64
457 ; CHECK: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0xb
458 ; CHECK: v_add_f64 [[REG:v\[[0-9]+:[0-9]+\]]], 63, [[VAL]]
459 ; CHECK: buffer_store_dwordx2 [[REG]]
460 define void @add_inline_imm_63_f64(double addrspace(1)* %out, double %x) {
461 %y = fadd double %x, 0x000000000000003F
462 store double %y, double addrspace(1)* %out
466 ; CHECK-LABEL: {{^}}add_inline_imm_64_f64
467 ; CHECK: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0xb
468 ; CHECK: v_add_f64 [[REG:v\[[0-9]+:[0-9]+\]]], 64, [[VAL]]
469 ; CHECK: buffer_store_dwordx2 [[REG]]
470 define void @add_inline_imm_64_f64(double addrspace(1)* %out, double %x) {
471 %y = fadd double %x, 0x0000000000000040
472 store double %y, double addrspace(1)* %out
477 ; CHECK-LABEL: {{^}}store_inline_imm_0.0_f64
478 ; CHECK: v_mov_b32_e32 v[[LO_VREG:[0-9]+]], 0
479 ; CHECK: v_mov_b32_e32 v[[HI_VREG:[0-9]+]], 0
480 ; CHECK: buffer_store_dwordx2 v{{\[}}[[LO_VREG]]:[[HI_VREG]]{{\]}}
481 define void @store_inline_imm_0.0_f64(double addrspace(1)* %out) {
482 store double 0.0, double addrspace(1)* %out