1 ; RUN: llc -march=r600 -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s
3 declare double @llvm.AMDGPU.trig.preop.f64(double, i32) nounwind readnone
5 ; SI-LABEL: @test_trig_preop_f64:
6 ; SI-DAG: BUFFER_LOAD_DWORD [[SEG:v[0-9]+]]
7 ; SI-DAG: BUFFER_LOAD_DWORDX2 [[SRC:v\[[0-9]+:[0-9]+\]]],
8 ; SI: V_TRIG_PREOP_F64 [[RESULT:v\[[0-9]+:[0-9]+\]]], [[SRC]], [[SEG]]
9 ; SI: BUFFER_STORE_DWORDX2 [[RESULT]],
11 define void @test_trig_preop_f64(double addrspace(1)* %out, double addrspace(1)* %aptr, i32 addrspace(1)* %bptr) nounwind {
12 %a = load double addrspace(1)* %aptr, align 8
13 %b = load i32 addrspace(1)* %bptr, align 4
14 %result = call double @llvm.AMDGPU.trig.preop.f64(double %a, i32 %b) nounwind readnone
15 store double %result, double addrspace(1)* %out, align 8
19 ; SI-LABEL: @test_trig_preop_f64_imm_segment:
20 ; SI: BUFFER_LOAD_DWORDX2 [[SRC:v\[[0-9]+:[0-9]+\]]],
21 ; SI: V_TRIG_PREOP_F64 [[RESULT:v\[[0-9]+:[0-9]+\]]], [[SRC]], 7
22 ; SI: BUFFER_STORE_DWORDX2 [[RESULT]],
24 define void @test_trig_preop_f64_imm_segment(double addrspace(1)* %out, double addrspace(1)* %aptr) nounwind {
25 %a = load double addrspace(1)* %aptr, align 8
26 %result = call double @llvm.AMDGPU.trig.preop.f64(double %a, i32 7) nounwind readnone
27 store double %result, double addrspace(1)* %out, align 8